tag:blogger.com,1999:blog-70737608887412181762024-03-16T02:12:34.816+01:00ESA Space blog - All Rights Reserved RSRed Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.comBlogger245125tag:blogger.com,1999:blog-7073760888741218176.post-46505329728611679942023-07-24T22:06:00.009+02:002023-07-28T10:06:57.269+02:00ZenBleed<div>ZenBleed Parallel Solvent RS 2023</div><div><br /></div>ZenBleed, So what about 64Bit to 128Bit bleed in SiMD? Mind you; 'Bound to be One' 20:20pm 24/07/2023 (c)RS<br /><br />XMM 128Bit YMM 256Bit ZMM 512Bit<br /><br />My theory involves using higher modes for synchronous packing!<br /><br />What do i mean ?<br /><br />When you have a full system (processes), 64Bit Processes start packing 128Bit registers! Particularly with Float units 182Bits...<br /><br />Indeed an olderror is packing 128Bit registers with Float unit (FPU) Values with rollover!<br /><br />So?<br /><br />Two things first positive:<br /><br />We can pack FPU Register Values into 256Bit (and Zero : vzeroupper & tzcnt (Trailing Zero Count)),<br />Enabling us to directly utilise SiMD <> with <> FPU!<br /><br />We can solve the lower XMM to YMM to ZMM differences! How ?<br /><br />We Multiple Array fill the next register with at least 2 values!<br /><br />So ?<br /><br />Parallel processing!<br /><br />How ?<br /><br />XMM-128 | ZMM / 4 or 128 * 4! Parallel!*4 Best!<br /><br />XMM-128 | YMM / 2 or 128 * 2! Parallel!*2 Best!<br /><br />YMM-256 | ZMM / 2 or 256 * 2! Parallel!*2 Best!<br /><br />FPU-182 | YMM or 182 * 1 = Single File FPU <> SiMD | <br /><br />ZMM / 2 or 182+r * 2! Parallel!*2 Best! = Double File FPU <> SiMD<br /><br />r = Remainder for vzeroupper | tzcnt<div><br /></div><div><h4 style="text-align: left;">Parallel Operation Principle with CPU Register & OPS division : RS</h4><br />We will be using the value split: <br /><br />512/2 = 256*2<br />256/2 = 128*2<br />128/2 = 64*2<br />128/4 = 32*4<br /><br />We will therefor be able to use 32Bit, 64Bit, 128Bit , 256Bit, 512Bit values at leasure..<br />But we have to optimise the entire branch to use a single precision!<br /><br />Single Type Precision operations make the effects of C++ Fast-float & Half Precision removed...<br /><br />No operation errors.. & Parallel operation<br /><br />reference (Faster Maths & ML)</div><div><br />(c)Rupert S<div><br /></div><div>< Yes Bug Bounty & Solve Bounty : Bounty Bounty ></div><div><br />https://lock.cmpxchg8b.com/zenbleed.html<br /><br />Vulnerability<br /><br />It turns out that with precise scheduling, you can cause some processors to recover from a mis-predicted vzeroupper incorrectly!<br /><br />This technique is CVE-2023-20593 and it works on all Zen 2 class processors, which includes at least the following products:<br /><br />AMD Ryzen 3000 Series Processors<br />AMD Ryzen PRO 3000 Series Processors<br />AMD Ryzen Threadripper 3000 Series Processors<br />AMD Ryzen 4000 Series Processors with Radeon Graphics<br />AMD Ryzen PRO 4000 Series Processors<br />AMD Ryzen 5000 Series Processors with Radeon Graphics<br />AMD Ryzen 7020 Series Processors with Radeon Graphics<br />AMD EPYC “Rome” Processors<br /><br />Speculation<br /><br />Hold on, there’s another complication! Modern processors use speculative execution, so sometimes operations have to be rolled back.<br /><br />What should happen if the processor speculatively executed a vzeroupper, but then discovers that there was a branch misprediction? Well, we will have to revert that operation and put things back the way they were… maybe we can just unset that z-bit?<br /><br />If we return to the analogy of malloc and free, you can see that it can’t be that simple - that would be like calling free() on a pointer, and then changing your mind!<br /><br />That would be a use-after-free vulnerability, but there is no such thing as a use-after-free in a CPU… or is there?</div><br />RS Spectra Mitigations <a href="https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html">https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html</a><div>ZenBleed Parallel Solvent RS 2023 <a href="https://science.n-helix.com/2023/07/zenbleed.html">https://science.n-helix.com/2023/07/zenbleed.html</a></div><div><br /></div>Core/CPU/GPU security core SSL/TLS BugFix <br /><a href="https://science.n-helix.com/2020/06/cryptoseed.html">https://science.n-helix.com/2020/06/cryptoseed.html</a><br /><a href="https://science.n-helix.com/2019/05/zombie-load.html">https://science.n-helix.com/2019/05/zombie-load.html</a><div><br /></div><div>Secure Configuration:<br /><a href="https://is.gd/SSL_NetSecurity_NTP_PTP">https://is.gd/SSL_NetSecurity_NTP_PTP</a><br /><a href="https://is.gd/EthernetTunnelOpt">https://is.gd/EthernetTunnelOpt</a><br /><a href="https://is.gd/SSL_Optimise">https://is.gd/SSL_Optimise</a><br /><br />PTP & NTP Improve security WW <a href="https://is.gd/PTP_TimeStream">https://is.gd/PTP_TimeStream</a></div><div><br /></div>Secure Configuration:<br /><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM</a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a><br /><br />Open Streaming Codecs 2023 <a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a></div><div><br />Vectors & maths<br />https://science.n-helix.com/2022/08/simd.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />Networking & Management<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/02/pm-qos.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2022/01/ntp.html<br /><br />Faster Maths & ML<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Focus on Quality<br />https://science.n-helix.com/2022/09/ovccans.html<br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br /><a href="https://blog.cloudflare.com/zenbleed-vulnerability/">https://blog.cloudflare.com/zenbleed-vulnerability/</a><br /><br />https://www.theverge.com/2023/7/25/23806705/amd-ryzen-cpu-processor-zenbleed-vulnerability-exploit-bug<br /><br /><div><div><div>************* Reportage ><br /><br />Introduction<br /><br />All x86-64 CPUs have a set of 128-bit vector registers called the XMM registers. You can never have enough bits, so recent CPUs have extended the width of those registers up to 256-bit and even 512-bits.<br /><br />The 256-bit extended registers are called YMM, and the 512-bit registers are ZMM.<br /><br />These big registers are useful in lots of situations, not just number crunching! They’re even used by standard C library functions, like strcmp, memcpy, strlen and so on.<br /><br />Let’s take a look at an example. Here are the first few instructions of glibc’s AVX2 optimized strlen:<br /><br /><br />(gdb) x/20i __strlen_avx2<br />...<br /><__strlen_avx2+9>: vpxor xmm0,xmm0,xmm0<br />...<br /><__strlen_avx2+29>: vpcmpeqb ymm1,ymm0,YMMWORD PTR [rdi]<br /><__strlen_avx2+33>: vpmovmskb eax,ymm1<br />...<br /><__strlen_avx2+41>: tzcnt eax,eax<br /><__strlen_avx2+45>: vzeroupper<br /><__strlen_avx2+48>: ret<br /><br />The full routine is complicated and handles lots of cases, but let’s step through this simple case. Bear with me, I promise there’s a point!<br /><br />The first step is to initialize ymm0 to zero, which is done by just xoring xmm0 with itself1.<br /><br />VPXOR xmm0, xmm0, xmm0<br />> vpxor xmm0, xmm0, xmm0<br />vpcmpeqb ymm1, ymm0, [rdi]<br />vpmovmskb eax, ymm1<br />tzcnt eax, eax<br />vzeroupper<br /><br />Here rdi contains a pointer to our string, so vpcmpeqb will check which bytes in ymm0 match our string, and stores the result in ymm1.<br /><br />As we’ve already set ymm0 to all zero bytes, only nul bytes will match.<br /><br />vpcmpeqb ymm1, ymm0, rdi<br />vpxor xmm0, xmm0, xmm0<br />> vpcmpeqb ymm1, ymm0, [rdi]<br />vpmovmskb eax, ymm1<br />tzcnt eax, eax<br />vzeroupper<br /><br /><div>Now we can extract the result into a general purpose register like eax with vpmovmskb.<br /><br />Any nul byte will create a 1 bit, and any other value will create a 0 bit.<br /><br />vpmovmskb eax, ymm1<br />vpxor xmm0, xmm0, xmm0<br />vpcmpeqb ymm1, ymm0, [rdi]<br />> vpmovmskb eax, ymm1<br />tzcnt eax, eax<br />vzeroupper<br /><br />Finding the first zero byte is now just a case of counting the number of trailing zero bits.<br /><br />That’s a common enough operation that there’s an instruction for it - tzcnt (Trailing Zero Count).<br /><br />tzcnt eax, eax<br />vpxor xmm0, xmm0, xmm0<br />vpcmpeqb ymm1, ymm0, [rdi]<br />vpmovmskb eax, ymm1<br />> tzcnt eax, eax<br />vzeroupper<br /><br />Now we have the position of the first nul byte, in just four machine instructions!<br /><br />You can probably imagine just how often strlen is running on your system right now, but suffice to say, bits and bytes are flowing into these vector registers from all over your system constantly.<br /><br />Zeroing Registers<br /><br />You might have noticed that I missed one instruction, and that’s vzeroupper.<br /><br />vzeroupper<br />vpxor xmm0, xmm0, xmm0<br />vpcmpeqb ymm1, ymm0, [rdi]<br />vpmovmskb eax, ymm1<br />tzcnt eax, eax<br />> vzeroupper<br /><br /></div><div>You guessed it, vzeroupper will zero the upper bits of the vector registers.<br /><br />The reason we do this is because if you mix XMM and YMM registers, the XMM registers automatically get promoted to full width. It’s a bit like integer promotion in C.<br /><br />This works fine, but superscalar processors need to track dependencies so that they know which operations can be parallelized. This promotion adds a dependency on those upper bits, and that causes unnecessary stalls while the processor waits for results it didn’t really need.<br /><br />These stalls are what glibc is trying to avoid with vzeroupper. Now any future results won’t depend on what those bits are, so we safely avoid that bottleneck!<br /><br />The Vector Register File<br /><br />Now that we know what vzeroupper does, how does it do it?<br /><br />Your processor doesn’t have a single physical location where each register lives, it has what’s called a Register File and a Register Allocation Table. This is a bit like managing the heap with malloc and free, if you think of each register as a pointer. The RAT keeps track of what space in the register file is assigned to which register.<br /><br />In fact, when you zero an XMM register, the processor doesn’t store those bits anywhere at all - it just sets a flag called the z-bit in the RAT. This flag can be applied to the upper and lower parts of YMM registers independently, so vzeroupper can simply set the z-bit and then release any resources assigned to it in the register file.<br /><br />Z-Bit<br /><br />A register allocation table (left) and a physical register file (right).<br /><br />Speculation<br /><br />Hold on, there’s another complication! Modern processors use speculative execution, so sometimes operations have to be rolled back.<br /><br />What should happen if the processor speculatively executed a vzeroupper, but then discovers that there was a branch misprediction? Well, we will have to revert that operation and put things back the way they were… maybe we can just unset that z-bit?<br /><br />If we return to the analogy of malloc and free, you can see that it can’t be that simple - that would be like calling free() on a pointer, and then changing your mind!<br /><br />That would be a use-after-free vulnerability, but there is no such thing as a use-after-free in a CPU… or is there?<br /><br />Spoiler: yes there is 🙂<br /><br />Zenbleed Demo<br /><br />This animation shows why resetting the z-bit is not sufficient.<br /><br />Vulnerability<br /><br />It turns out that with precise scheduling, you can cause some processors to recover from a mispredicted vzeroupper incorrectly!<br /><br />This technique is CVE-2023-20593 and it works on all Zen 2 class processors, which includes at least the following products:<br /><br />AMD Ryzen 3000 Series Processors<br />AMD Ryzen PRO 3000 Series Processors<br />AMD Ryzen Threadripper 3000 Series Processors<br />AMD Ryzen 4000 Series Processors with Radeon Graphics<br />AMD Ryzen PRO 4000 Series Processors<br />AMD Ryzen 5000 Series Processors with Radeon Graphics<br />AMD Ryzen 7020 Series Processors with Radeon Graphics<br />AMD EPYC “Rome” Processors<br /><br />The bug works like this, first of all you need to trigger something called the XMM Register Merge Optimization2, followed by a register rename and a mispredicted vzeroupper. This all has to happen within a precise window to work.<br /><br />We now know that basic operations like strlen, memcpy and strcmp will use the vector registers - so we can effectively spy on those operations happening anywhere on the system! It doesn’t matter if they’re happening in other virtual machines, sandboxes, containers, processes, whatever!<br /><br />This works because the register file is shared by everything on the same physical core. In fact, two hyperthreads even share the same physical register file.<br /><br />Don’t believe me? Let’s write an exploit 🙂<br /><br />Exploitation<br /><br />There are quite a few ways to trigger this, but let’s examine a very simple example.<br /><br /> vcvtsi2s{s,d} xmm, xmm, r64<br />vmovdqa ymm, ymm<br />jcc overzero<br />vzeroupper<br />overzero:<br />nop<br /><br />Here cvtsi2sd is used to trigger the merge optimization. It’s not important what cvtsi2sd is supposed to do, I’m just using it because it’s one of the instructions the manual says use that optimization3.<br /><br />Then we need to trigger a register rename, vmovdqa will work. If the conditional branch4 is taken but the CPU predicts the not-taken path, the vzeroupper will be mispredicted and the bug occurs!<br /><br />Optimization<br /><br />Exploit Running<br /><br />It turns out that mis-predicting on purpose is difficult to optimize! It took a bit of work, but I found a variant that can leak about 30 kb per core, per second.<br /><br />This is fast enough to monitor encryption keys and passwords as users login!<br /><br />We’re releasing our full technical advisory, along with all the associated code today. Full details will be available in our security research repository.<br /><br />If you want to test the exploit, the code is available here.<br /><br />Note that the code is for Linux, but the bug is not dependent on any particular operating system - all operating systems are affected!<br /><br />Discovery<br /><br />I found this bug by fuzzing, big surprise 🙂 I’m not the first person to apply fuzzing techniques to finding hardware flaws. In fact, vendors fuzz their own products extensively - the industry term for it is Post-Silicon Validation.<br /><br />So how come this bug wasn’t found earlier? I think I did a couple of things differently, perhaps with a new perspective as I don’t have an EE background!<br /><br />Feedback<br /><br />The best performing fuzzers are guided by coverage feedback. The problem is that there is nothing really analogous to code coverage in CPUs… However, we do have performance counters!<br /><br />These will let us know when all kinds of interesting architectural events happen.<br /><br />Feeding this data to the fuzzer lets us gently guide it towards exploring interesting features that we wouldn’t have been able to find by chance alone!<br /><br />It was challenging to get the details right, but I used this to teach my fuzzer to find interesting instruction sequences. This allowed me to discover features like merge optimization automatically, without any input from me!<br /><br />Oracle<br /><br />When we fuzz software, we’re usually looking for crashes. Software isn’t supposed to crash, so we know something must have gone wrong if it does.<br /><br />How can we know if a a CPU is executing a randomly generated program correctly? It might be completely correct for it to crash!<br /><br />Well, a few solutions have been proposed to this problem. One approach is called reversi. The general idea is that for every random instruction you generate, you also generate the inverse (e.g. ADD r1, r2 → SUB r1, r2). Any deviation from the initial state at the end of execution must have been an error, neat!<br /><br />The reversi approach is clever, but it makes generating testcases very complicated for a CISC architecture like x86.<br /><br />A simpler solution is to use an oracle. An oracle is just another CPU or a simulator that we can use to check the result. If we compare the results from our test CPU to our oracle CPU, any mismatch would suggest that something went wrong.<br /><br />I developed a new approach with a combination of these two ideas, I call it Oracle Serialization.<br /><br />Oracle Serialization<br /><br />As developers we monitor the macro-architectural state, that’s just things like register values. There is also the micro-architectural state which is mostly invisible to us, like the branch predictor, out-of-order execution state and the instruction pipeline.<br /><br />Serialization lets us have some control over that, by instructing the CPU to reset instruction-level parallelism. This includes things like store/load barriers, speculation fences, cache line flushes, and so on.<br /><br />The idea of a Serialized Oracle is to generate a random program, then automatically transform it into a serialized form.<br /><br />A randomly generated sequence of instructions, and the same sequence but with randomized alignment, serialization and speculation fences added.<br /><br />movnti [rbp+0x0],ebx movnti [rbp+0x0],ebx<br />sfence<br />rcr dh,1 rcr dh,1<br />lfence<br />sub r10, rax sub r10, rax<br />mfence<br />rol rbx, cl rol rbx, cl<br />nop<br />xor edi,[rbp-0x57] xor edi,[rbp-0x57]<br /><br />These two program might have very different performance characteristics, but they should produce identical output. The serialized form can now be my oracle!<br /><br />If the final states don’t match, then there must have been some error in how they were executed micro-architecturally - that could indicate a bug.<br /><br />This is exactly how we first discovered this vulnerability, the output of the serialized oracle didn’t match!<br /><br />Solution<br /><br />We reported this vulnerability to AMD on the 15th May 2023.<br /><br />AMD have released an microcode update for affected processors. Your BIOS or Operating System vendor may already have an update available that includes it.<br /><br />Workaround<br /><br />It is highly recommended to use the microcode update.<br /><br />If you can’t apply the update for some reason, there is a software workaround: you can set the chicken bit DE_CFG[9].<br /><br />This may have some performance cost.<br /><br />Linux<br /><br />You can use msr-tools to set the chicken bit on all cores, like this:<br /><br /># wrmsr -a 0xc0011029 $(($(rdmsr -c 0xc0011029) | (1<<9)))<br /><br />FreeBSD<br /><br />On FreeBSD you would use cpucontrol(8).<br /><br />Others<br /><br />If you’re using some other operating system and don’t know how to set MSRs, ask your vendor for assistance.<br /><br />Note that it is not sufficient to disable SMT.<br /><br />Detection<br /><br />I am not aware of any reliable techniques to detect exploitation. This is because no special system calls or privileges are required.<br /><br />It is definitely not possible to detect improper usage of vzeroupper statically, please don’t try!<br /><br />Conclusion<br />It turns out that memory management is hard, even in silicon 🙂<br /><br />Acknowledgements<br /><br />This bug was discovered by me, Tavis Ormandy from Google Information Security!<br /><br />I couldn’t have found it without help from my colleagues, in particular Eduardo Vela Nava and Alexandra Sandulescu. I also had help analyzing the bug from Josh Eads.</div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-55097000642175203752023-07-24T11:55:00.007+02:002023-07-25T02:53:10.077+02:003DChiplet Side By Side 3D Magic with 3D Trenching<h4>3DChiplet Side By Side 3D Magic with 3D Trenching 2021-2023</h4>3D Fabric 5800X3D is hard in production but the delivery is the problem so ... i have another proposal,<div><br /></div><div>Called </div><div><br /></div><div><h4 style="text-align: left;">Side By Side 3D Magic (c)Rupert S</h4><br />Yes 3D Chips are good for cache, Simply connecting chiplets does not require 3D or 3D Stacking,<br /><br />Side By Side 3D Magic (c)Rupert S<br /><br />https://science.n-helix.com<br /><br />Has Layered Chip wafer & PCB Board with interweaved wires:<br /><br />Carbon fibers, Copper or aluminum or Iron, Not a problem<br /><br />Through the PCB Chip board, These micro tunnels provide all the PCI & Chip tunnels that a Board could require!<br /><br />Layered micro tunnel imprinted PCB can have 3 wires per layer (crosswise, Diagonal & Ordered form)<br /><br />Additionally tunneling up and down is not a problem for you simply layer a connection point that is welded to the next layer as it is laid on top..<br /><br />Micro film is available, As this is both electrostatic & noise resistant composite.<br /><br />Since this is a micro multiformat PCB / Chip fabric, At no time do you have to worry about dampness or heat split when made well.<br /><br />https://www.youtube.com/watch?v=pBZQeW1eeEw<br /><br />Example of 3D Layered PCB, A but too rigid but good for a phone or telescope Board..<br /><br />Chips can be placed inside if you need to! for space reasons; Embed the chiplet..<br /><br />PCB is ideal for this task; Common view PCB is large space & coy compact?<br /><br />3D PCB is a space saver & 3D Network Ethernet/Chip IO memory ops<br /><br />PCB Wire mesh (internal networks) = - |, PCB Layer = _<br /><br />______(CHIP With Connect)________<br />----------|-----|-----|----|----|-----------------<br />_______\____|___\___\_|___________<br />--------(cooling & IO Chip)--------------<br />_______|__|_______|___|___________</div><div><br /></div><div><br /></div><div>***********</div><br />07:39 23/07/2023 (c)Rupert S<br /><br /><h3 style="text-align: left;">Circuit 3D Print with laser (c)RS</h3><br />While trenching semiconductors work, in space (vacuum) electrical energy transfers through vacuum!<br /><br />So you have to use a resistor material in the trench, this is not impossible if you imbed ceramic formulas with a laser!<br /><br />you can however with this technology go upto 2.7v on 5nm; Because higher voltages are faster & more resistant; this makes sense..<br /><br />The trench (hole) Formatic processor 3D layering technology with:<br /><br />Circuit = C, Trench = \_/ , resistor = r, Circuit in trench = c, raised bit Circuit or resistor = /C\<br /><br />C\r/C C\r/C C\r/C<br /><br />C\_/C C\_/C C\_/C<br /><br />C\_/C C\r/C C\_/C<br /><br />/C\c/C\r/C\r/C\r/C\<br /><br />The challenge of using traditional circuit printing methods in space is that the vacuum can cause the circuit to degrade over time..<br /><br />This is because the vacuum can strip away the electrons that carry current in the circuit.<br /><br />3D laser circuit printing could help to mitigate this problem by creating a very dense and compact circuit. This reduces the surface area of the circuit that is exposed to the vacuum and it helps to protect the circuit from the harsh environment of space.<br /><br />& Also..<br /><br />One of the challenges of using trench & processor circuit methods in space is that electrical energy transfers through vacuum; Which can be difficult in a vacuum.<br /><br />This means that you need to use a resistor material in the trench,<br /><br />It is possible to imbed ceramic formulas with a laser; This could be a promising way to create resistors in/for space.<br /><br />However, 3D laser circuit printing could help to mitigate this problem; As the laser can be used to create a very precise and durable circuit.<br /><br />This technology is meant for the world but also with spatial integrity for deep space & So functionally Rugged/Rigid in use & Function.<br /><br />Additional thoughts on the challenges and potential of 3D laser circuit printing for space applications:<br /><br />Challenges:<br />The vacuum of space can be very harsh on materials, so it is important to use materials that are resistant to radiation and temperature extremes.<br /><br />Potential:<br /><br />3D laser circuit printing could allow for the creation of more complex and efficient circuits.<br /><br />3D laser circuit printing could make it possible to print circuits on-demand; Which could be a major advantage for space missions.<br /><br />It could also be used to create circuits that are more resistant to the harsh environment of space.<br /><br />The lack of gravity can also make it difficult to print precise circuits..<br /><br />(c)Rupert S<br /><br />Application 23/07/2023<br /><br />https://science.n-helix.com/2023/07/3dchiplet.html<br /><br />https://science.n-helix.com/2023/06/map.html<br /><br />https://science.n-helix.com/2023/06/ptp.html<br /><br />https://science.n-helix.com/2023/06/tops.html<br /><br />https://science.n-helix.com/2022/01/ntp.html<div><br /></div><div><br /></div>*********************<br /><br />Tilly Arms; The girl with no arms, sympathetic nerve response & frequency rate : Operation Cyborg RS 2023<br /><br />Tilly Arms; The girl with no arms<br /><br />I think that the arms are very good, But she needs more!<br />Clearly artificial skin in silver would do the trick?<br /><br />I noticed that she has control of them though her stimulated skin.... at the elbow....<br />Now i saw a study that clearly would help....<br /><br />Neurons respond on training to noisy signals- & clear notes+<br /><br />We can clearly get a sympathetic skin monitor to receive the feelings; By listening to skin cell responses ....<br /><br />Now i feel that since a 9v battery stings the tongue; 2volts is about a bit too much right on sweaty skin, So 1.8 is around right? Dr<br /><br />https://www.youtube.com/shorts/pmIoL-Ja_Co<br /><br />Depending upon how much resistance there is in skin, might even help with Lightening & Shocks...<br /><br />RS<br /><br />20:08 23/07/2023 What have we learned; Brain Cells : RS : https://www.youtube.com/watch?v=bEXefdbQDjw<br /><br />Brain Cells respond to:<br /><br />Clear tones : } well to { Entropic Noisy tones }: unwell<br />Clean Image } to [ Entropic Noisy Image }<br /><br />Cell electrode networks begin at 0.75cm for tasks like DOOM<br /><br />Cell inputs are learned,<br />Dynamic connections form to the electrodes & We use logic on the inputs...<br /><br />Here the strategy is to use tones & noise to respond to the doom player in motion.<br /><br />The cell structure is clearly not a problem at 3700 * 4 mm<br /><br />Rupert S<div><br /></div><div>*<br /><div><br /></div><h4 style="text-align: left;">AnPa_Wave - Analogue Pattern Wave Vector SiMD Unit : (c)RS</h4><br />The base symphony is harmony, In other words waveforms; There are a couple of Simple methods that really work:<br /><br />High performance Float values F16, F32, F64, FPU<br /><br />Q-Bit Quantum; All forms of Quantum wave work<br />Radio waves;<br />Light patterns<br />Photon wave patterns; single & multiple<br />Sound hardware; 1 to 3 Bit DAC; Audio conversions; Sample range<br />Analogue chips that work on harmony & frequency<br />SVM Elliptic curve maths<br />Sin, Arc, Tan, Time, Vector<br /><br />In essence Harmony & frequency is the equivalent of Complex Elliptic curve maths<br /><br />A Music note score suffices to specify harmony basics:<br /><br />Waveform shape in 3D<br />Harmony / Disharmony<br />Vibration High / Vibration Low<br />Power High / Power Low<br />Volts High / Volts Low<br />Watts High / Wats Low<br /><br />(c)Rupert S<br /><br />https://science.n-helix.com/2023/07/3dchiplet.html<br /><br />https://science.n-helix.com/2023/06/map.html<br /><br />Wonderful Wave-Pattern Analogue waveforms in meta materials - Pattern recognition in reciprocal space with a magnon-scattering reservoir<br />https://www.nature.com/articles/s41467-023-39452-y.pdf<br /><br /></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-41429025165630571122023-06-26T14:04:00.013+02:002023-08-09T14:32:02.788+02:00Clock & Low Latency Secure NTP, PTP Video & Audio Sync network card (c)RS<h4 style="text-align: left;">Clock & Low Latency Secure NTP, PTP Video & Audio Sync network card (c)RS</h4><br />Data Throughput:PTP,NTP,AES - Programmable logic, Why use this instead of a NIC ? or with a nic, Latency RS 2023-06-14 (c)RS<br /><br />FPGA | FPMG Programmable clocks<br /><br />PTP Official Clock generator,<br />In board multiplier,<br />On Die Cache<br />Precision enhancement Interpolation circuit<br />On Die Network translation, IP6 & IP4 with<br />Output Cache<br /><br />In the case of low latency networking with EEC & Elliptic Curve integrated security:<br /><br />Time clock +<br /><br />Onboard<br />TPM<br />Certificate Cache<br /><br />AES output with certificate (can be static & cached)<br /><br />Output Cache,<br />Security layer & IP Translation layer<br /><br />(c)Rupert S<br /><br />https://www.youtube.com/watch?v=l3pe_qx95E0 1h:00<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2022/10/ml.html<br /><br />https://science.n-helix.com/2023/06/tops.html<br /><br />https://is.gd/LEDSource<br /><br />Clock expander with parallel async gate activation<br /><br /> / |<br />{Clock} |< |<br /> |< |<br /> |< |<br /> |< |<br /> \ |<br /><br /> [C] [E]<br /><br /> / |<br />{Clock} |< |<br /> |< | = [CE]<br /> |< |<br /> |< |<br /> \ |<br /><br />[CE] + Micro [E]<br /><br />Value Large F16, F32, F64 & so forth<br /><br />Interpolator<br /><br />A<br />----- = Fraction<br />B<br /><br />A = 100 - [Fraction] Until B<br /><br />Or<br /><br />100 = [Value]A<br /><br /> 0 = [Value]B<br /><br />100 - [Fraction] (A - B)<br /><br />Rupert S<div><br /></div><div><h4 style="text-align: left;">Reasoning for the network NTP & PTP Audio & Video Sync device</h4><br />The Network card & Devices are designed to provide high-precision synchronization for video and audio applications using NTP and PTP protocols..<br /><br />It features a FPGA-based programmable clock generator that can produce multiple output frequencies and phases with low jitter and high accuracy.<br /><br />The clock generator also supports NTP & PTP official clock functionality, <br />Which allows the network card to act as a master or slave clock in a NTP & PTP network.<br /><br />The network card also has a FPMG circuit that can perform interpolation and scaling operations on the input and output clocks & an on-die cache that can store the clock data and reduce latency.<br /><br />The network card also has a built-in network translation module that can handle both IPv4 and IPv6 protocols, <br />An output cache that can buffer the data packets before sending them to the network.<br /><br />In addition, the network card has a security layer that integrates EEC and elliptic curve cryptography to protect the data transmission.<br /><br />The security layer can also generate AES output with certificates that can be static or cached on the network card.<br /><br />The network card also has a TPM module that can store the certificates and keys securely.<br /><br />The network card is compatible with various video and audio formats and standards, such as Ethernet, Wifi & Radio, HDMI, DisplayPort, SDI, AES3, etc..<br /><br />It can also support JIT compilation and machine learning applications using the resources of the FPGA and FPMG circuits.<br /><br />Research and Development,<br /><br />Rupert S</div><div><br /><a href="https://science.n-helix.com/2023/06/ptp.html">https://science.n-helix.com/2023/06/ptp.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2023/06/tops.html">https://science.n-helix.com/2023/06/tops.html</a><br /><a href="https://science.n-helix.com/2022/01/ntp.html">https://science.n-helix.com/2022/01/ntp.html</a></div><div><br /></div>PTP Server Clock Sync with NTP <a href="https://is.gd/PTP_TimeStream">https://is.gd/PTP_TimeStream</a><div>PTP Server Clock Sync <a href="https://is.gd/PTP_Low_Latency_Time">https://is.gd/PTP_Low_Latency_Time</a><br /><div><br /></div><div>Photo <a href="https://is.gd/NTP_PTPStreamSync">https://is.gd/NTP_PTPStreamSync</a></div><div><br /></div><div>https://is.gd/HPC_PTP_Low_Latency_Network<br /><br />https://www.linuxfoundation.org/press/announcing-ultra-ethernet-consortium-uec<br /><br />https://ultraethernet.org/<br /><br />https://jointdevelopment.org/</div><div><br /></div><div>Secure Configuration:<br /><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM</a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a><br /><a href="https://is.gd/SSL_NetSecurity_NTP_PTP">https://is.gd/SSL_NetSecurity_NTP_PTP</a><br /><a href="https://is.gd/EthernetTunnelOpt">https://is.gd/EthernetTunnelOpt</a><br /><br />PTP & NTP Improve security WW <a href="https://is.gd/PTP_TimeStream">https://is.gd/PTP_TimeStream</a></div>NTP64 Server (run after PTP) <a href="https://is.gd/NTP_Server">https://is.gd/NTP_Server</a><div><br />Open Streaming Codecs 2023 <a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a><h4 style="text-align: left;">The following diagram illustrates some of the possible components and functions of a programmable logic device for data throughput optimization:(c)RS</h4><br />|-----------------| |-----------------| |-----------------|<br /><br />| PTP official | | In-board | | On-die cache |<br /><br />| clock generator |----| multiplier |----| |<br /><br />|-----------------| |-----------------| |-----------------|<br /><br />| | |<br /><br />| | |<br /><br />V V V<br /><br />|-----------------| |-----------------| |-----------------|<br />| Precision | | On-die network | | Output cache |<br />| enhancement |----| translation |----| |<br />| interpolation | | | |-----------------|<br />| circuit | |-----------------|<br />|-----------------|<br /><br />|<br /><br />|<br /><br />V<br /><br />|-----------------|<br />| Time clock |<br />|-----------------|<br /><br />|<br /><br />|<br /><br />V<br /><br />|-----------------|<br />| Onboard TPM |<br />|-----------------|<br /><br />|<br /><br />|<br /><br />V<br /><br />|-----------------|<br />| Certificate |<br />| cache |<br />|-----------------|<br /><br />|<br /><br />|<br /><br />V<br /><br />|-----------------|<br />| AES output with |<br />| certificate |<br />|-----------------|<br /><br />|<br /><br />|<br /><br />V<br /><br />|-----------------|<br />| Security layer |<br />| and IP |<br />| translation |<br />| layer |<br />|-----------------|<br /><br />*****<br /><br />Data Throughput:PTP,NTP,AES Programmable Clock & Event Timer (c)RS<br /><br />One of the challenges of modern network applications is to achieve high data throughput with low latency and high reliability.<br /><br />Data throughput is the amount of data that can be transferred over a network in a given time.<br /><br /><div>Latency is the delay between sending and receiving data.<br /><br />Reliability is the ability to maintain data integrity and availability.<br /><br />One way to improve data throughput is to use programmable logic devices, such as field-programmable gate arrays (FPGAs) or field-programmable micro-gate arrays (FPMGs).<br /><br />These devices can be customized to perform specific functions at high speed and efficiency, such as encryption, compression, filtering, routing, etc.<br /><br />Programmable logic devices can also be configured to support different network protocols Such as:<br /><br />Precision Time Protocol (PTP), Network Time Protocol (NTP), and Advanced Encryption Standard (AES).<br /><br />PTP is a protocol that synchronizes the clocks of different devices on a network.<br /><br />It is used for applications that require precise timing and coordination, such as industrial automation, test and measurement, and telecommunications.<br /><br />PTP can achieve sub-microsecond accuracy over Ethernet networks.<br /><br />NTP is a protocol that synchronizes the clocks of different devices on a network.<br /><br />It is used for applications that require moderate accuracy and stability, such as web servers, email servers, and databases.<br /><br />NTP can achieve millisecond accuracy over Ethernet networks.<br /><br />AES is a standard for symmetric-key encryption.<br /><br />It is used for applications that require data security and confidentiality, such as banking, e-commerce, and government.<br /><br />AES can encrypt and decrypt data with 128-bit, 192-bit, or 256-bit keys.<br /><br />Programmable logic devices can be used instead of or with network interface cards (NICs) to improve data throughput.<br /><br />NICs are hardware components that connect a device to a network.<br /><br />They are responsible for sending and receiving data packets over the physical layer of the network.Programmable logic devices can be integrated with NICs or replace them entirely, <br /><br />depending on the application requirements.<br /><br />For example: <br /><br />A programmable logic device can be used as a PTP official clock generator providing a reference time for other devices on the network.<br /><br />It can also implement an in-board multiplier, which increases the clock frequency of the device.<br /><br />Additionally, it can have an on-die cache, which stores frequently used data for faster access.<br /><br />A programmable logic device can also perform precision enhancement interpolation circuitry; Which improves the accuracy of the clock signal by interpolating between two adjacent clock pulses.<br /><br /> Furthermore, it can have an on-die network translation unit, which converts between different network protocols, such as IPv6 and IPv4.<br /><br />Moreover, It can have an output cache, which buffers the outgoing data packets for smoother transmission.<br /><br />In the case of low latency networking with error correction code (ECC) and elliptic curve integrated security, a programmable logic device can also provide additional features.<br /><br />For example, a programmable logic device can have a time clock module that synchronizes with the PTP official clock generator.<br /><br />It can also have an onboard trusted platform module (TPM), Which provides hardware-based security functions..<br /><br />Such as key generation and storage.<br /><br />Additionally, it can have a certificate cache; Which stores digital certificates for authentication and encryption.<br /><br />A programmable logic device can also perform AES output with certificate verification.. <br /><br />Which encrypts the data packets with AES and attaches a digital signature for integrity checking.Furthermore, <br /><br />It can have a security layer and an IP translation layer, <br /><br />Which provide additional protection and compatibility for the data packets.<br /><br />Some of the possible components and functions of a programmable logic device for data throughput optimization.<br /><br />(c)Rupert S</div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-11055406988796172842023-06-23T23:13:00.121+02:002024-02-07T05:19:02.757+01:00[M.A.P] [=====] [H.P.C] - Matrix Array Processor Unit (c)RS<h4 style="text-align: left;">Matrix Array Processor Unit (c)RS</h4><div><br /></div>[M.A.P] [=====] [H.P.C] - Matrix Array Processor Unit (c)RS<div><br /></div><div>*<br />The M.A.P Processor is ideal as a Tensor Unit, For Small Array Solving; Such as MP3, MP4 & AC4 3D Audio, <br />The Base Map is simply to Fit a large static conversion M.A.P into the device, <br />For example a 32Bit Audio Sample Pluse 3D Layer for Bluetooth would simply be around 64Bits for Stereo 32Bit Audio MP4; Plus 32Bits for the 3D Map, <br />The M.A.P Process is not static; But you stick to the maths you wanted. <br /><br />In parallel instructions, one calls interrupts if bad; IRQ & DMA Notes if you want to have better performance, <br />But in a processor Internals you have to call the main loops in your App; & OS Task Instruction cache..</div><div><br /></div><div>Instruct The loop; Don't Interrupt; Stop, Look, Listen! Look, Slowdown, Showtime!<br /><br />Integer instructions multiple parallel example of The principle of, <br />M.A.P is based on wide multiple instructions, This suites AVX & SiMD, <br />Particularly in 16Bit Multi Parallel Instruction Mode<br /><br /></div><div>Rupert S</div><div><br /></div><h4 style="text-align: left;">Soft Interrupt IRQ: Faster CPU Cycles: RS</h4><div>A Soft Interrupt is where you direct the interrupt register to a compiled Code Block..<br />The code block handles the Wait Queue in a gentle way that allows processing to continue & Ram to be accessed..</div><div><br />While the HDD directly writes the IRQ messages to the Code Block; The Code block is below the size of Cache on the Processor..<br /><br />In advanced scenarios the Soft Int Caches Read/Write in RAM while Directing DMA & R/W Cached Cycles; Good Bioses & Software do this.<br /><br />But in a processor Internals you have to call the Main Micro loops (Soft Int) in your App; & OS Task Instruction cache.<br /><br />RS<br /><br />Interrupts particularly effect the Processor functions such as.. <br />Machine Learning Load & Store of Frames, Also the internet..<br />In such as Network cards offloading is often required to handle interrupts..</div><div><br /></div><div>*<br /><br /><h4 style="text-align: left;">VPDM-ST-LRS : Verified Processor Direct Memory Space Transactions Load, Register & Save (c)RS</h4><br />In Concurrence with DM-TCP & DM-UDP & DM-Quicc Soft Interrupt IRQ<br /><br />https://www.phoronix.com/news/Linux-Device-Memory-TCP<br /><br />For SI-IRQ to safely directly write RAM for a SiMD & CPU/TPU; The following protocol is observed:<br /><br />1 DMA Memory Management Processor, Device Bios/PCI Bus & Network Chipset/Network card..<br />Shall directly code check incoming traffic; But shall not void EEC Mode error check...<br /><br />Bear in mind that AES, Common TLS & Packet Compression are in effect!<br />So you shall be using Networking features directly through the Transparent H.D.L Hardware Device Layer...<br /><br />In effect the MMU & Network adapter transparently offload directly to Device Topography RAM & Cache!<br /><br />2 The network card Certifies transactions & offloads security to internal features; Main Certification is still TPM & HMS.<br /><br />3 You can handle directly to Processor of memory space matches internet Bit-depth; However this is usually 32Bit as with IP4 & 64Bit with IP6..<br /><br />4 So the MMU & Network chipset work in sync; EEC, Security, TLS, M.S.T: Memory Space Translation...<br /><br />5 VPDM-ST-LRS : Verified Processor Direct Memory Space Transactions Load, Register & Save (c)RS<br /><br />So to be clear Automated Load, Register & Save Networking; Yes,<br />Device Low Level Firmware Translation Transactions; Yes<br />Processor Direct Memory Space Transactions; No, With Verification? Yes</div><div><br /></div><div>To stop per Frame IO being a high cost transport processing; We process the entire frame per In/Out,<br />The same with TCP/UDP/Quicc; We process per whole Bit; For example 192Bits (SSL,AES), <br />Packet containment & control protocols; Mainly because Half packets caused inefficiency!</div><div><br />Rupert S<br /><br />https://science.n-helix.com/2023/02/pm-qos.html<br /><br />https://lore.kernel.org/dri-devel/20230710223304.1174642-1-almasrymina@google.com/</div><div><br /></div>https://is.gd/HPC_PTP_Low_Latency_Network<br /><br />https://www.linuxfoundation.org/press/announcing-ultra-ethernet-consortium-uec<br /><br />https://ultraethernet.org/<br /><br />https://jointdevelopment.org/<div><br /></div><div>*</div><br /><h4 style="text-align: left;">Embedded Hardened Pointer Table Cache for 3D Chips : RS</h4><br />Based on PCI Edge RAM, Internal Loop Dynamic RAM; With internalised DMA Memory transfers..<br /><br />In the process the feature has the ability to set a page table; 1MB, 2MB, 4MB, 16MB > 1TB,The Ram can be internally written to without invoking ALU or OS,<br /><br />Pages are allocated; The GPU is an example; Physical pages are allocated in RAM that is directly Set by OS & Firmware/ROM Parameters...<br /><br />Internal access to the RAM is set within the page allocation set, But all internal mapping & paging is done directly & though ALU & Memory Management Unit MMU.<br /><br />With 1MB Cache set aside per feature; Not entirely unreasonable these days...<br /><br />Most if a process such as SiMD can be carried out on internal loops..<br /><br />Depending on Cache/RAM Space; Based on PCI Edge RAM<br /><br />Internal DataSet Size based on Dynamic RAM Variable; That is set per USE &Or Per Settings or application,<br /><br />That being said; RAM Allocations best be per session & directly after Setting is changed on reboot or refresh, Load & unload cycling.<br /><br />Rupert S<br /><br />*<div><br /></div><div><h4 style="text-align: left;">Gather/Scatter Microcode no-overload ALU or Data/Code Cache, Just L3/RAM</h4><br />When we look at the Instructions of the SiMD; We could see potential in them to further improve the Gather/Scatter Instructions; Although it has to be said that the instructions are well optimised!<br />Like many pre-Fetching Assembly code for earlier years they are well created & quick!<br /><br />But we can do several things with them; So what ?<br /><br />We can directly fetch the Cache in the code & Link to cache locations using linking (if we have enough & we do at L3/L2)<br /><br />We can make a Hardlink table in cache(L3) for load and save processing (64Kb, Including header)<br /><br />We can directly invoke pre-fetch with a system call (With SoftLink Pointer Tables)<br /><br />We can incache modify (if a directive is singular in a chain of a, b, c, d)<br />We can individually SysCall a direct load of a single {a, b, c, d) statement & not reload it all...<br /><br />For this we need a matrix table in L3 RAM; We can do this if we keep the table under 512KB,<br />But we do not intend to be selfish & RAM is fast these days! So we can directly load a single matrix Element {a, b, c, d} & not refresh the loading cycle for the code...<br /><br />Thus we do not have to overload ALU or Data/Code Cache, Just L3/RAM<br /><br />Rupert S<br /><br /><br />*<br /><h4 style="text-align: left;">Temporary HardLinking in Prefetching Matrix instructions,</h4>Gather/Scatter operations of localised random scattering of information to ram & retrieval<br /><br />Gather<br />for (i = 0; i < N; ++i)<br /> x[i] = y[idx[i]];<br /><br />Scatter<br />for (i = 0; i < N; ++i)<br /> y[idx[i]] = x[i];<br /><br />Firstly i read statistical gathing & Seeding; Pre-Fetching is a method of anticipating & preloading data,<br />So what do i want to do ? In Vector Matrix Prefetch Logical Gather<br /><br />Potentially i would like to use:<br /><br />Softlink (ram retrieval & multiple value)<br />HardLink (maths)<br />Prefetching logic {such as, <br /><br />Run length prefetching, <br />Follow & Forward loading Cache, <br />Entire instruction load & Timing Pre-fetch & Statistic for Loop time & load frequency<br />}<br /><br />So on any potential layout for SiMD Matrix a most likely configuration is:<br /><br />A B C : FMA<br />A B = C : Mul or ADD<br /><br />So a logical statement is, A, B Gather/Seed C; Directly logical AKA Prefetch<br />A B C D; Logical fields of prefetch are localised to parameter...<br /><br />Only likely to draw data from a specific subset of points,<br />Byte Swapping is obviously A1 B1,2,3<br /><br />Most specifically if the command is a hardlink With A B C; Then most likely Storage is directly linked; Like a HardLink on a HDD in NT,<br /><br />The hard link is direct value fetching from a specific Var table & most likely a sorted list!<br />If the list is not sorted; We are probably sorting the list..<br /><br />If we do not HardLink data in a matrix (Example):<br /><br />Var = V+n, Table<br /> a b c d<br />1[V1][V1][V1][V1]<br />2[V2][V2][V2][V2]<br />3[V3][V3][V3][V3]<br />4[V4][V4][V4][V4]<br /><br />A Matrix HardLink is a temporary Table specific logical reading of instructions & direct memory load and save,<br />Registers {A,B,C,D}=v{1,2,3,4}..<br /><br />Directly read direct memory table logic & optimise resulting likely storage or retrieval locations & Soft Link (pointer table)</div><div><br /></div><div>Solutions include multiple Gather/Scatter & 'Gather/Scatter Stride' Cube Block multi load/save..<br />Logical Cache Storage History Pointer Table, Group Sorted RAM Save/Load by classification {A,B,C,D}=v{1,2,3,4}<br />When X + Xa + Xb + Xc, When Y + a b c, When Y or X Prefetch Pointer Table + Data { a, b, c }<br /><br />Example Gather/Scatter logical multiple<br /><br />var pointer [p1] {a ,b, c, d} <br />var pointer [p2] {1 ,2, 3, 4} <br /><br />Gather<br />for (i = 0; i < N; ++i)<br /> x[i] = y[idx[i]];<br />fetch y {p1, p2}; {a, b, c, d}:{1 ,2, 3, 4} <br /><br />Scatter<br />for (i = 0; i < N; ++i)<br /> y[idx[i]] = x[i];<br />send x {p1, p2}; {a, b, c, d}:{1 ,2, 3, 4}</div><div> <br />Rupert S : Reference https://en.wikipedia.org/wiki/Gather/scatter_(vector_addressing)<br /><br />*<div><br /></div><div><div>FMA is a Matrix SiMD feature & is common to ARM & AMD, CPU & GPU</div><div><br /></div><div>Phone SIM cards can use FMA for GSM network acceleration,</div><div><br /></div><div>We can use FMA fused MUL ADD for elliptic curve encryption to multiple Time * curve & ADD AES encryption in the form of time model & 3D dimensions,</div><div><br /></div><div>Therefore we can use FMA to calculate the room area & add audio reverberation matrix as volume levels over time..</div><div><br /></div><div>FMA as a basic GPU..</div><div><br /></div><div>We can convert adder & fused MUL ADD ML,</div><div><br /></div><div>Use all 3 types on integer function of CPU & internal GPU on echo dot type device's with internal GPU and CPU.. FPGA design.</div><div><br /></div></div><div>Rupert S</div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Pre-Fetching; Statistically Ordered Gather/Scatter & The Scatter/Gather Commands</h4><br />(SiMD) The gather/scatter commands may seem particularly random?<br />But we can use this in machine learning:<br /><br />Gather<br />The equivalent of Gathering a group of factors or memories into a group & thinking about them in the context of our code! (our thought rules),<br /><br />Scatter<br />Now if we think about scatter; we have to limit the radius of our through to a small area of brain matter (or ram)... Or the process will leave us "Scatter-Brained"<br /><br />Statistical Pre-Fetching:<br /><br />Ordered Scatter<br />When you know approximately where to scatter<br /><br />Ordered Gather<br />Where you know approximately where to gather<br /><br />Free Thought<br />So now we can associate scatter & gather as a form of free thought? Yes but chaotic...<br />So we add order to that chaos! We limit the scattering to a single field.<br /><br />Stride<br />Stride is the equivalent of following a line in the field; Do we also gather &Or Scatter while we stride ?<br />Do we simply stride a field?<br /><br />Now to answer this question we simply have to denote motive!<br />In seeding we can scatter; Will we do better with an Ordered Scatter ? Yes we could!<br /><br />Statistically Ordered Gather/Scatter & The Scatter/Gather Commands<br />Pre-Fetched<br /><br />Rupert S<div><br /></div>*</div><div><br /></div><h4 style="text-align: left;">Multi-line Packed-Bit Int SiMD Maths : Relevance HDR, WCG, ML Machine Learning (Most advantaged ADDER Maths)</h4><br />The rules of multiple Maths with lower Bit widths into SiMD 256Bit (example) 64Bit & 128Bit & 512Bit can be used<br /><br />In all methods you use packed bits per save, so single line save or load, Parallel, No ram thrashing.<br /><br />You cannot flow a 16Bit block into another segment (the next 16Bit block)<div><br /></div><div>You can however use 9 bit as a separator & rolling an addition to the next bit means a more accurate result!<br />in 32Bit you do 3 * 8bit & 1 * 4Bit, in this example the 4Bit op has 5 Bit results & The 8Bit have 9Bit results..<br />This is preferable!<br /><br />2Bit, 3Bit, 4Bit Operation 1 , 8Bit Operations 3: Table<br /><br />32Bit<br />4 : 1, 8 : 3<br /><br />64Bit<br />4 : 2, 8 : 6<br />2 : 1, 7 : 8<br />3 : 1, 8 : 1, 16 : 3<div><br /></div>Addition is the only place where 16Bit * 4 = 64Bit works easily, but when you ADD or - you can only roll to the lowest boundary of each 16Bit segment & not into the higher or lower segment.<br /><br />A: In order to multiply you need adaptable rules to division & multiply<br />B: you need a dividable Maths unit with And OR & Not gates to segment the registered Mul SiMD Unit..<br /><br />In the case of + * you need to use single line rule addition (no over flow per pixel)..<br />& Either Many AND-OR / Not gate layer or Parallel 16Bit blocks..<br /><br />You can however painful as it is Multi Load & Zero remainder registers & &or X or Not remainder 00000 on higher depth instructions & so remain pure!<br /><br />8Bit blocks are a bit small and we use HDR & WCG, So mostly pointless!<br /><br />We can however 8Bit Write a patch of pallet & sub divide our colour pallet & Light Shadow Curves in anything over 8Bit depth colour,<br /><br />In the case of Intel 8Bit * 8 Inferencing unit : 16 Bit Colour in probably (WCG 8 * 8) + (HDR 8 * 8) Segments,<br /><br />In any case Addition is fortunately what we need! so with ADD we can use SiMD & Integer Today.<br /><br />Rupert S<br /><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a><div><br /></div><div><a href="https://science.n-helix.com/2021/11/parallel-execution.html">https://science.n-helix.com/2021/11/parallel-execution.html</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">M.A.P NPU Matrix Processor Dimensional construct (c)RS</h4><br />Primary reason for expansion of function data sets: 2D, 3D,< nD<br /><br />P.D.C is a worker thread parallel 2D or 3D Grid,<br />Utilising QQ & A, B,C Array maths allows us to collapse or expand dimensions in a flexible way,<br /><br />The same principles as SVM (S.V.M SiMD Vector matrix) can be used to culminate or expand dimensions...<br /><br />That way a M.A.P Processor can expand or collapse all mathematical constructs,<br />We can therefore use all mathematical & statistical arrays for machine Learning & Maths.<br /><br />RS<div><br /></div><div>*<br /><br />The Subject of 4x4 tables, <br /><br />We are obviously looking for more like 16x16 for Physics maths!<br />The matrix processor is a large data set; Divisible into 4x2 & 4x4 & 8x8 groups for execution speedups,<br />Aligned Parallel processing....<br /><br />Aligned Matrix tables need to be larger than 4x4 for Physics & Chemistry; So a matrix processor ideally can at a minimum:<br /><br />Matrix Table<br /><br />x1<br />16x16<br /><br />16/2<br />x2<br />8x8,8x8<br />8x8,8x8<br /><br />8/4<br />x4<br />4x4,4x4<br />4x4,4x4<br /><br />RS<br /><br />*</div><div><br /></div><h4 style="text-align: left;">Matrix Method (c)RS</h4><br />Any GPU & CPU SiMD can do a form of Matrix maths in an Array Parallel Load & Run as consecutive tasks..<br /><br />Like So<br /><br />Matrix Formulas : (c)RS<br /><br />SiMD Array A to X, Usually 8, 16, 32, 64 Parallel Groups<br /><br />Grouped Parallel Runs<br />A 1, 2, 3, N<br />B 1, 2, 3, N<br />to<br />Y 1, 2, 3, N<br />X 1, 2, 3, N<br />Run 1 {A1, B1 to X1, Y1} Run 2+ {A2, B2 to X2, Y2}++ {An, Bn to Xn, Yn}<br /><br />Matrix Processor Method Synchronous Cube Map Usually 8x8, 16x16, 32x32, 64x64 Parallel Quad++ Groups<br /><br />2D:3D Cube<br /> <br />A 1, 2, 3, N<br />B1, 2, 3, N<br />C1, 2, 3, N<br />D1, 2, 3, N<br /><br />Run 1 2D:3D Cube {<br />A 1, 2, 3, N<br />B1, 2, 3, N<br />C1, 2, 3, N<br />D1, 2, 3, N<br />};<br /><br />Run N 2D:3D Cube {<br />A 1, 2, 3, N<br />B1, 2, 3, N<br />C1, 2, 3, N<br />D1, 2, 3, N<br />}<br /><br />Rupert Summerskill<div><br /></div><div>*</div><div><h4 style="text-align: left;">SiMD Matrix maths begins with a 3D graph,</h4><div><br /></div><div>a</div><div>|___c</div><div> \</div><div> b</div><div><br /></div><div>The graphs principal of 3 dimensions; We can use more dimensions but on paper we need to represent dimensions in colours so that all 3 dimensions that we can draw; are represented.</div><div><br /></div><div>In algebra we represent 3+ dimensions with small glyphs next to each letter that represents our maths operation theoretical number.</div><div><br /></div><div>During operation of computation we maintain in memory the specific dimensions interactions and interplay of complex matrix maths.</div><div><br /></div><div>Rupert S</div></div><div><br /></div><div>Numbers example 4D matrix</div><div><br /></div><div><div>I love you 2, I love you 3, I love you 4 the ends of time... To be continued...</div><div><br /></div><div>JN</div></div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Directed Matrix Principle : RS</h4><br />Matrix Principle directed at traditional parallel Integer & SiMD Instruction groups<br /><br />The main problem with 32KB L1 tables is cache filling & domination of CPU/GPU by single program instruction groups..<br /><br />Instruction cache is the primary challenge; Because Instruction cache L1 is commonly 32KB; Data cache 64KB,<br />L2 is 512KB to 4MB; L3 4MB to 16MB (can be more on Epyc)..<br /><br />Optimised instruction groups by instruction, SiMD multiprocessing thread count:<br /><br />Firstly requirements: (32KB instruction Cache L1, 512KB L2, 8MB L3)<br /><br />L1 Instruction Group 32KB<br />L2 running group 512KB<br />L3 RAM & storage direct fetching 8MB<br /><br />8KB core table for group threading,<br />24KB of grouped & Synchronised instructions<br /><br />Data work Groups 512KB L2 / 64 Instruction Group sets (L1 32KB Table), <br />So Main instruction groups from L1 with larger data sets.<br /><br />L3 4MB to 8MB of data & instruction caching load (directed from L1 & funneled into L2)<br /><br />Instructions are cross threaded directly though L3 & L2 synchronised Load, Run & Save,<br /><br />Optimised instruction groups by instruction, SiMD multiprocessing thread count.<br /><br />Rupert S<div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Parallel Arrays : Matrix forms : RS</h4><div><br /></div>Matrix processor is a feature that will be more common & is relatively similar to an Abacus with a multiple array of + & * Operators..<br /><br />Now a Matrix Array is X1 > Xn & Y1 > Yn<br /><br />Commonly an array of 16 x 16 but can be 8 x 8 or 4 x 4,<br /><br />Now we can perform such operations as Relativity & String theory on a lattice & that is very fast!<br /><br />We can also perform these functions on SiMD, AVX in parallel; Such that 256Bit SiMD is 32Bit x 8 Parallel & so forth<br /><br />Parallel<br />a : 64Bit<br />b : 64Bit<br />c : 64Bit<br />d : 64Bit<br /><br />Matrix<br />a1a2a3a4<br />b1b2b3b4<br />c1c2c3c4<br />d1d2d3d4<br /><br />Now we can see that we can perform a matrix operation such as lattice with both SiMD & SiMD-Matrix,<br /><br />We can also see that a Matrix shall & can present our solution & that SiMD can also!<br />But we need Long operation SiMD or many passes to complete our operations; If Larger than our size..<br /><br />We can also therefore most likely..<br /><br />Use AES-NI S Letter Box & SVE & Matrix & SiMD to our advantage for many Lattice operations.<br /><br />Multiplier Matrix Accelerated Encryption, Like i said A Parallel SiMD array may do the same; If all memory arrays are connected by a single RAM/Cache ALU Node,<br /><br />As stated Parallel Arrays & Parallel Matrix Arrays.<br /><br />Rupert Summerskill<br /><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br />Bluetooth LE Protocol<br /><a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a><br /><br />*<div><br /><div><h4 style="text-align: left;">Examples of Parallel execution pipeline : Parallel arrays:</h4><br />Crypto lattice, Kyber/ML-KEM, AES : Parallelised Lattices, 8x & 16x Parallel SiMD F16/32/64/128/192/256Bit<br /><br />parameterisation of groups of 4x Parallel SiMD F16 & 8x Parallel SiMD F16<br /><br />Parallelised motion & Video/Audio Deblocking/Blocking<br /><br />8x8 16x16 quantification of video is common in VVC & H265 & H264 & JPEG & MP3, MP4a & AAC,<br />Suggested parameterisation of 4x Parallel SiMD F16<br /><br />8x8 16x16 quantification of video is common in HDR VVC & H265 & H264 & JPEG & MP3, MP4a & AAC & AC3 & AC4,<br />Suggested parameterisation of 4x Parallel SiMD F32<br /><br />Shapes in motion 2D : 4x per Cube in motion,<br />Shapes in motion 2D : 6x per Texture Shaded Cube in motion,<br /><br />Shapes in motion 3D : 6x per Cube in motion,<br />Shapes in motion 3D : 8x per Texture Shaded Cube in motion,<br /><br />RS<br /><br />*<div><h4 style="text-align: left;">Number relativity, Bit precision: RS</h4><div><br /></div><div>In gaming a player has access to palette of 16bit FFFFFFFFFFFFFFFFFFFF.FFFFFFFF BF16 F=16 HEX; In 32bit memory storage.</div><div><br /></div><div>Average gamers recognise maybe 32000 colours directly,</div><div><br /></div><div>Colour rich artist colourist's recognise almost 6000000 colours TOPCloud.</div><div><br /></div><div>Variety is king & queen of experience,</div><div>Artists specialist recognises more colours than a basic gamer or graphics artist in vectors..</div><div><br /></div><div>Matrix maths operations precision is relative to hardware,</div><div>XBox 4bit FFFF, PLAYSTATION 8Bit FFFFFFFF</div><div><br /></div><div>RollINT precision 1 to 4 bit + integer -1 to 4 bit F, FFFF, FFF+.F Xbox Or FFFFFFF+.F Ps</div><div><br /></div><div>Bit precision is relative to your experience!</div><div><br /></div><div>Rupert S</div></div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">RollINT - Machine Learning for Console & Computer : RS</h4>With True Value memory/Operation cache...<br /><br />Application of RollINT to machine learning with definition,<br />A Playstation APU has 8Bit Integers for inference; XBox 4Bit..<br /><br />In order to describe 4Bit as float; You would need to define 3Bit & 1Bit R remainder,<br />So how does this work?<br /><br />In loading value the first 3Bit is the value & the 4th bit is remainder & when you load the value stored..<br /><br />You fetch 3Bit as the value & 1 Bit as the remainder; Example:<br /><br />FFFe > Value FFF &R e, So the value is FFF.e not FFFe<br />you can do multiple data type operations in this method; For example:<br /><br />FFde = FF & de or FF.de or you could do Ffde & mean F.fde; Useful for definitions of Pi,<br /><br />For example Pi in 4Bit (8Bits Prefered); Commonly used by kids at school!,<br /><br />However you convert the stored 4Bit Pi to a fully accurate value on FPU & SiMD execution by loading pre-stored true value.<br /><br />RollINT<br /><br />We are using roll to roll a zero on or off an integer,<br /><br />Therefore we are able to divide and multiply and add so that..<br /><br />101-0 > 10.1+0 No can range practically from 0 to 00000000 practically.<br /><br />So 10023-000 > 10.023+000<br /><br />We can then store floating point numbers in integers.<br /><br />(C) Rupert S,<br /><br />Reference Int & FP Value Sizes; A reminder that Floats are 50% of highest Integer Value,<br />ROLLInt floats still have an amazing additional value!<br /><br />https://learn.microsoft.com/en-us/dotnet/standard/numerics<div><br /></div>*<br /><br /><h4 style="text-align: left;">RollINT : The Float Perfectionist</h4><br />Playstation & XBox are primary examples where the Int8 unit could do a RollINT Floating point operation for machine learning that is specific to float FPU Solves, <br /><br />Edge detection, Sharpening & Adaptive Contrast & Colour HDR.. <br /><br />Depending if you directly roll on SiMD & FPU then you can still sharpen with the bF16 & half precision FPU/SiMD Maths operations on the final run! <br /><br />Imagine Luke SkyWalkers final Torpedo Salvo as FPU/SiMD Vectors DT<br /><br />RS<div><br /></div><div>*</div><div><br /></div><div><h4 style="text-align: left;">Scaler is an argument for the role of RollINT & also a pointer to method</h4><br />RollINT : A Float view of machine learning,<br />Essentially the core issue is the role float may play in a result...<br /><br />Not the human mind does use a common integer format with a small float remainder?<br />Potential for this configuration is mainly because Integer values are in the main Substantive information..<br /><br />Float value (the sub decimal place below 0.); Is in essence a precise small value of high importance to skills such as jumping, Running, Motions & skill actions like shooting..<br /><br />Integer is the majority of action related to large steps; Particularly because people have the capacity to change from Meter to Centimetre to Millimetre, <br /><br />Justifications for Float values diminish if you have scalar units such as the meter, the Yard, foot, Inch & 16th!<br /><br />However; As may be pointed out, Roll Scalar? Is a form of floating unit expression; If Scalar measurements are regarded in terms of static's; Then Yes Integer:{Meter; FPU:{cm, mm} is a float value!<br /><br />Nonetheless Scaler is an argument for the role of RollINT & also a pointer to method..<br /><br />Scaling you see; is everything to detail; If you want to see this? Magnify or Zoom & Wide angle!<br />We further scale; By hitboxing our ML; In other words by training the AI on Centric value rewards..<br /><br />AI Content:<br /><br />{Content value reward targets};<br />{Centric Core values};<br /><br />Return = Value;<br />end = infinite<br />Test Loop {AI C, End}; Begine<br /><br />Epoches = {Satisfied End}<br /><br />Rupert S</div><div><br /></div><div>*</div><div><br /></div>Float & Integer : RollINT : In Depth Analytics<br /><br />RollINT List<br /><br />Floats with small precision values : RollINT<br /><br />Dreams have 'Small Randoms', Minor details make a true reality<br /><br />(OS & Chrome Example)<br />The size of frames & text alignment<br />Main colour groups for desktop & browser colours : FFFFFF.FF<br />Frames forward & backward with submenus are worthy of low precision floats : FFF.F 300 Frames 16 sub allocated positions inside frame:{SubFrame}<br /><br />Both low & high precision<br /><br />High Efficiency ZLib, GZip Ram compression<br />Localised Error correction<br /><br />Colour depth & contrast HDR, Low error rate/Higher<br /><br />RS<div><br />*</div><div><br /></div>RollINT Versus Metric principle of float reduction : RS<div><br /></div><div>Scale correctly & avoid that FPU being needed<br /><br />Scale correctly first; Example mouse is Millimetre & Micrometre & Large scale Centimetre,<br />Photon Microscope is Picometre, Milimetre, Centimetre,<br />Telescope is Kilometer, Metre, Milimetre..<br />Screens UpScale & Zoom, Do we need to rescale our measurement ?<br /><br />https://learn.microsoft.com/en-us/dotnet/standard/numerics<br /><br />X+- , Y+- 2D+- central point measurements<br />Int16 2 -32,768 32,767<br />Int32 4 -2,147,483,648 2,147,483,647<br />Int64 8 -9,223,372,036,854,775,808 9,223,372,036,854,775,807 (might want to use floats; A lot quicker)<br /><br />Precision Floats<br />16Bit Half 2 ±65504 <br />32Bit Single 4 ±3.4 x 1038<br />64Bit Double 8 ±1.7 × 10308</div><div><br /></div>The main attack Vector being mice & touchscreens & utility scopes & measuring devices...<br />We wanted DPI without stress!<div><br /></div><div>A range of options exist when using RollINT; The idea is to Roll a float on operation; To be fair hardware like the Amiga has the concept of Integer operation with a float as the final result..<br /><br />However that option Is "the Final result" & does not mean that you could use RollINT to make a repeated Float maths for applications..<br /><br />However RollINT could be used 2 Significant ways: <br /><br />You could use FPU on the result (Previous integer operations save FPU for other tasks)<br />You could receive an Integer result from the float operation (Final float value on multiple operations not important to you?)<br /><br />Perform Metrification & therefor avoid float value use; for example expand the data into a higher precision mode,<br /><br />The principle of the Metric system is to use sub parts to reduce the necessity of floats : Meter, Centimetre, Milimetre, KG, Gram, Ounce..<br /><br />So avoiding a floating unit..<br /><br />The method is multiple operations, Large, Small, Smaller & can in reality be repeated down to picometer or tiny weights...<br /><br />This method is multiple operation rounds,<br /><br />RollINT & FPU Avoid rounds of CPU Cycles; But options exist.<br /><br />RS<div><br /></div><div>*<br /><div><div><div><br />As you know the Matrix Array Processor is now frequent with Intel, Mac M1 & M2, AMD & NVidia Versions..<br /><br />Quantum computers rely on Multi-Directional & Multi-Dimensional Arrays per Qbit!<br /><br />Well this is a design structure for a Multi-Array Multi-Connection Matrix Array Processor..<br /><br />The principle is basically quite logical!<br /><br />Multi-Array Multi-Connection Matrix Array Co-Processor - Quanta Light Compute 2023-06-23<br /><br />Percentage based 3D Processing to handle all 3D Array processing,<br /><br /><div>Central [H.P.C] Tasks map to probability over Networks [=====] & [M.A.P] Units in arrays<br /><br />Table define <br /><br />{ <br /><br />[M.A.P] = M.A.P , M.A.P 8 Way interconnect, <br />[H.P.C] = M.A.P High Precision Central Core, <br />[=====] = Buss Connections & networking <br /><br />}<br /><br />Top View<br /><br />[M.A.P][M.A.P][M.A.P]<br />[M.A.P][H.P.C][M.A.P]<br />[M.A.P][M.A.P][M.A.P]<br /><br />Side View 3D<br /><br />[M.A.P][H.P.C][M.A.P]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br /><br />Each [H.P.C] Central Contains RAM & connections to the 8 [M.A.P] & Optionally to layers above & bellow in 3D Matrix,<br />Bottom of wafer contains high resolution buss to onboard controllers & networks & DPU/GPU/CPU's<br /><br />Array = Matrix Array Processor Unit (c)RS<br /><br />ffffffff ffffffff ffffffff<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br /><br />f=fp,unit<br />*=mul<br />+=add<br />.=Cache/Ram</div><div><br /></div><div>Simple absolver table for MUL:ADD : MUL* Only = +0, +- Only = N*1 then +-<br />% = / 100 + ADD Table {N1 <> N...} : Result!</div><div><br />(c)Rupert S</div><div><br /></div><div><h4 style="text-align: left;">SiMD:CMA (c)RS</h4><br />Standard SiMD Features, Byte Swap, ADD,MUL[SSimd]<br />8 x Cache,Mul,ADD: [8xCMA]<br /><br />[SSimd]<br />[8xCMA][8xCMA][8xCMA][8xCMA]<br /><br />[SSimd] is additional features accessed by register poke, Standard Operation is CMA & RAM<br />[8xCMA] is used as RAM in most SiMD Operations & MUL+ADD, ADD, MUL<br /><br />In SiMD Ops<br />On RAM upto 3x F16 can be stored (3xF16, F32 + F16, F48, F24x2)<br /><br />MUL or ADD Operations can be {F16:F16:F16, F32 *+- F16, F24 *+- F24}<br />Operations are saved to Master Cache & sent to RAM or other functions & can be {F16, F24, F32, F48},<br />Because master cache is a full buffer; you have to save it first! before reuse!<br /><br />Design uses the M.A.P basic MUL+ADD & RAM<br /><br />(c)Rupert S<br /><br />References: DOT4, INT8, INT16, F16, F32, F64 (c)Rupert S</div><div><br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br /><br /><a href="https://science.n-helix.com/2023/06/ptp.html">https://science.n-helix.com/2023/06/ptp.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2023/06/tops.html">https://science.n-helix.com/2023/06/tops.html</a><br /><a href="https://science.n-helix.com/2022/01/ntp.html">https://science.n-helix.com/2022/01/ntp.html</a></div><a href="https://science.n-helix.com/2023/02/pm-qos.html">https://science.n-helix.com/2023/02/pm-qos.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2023/07/3dchiplet.html">https://science.n-helix.com/2023/07/3dchiplet.html</a><br /><div><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a><br /><a href="https://science.n-helix.com/2021/02/multi-operation-maths.html">https://science.n-helix.com/2021/02/multi-operation-maths.html</a><br /><a href="https://science.n-helix.com/2021/11/parallel-execution.html">https://science.n-helix.com/2021/11/parallel-execution.html</a><br /><a href="https://science.n-helix.com/2022/12/math-error-solve.html">https://science.n-helix.com/2022/12/math-error-solve.html</a><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br />Sparse matrix multiplication in SRM array<br /><a href="https://www.science.org/doi/10.1126/sciadv.adf7474">https://www.science.org/doi/10.1126/sciadv.adf7474</a><br /><br />Error Correction Options & Mitigation<br /><a href="https://futurism.com/ibm-breakthrough-quantum-computing">https://futurism.com/ibm-breakthrough-quantum-computing</a></div><div><br /></div>Nx-DeepMatrix Engines<br /><a href="https://www.nextplatform.com/2023/08/02/unleashing-an-open-source-torrent-on-cpus-and-ai-engines/">https://www.nextplatform.com/2023/08/02/unleashing-an-open-source-torrent-on-cpus-and-ai-engines/</a><br /><a href="https://idstch.com/geopolitics/next-generation-neuromorphic-chips-bringing-deep-learning-from-cloud-to-iot-edge-devices-and-mobiles/">https://idstch.com/geopolitics/next-generation-neuromorphic-chips-bringing-deep-learning-from-cloud-to-iot-edge-devices-and-mobiles/</a><br /><a href="https://www.backblaze.com/blog/ai-101-gpu-vs-tpu-vs-npu/">https://www.backblaze.com/blog/ai-101-gpu-vs-tpu-vs-npu/</a></div><div><br /></div>Experimental CPU Proof : A proposal for an Open RISC V Processor, Statistical diagrams of function & graphs with function use under load...<br /><a href="https://www.researchgate.net/publication/373403576_Design_of_a_High_Performance_Vector_Processor_Based_on_RISIC-V_Architecture">https://www.researchgate.net/publication/373403576_Design_of_a_High_Performance_Vector_Processor_Based_on_RISIC-V_Architecture</a></div><div><br /></div>ML Batch Matrix MAP in FPGA<br /><a href="https://drive.google.com/file/d/1hdxeK1r8LIhvpn7poOm3MfXmGr9Tq-ni/view?usp=sharing">https://drive.google.com/file/d/1hdxeK1r8LIhvpn7poOm3MfXmGr9Tq-ni/view?usp=sharing</a><div><div><br /></div>ML Compressed Dynamic16bit-8Bit - Hardware-friendly compression and hardware acceleration for ML Transformer<br /><a href="https://aimspress.com/article/doi/10.3934/era.2022192">https://aimspress.com/article/doi/10.3934/era.2022192</a><br /><br />Matrix Processors - Memory & command - All-Digital Compute-In-Memory FPGA Architecture for Deep Learning Acceleration<br /><a href="https://dl.acm.org/doi/pdf/10.1145/3640469">https://dl.acm.org/doi/pdf/10.1145/3640469</a><br /><br />Matrix Processors - Inline Ram & Command { CMD : RAM }:{NET}<br /><a href="https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf">https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf</a><br /><a href="https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/EW2020-Deep-Learning-Inference-AICore.pdf">https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/EW2020-Deep-Learning-Inference-AICore.pdf</a><div><br />***<br /><br /><h4 style="text-align: left;">Cooperative Matrix Math : RS</h4><br />Cooperative Matrix is a Math type where you formulate a Grid of number & math notations & solve them in sync,<br /><br />The consequence for you is that the maths is both Faster; More Complex But also easier to correct for errors...<br /><br />Usually Matrix Maths is used for Algebra, Image & 3D Mapping ML; Such as to see, Maps & Dungeons, Water tables, Technology Development.<br /><br />Matrix</div><div><br /></div><div>Var = V+n, Table</div><div> a b c d</div><div>1[V1][V1][V1][V1]<br />2[V2][V2][V2][V2]</div><div>3[V3][V3][V3][V3]</div><div>4[V4][V4][V4][V4]</div><div><br /></div><div><div>There are 3 main ways for matrix maths:</div><div><br /></div>V1a {/,*,+,-},Value, %, Fraction V1b, V2a, V2b : In effect a dither map or calulation; So connected.<br />Vector groups {V1a<>z} Maths to {V2a<>z} to {V3a<>z} to {V4a<>z} & more ..<br /><br />Sorted by Type of operation example<br />M = Multi Complex Operations In Groups<br /> a b c d<br />1[V1]+[V1]+[V1]+[V1]<br />2[V2]*[V2]*[V2]*[V2]<br />3[V3] / [V3] / [V3]/[V3]<br />4[V4]M[V4]M[V4]M[V4]<br /><div><br /></div></div><div><h4 style="text-align: left;">Refer to : Var = V+n, Table</h4><br />Matrix Accumulator Header Matrix : {MAHM}<br />SiMD Wave : 32, 64 Group with finalised result + ALU : Work Group Wave Matrix : {WGWM}<br />Wave Matrix Accumulator Cube : {WMAC}<br /><br />{MAHM}<br />{WMAC},{WMAC}<br />{WMAC},{WMAC}<br /><br />{MAHM}<br />{WGWM},{WGWM}<br />{WGWM},{WGWM}<br /><br />{MAHM}<br />{WGWM},{WGWM}<br />{WMAC},{WMAC}</div><div><br /></div><div>CTP-HTM : CPU, TPU, Processor Hypervisor Thread Management : RS<br /><br />Parallel Group Threads:<br /><br />Work groups by Aligned by: <br /><br />Work Group Size (aligned by Bit): <br /><br />Memory Range {Half Float, b16Bit,b32Bit, 16Bit,32Bit , Double Float}<br />Aligned Cluster Size, <br />Bit-depth & Length of code<br /><br />The logic is that Parallel Group Threads with the same Code complexity & Size should finish around the same time,<br />They also typically require the same processor priority so that system tasks have Runtime Availability.</div><div><br />RS<br /><br />Guide to Cooperative Matrix Math : RS<br /><br />Base principle of the Matrix & Graph goes beyond Accumulation of numbers..<br />I am reminded by microsofts dev post of Excel & Spreadsheet applications..<br /><br />Yes they Graph/Matrix; But math solves require it! For example the Acidity/Alkaline matrix with Protons & Electrons,<br /><br />However a more sophisticated form is algebra; But you have to simply the Algebra & put that in a table..<br />Einstein, Shrodinger, Physics, Chemestry & DNA By connection...<br /><br />Algebra is the main reason we would use Float : {bF16 <> bF32} {Single Precision <> Double Precision} SiMD,<br />The chief objective is the solve; Complex SiMD offer the answer of flexibility..<br />MUL:DIV ADD</div><div><br /></div><div>Simple absolver table for MUL:ADD : MUL* Only = +0, +- Only = N*1 then +-<br />% = / 100 + ADD Table {N1 <> N...} : Result!</div><div><br />(c)Rupert S<br /><br />Graph Accumulator Multiply ADD - Cooperative Matrix<br /><br /><br />SDK Sample : <a href="https://github.com/ROCmSoftwarePlatform/rocWMMA">https://github.com/ROCmSoftwarePlatform/rocWMMA</a></div><div><br />VK_KHR_cooperative_matrix <a href="https://www.amd.com/en/support/kb/release-notes/rn-rad-win-vulkan">https://www.amd.com/en/support/kb/release-notes/rn-rad-win-vulkan</a><br /><br /><a href="https://registry.khronos.org/vulkan/specs/1.3-extensions/man/html/VK_KHR_cooperative_matrix.html">https://registry.khronos.org/vulkan/specs/1.3-extensions/man/html/VK_KHR_cooperative_matrix.html</a><br /><br /><a href="https://devblogs.microsoft.com/directx/d3d12-work-graphs-preview/#Prerequisites">https://devblogs.microsoft.com/directx/d3d12-work-graphs-preview/#Prerequisites</a><br /><a href="https://devblogs.microsoft.com/directx/agility-sdk-1-711/">https://devblogs.microsoft.com/directx/agility-sdk-1-711/</a><br /><br /><a href="https://gpuopen.com/wmma_benefits_ml_compute/">https://gpuopen.com/wmma_benefits_ml_compute/</a></div><br /><a href="https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme/">https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme/</a></div><div><br /></div><div><a href="https://paperswithcode.com/paper/a-survey-on-deep-learning-hardware/review/">https://paperswithcode.com/paper/a-survey-on-deep-learning-hardware/review/</a><br /><div><br />AMD 23.Q3Pro_HIP #HPC #DirectML MatrixMathOps 'Release unto me the great! Chobokniki' Thine Prayers Answered <a href="https://is.gd/AMD23Q3PRO_HIP">https://is.gd/AMD23Q3PRO_HIP</a><br />Run the .reg after install; Before reboot <a href="https://is.gd/AMDRebarReg">https://is.gd/AMDRebarReg</a><div><br /></div><div><div>*</div><div><br /></div><h4 style="text-align: left;">Inference & FMA De-Block Styles</h4><br />For upscaling matrix: MMX+ & SiMD<br />16x16 Block as used just about in HD, <br />8x8 Blocks Certainly NTSC, PAL, JP_NTSC!, <br />Very usable for deblocking JPG,<br />16x16 & 8x8 is very good for Inferencing active on Scaling & Deblocking..<br /><br />4x4 for main Inference XBox & 8x8 for PS5..<br />XBox can use (4x4)x4 for 8x8 & (4x4)x16 for 16x16; Very powerful!<br />PS5 can use (8x8)x1 or x2 for 8x8 & (8x8)x4 (x8 for additional processing) for 16x16; Very powerful!<br /><br />The table solves common issues with 4Bit & 8Bit direct loading of colour tables of the F16 Types..<br />16Bit is a bit more common in older hardware & luckily quite a lot more flexible!<br />But 8Bit & 4Bit inferencing have a number of uses...<br /><br />Indirect load though F16 Register can work by sideloading the operation; With Inferencing Sub routine coding & Returns,<br />Processing the actual inference but losing data store & returns just information..<br /><br />Sub Routine INT8 & INT4 can: <br />Directly manipulate a small palette; Scoped Palette, <br />Single channel colour or multiple operations.. <br />Load, Store & Save<br /><br />Inference & FMA De-Block Styles List<br /><br />(4x4)x4<br />(4x4)x8<br />(4x4)x16 + processing<br />(4x4)x32 +++ processing<br /><br />(8x8)x4<br />(8x8)x8 + processing<br />(8x8)x16 + processing<br /><br />(16x16)x1 + processing<br />(16x16)x2 ++ processing<br />(16x16)x4 +++ processing</div><div><br /></div><div>8:4Bit Concepts: 65535/255=8Bit 65535/16=4Bit<br /><br />16bit/4bit : 4Bit colour pallet, But we can fraction 16Bit/4bit in essence 16/4! 65535/16; Compression Shapes & Gradients.<br />Polygon, Shadow, Contact<br />Alpha Channel 2Bit, 4Bit<br />Grayscale edge define sharpening<br />Single Colour Edge detect<br />Shape Fill in Alpha 10,10,10,2<br />Xor, Pattern, Shading, Shader, Cull, Shape & Depth Compare after define</div><div><br /></div><div>For when {U, X, Y, Z} = N Expressions <a href="https://is.gd/ForWhen_UXYZ_N">https://is.gd/ForWhen_UXYZ_N</a><br />For when {(A+B/2)} = C Expressions <a href="https://is.gd/ForWhen_ABx2_C">https://is.gd/ForWhen_ABx2_C</a><br /><br />(c)RS</div><div><br />*<div><br /></div><h4 style="text-align: left;">An example use of FMA Cooperative Matrix</h4><br />In the example we use a formula like (U/X²)+(U/Y²)+(U/Z²)<br />Firstly the x²,y²,z² are MUL, So we need a * table or maybe with FMA we can use a (MUL)+0 ?<br />My primary observation is that we can use 2 methods:<br /><br />MUL (U/X²), (U/Y²), (U/Z²) in tables, I suggest 3 * or FMA (MUL)+0<br />Or we can perform tables in order but complete all the MUL operations in Sync & then ADD with FMA,<br />Sync : (U/X²)+(U/Y²)+(U/Z²) to (Un/X²)+(Un/Y²)+(Un/Z²)<br /><br />F1 = First Operation F2 = Second operation R = Result {R1:R3 = R4}<br /><br />F1<br />R1=(U/X²) R2=(U/Y²) R3=(U/Z²)<br />F2<br />R1=+ R2=+ R3 = R4<br /><br />So we have an example where MUL & then ADD is usable; But we could use Synced FMA<br /><br />For when {U, X, Y, Z} = N Expressions <a href="https://is.gd/ForWhen_UXYZ_N">https://is.gd/ForWhen_UXYZ_N</a><br /><br />RS </div><div><br /></div>Brilliant examples of matrix maths<br /><a href="https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-finite-difference-docs-laplacian_part1/">https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-finite-difference-docs-laplacian_part1/</a><br /><br />VXEdDSA & XEdDSA & X25519 & X448<br /><a href="https://signal.org/docs/specifications/xeddsa/">https://signal.org/docs/specifications/xeddsa/</a></div><div><br /></div><div>SiMD-Matrix Maths example - Wave retrieval from quad-polarized Chinese Gaofen-3 SAR image using an improved tilt modulation transfer function<br />https://www.tandfonline.com/doi/full/10.1080/10095020.2023.2239849?src=<br /><a href="https://drive.google.com/file/d/1uN047PvBJhFkcdNJKqx6cBZ9vnAxcjPj/view?usp=drive_link">https://drive.google.com/file/d/1uN047PvBJhFkcdNJKqx6cBZ9vnAxcjPj/view?usp=drive_link</a></div><div><br /></div><div>SiMD-Matrix Maths example D-Waves</div><div><a href="https://drive.google.com/file/d/15iPy-Z24GsbcUdEycOfS1819Fdf0sWoE/view?usp=drive_link">https://drive.google.com/file/d/15iPy-Z24GsbcUdEycOfS1819Fdf0sWoE/view?usp=drive_link</a><div><br /></div><div>*****</div><div><br /></div><h4 style="text-align: left;">High speed Per operation Cycle operations of D R² Pi</h4><br />An (A[diameter]*B²[Pi] : D * R² operation is 2 Cycles, this specialised Arc, Sin, Tan operation can be accomplished a couple of ways in a single cycle,<br /><br />Options table : D R² Pi<br /><br />Firstly by sideways memory load in lower Single Precision to double precision output in a SiMD<br /><br />You need to pre cache R²You can use the same value for R or for D &or both<br />You can pre cache all static D &or R, So you can vary either D or R & single cycle<br />You need to perform 2 operations , Diameter & R² & obviously they are relational!<br /><br />For examples:<br /><br />R = Atom Zink (standard size!) Cache D R<br />You move a compass but the needle is the same size! Cache D<br />You draw faces but the width is the same, Cache D<br />You draw faces but the Shape is the same but size is not! Cache R<br /><br />Rupert S<div><br /></div><div>**********</div><div><h4 style="text-align: left;">How you use FMA, Basic MUL+ADD examples first & then Mul & ADD</h4><br />Firstly in video,<br />MUL a float set A * B + C<br />Video Upscaling basic A:Pixel * B:PixelDiffRightPixel + C:RightPixel,<br />Do that 16 Times per pixel pair and you have 16*Interpolate, So a 16* Data set Wave!<br />You could obviously use a 32* Wave SiMD & do 4x8; So 4 Pixel groups per Wave.<br /><br />So for example you can ADD Log Gama or other simple values, In A * B + C,<br />Pixel Values or whatever, You can use Point float 0.001 for example to do division on floats.<br /><br />For all personal maths that you imagine:<br />Simple absolver table for MUL:ADD : MUL* Only = +0, +- Only = N*1 then +-<br />% = / 100 + ADD Table {N1 <> N...} : Result!<br /><h4 style="text-align: left;">Interpolation & smoothing : </h4>The method i am thinking of is ADD Mul/Div : Edge Left A+B Edge Right = C Center, (A to C)<>(C to A)<br /><br />(A+B)/2 = C<br /><br />Factor A_to_C<br /> 16 Steps<br /><br />Factor C_to_B<br /> 16 Steps<br /><br />*alternatives*<br /><br />((A-C)/16)=F | (F* A over C)=F Step * 16 over Time or distance<br /><br />(Call slope)<br />find 16 Fractions of A To C<br />find 16 Fractions of C to B <br /><br />For when {(A+B/2)} = C Expressions <a href="https://is.gd/ForWhen_ABx2_C">https://is.gd/ForWhen_ABx2_C</a><br /><br />RS</div><div><br /></div><h4 style="text-align: left;">Pixel A to B, Interpolation upscaling</h4><br />from A1 to B16 ADD Difference of A - B<br /><br />Red A1 : 2 : 3 : 4 : 5 : 6 : 7 : 8 : 9 : 10 : 11 : 12: 13 : 14 : 15 : 16B<br />Green A1 : 2 : 3 : 4 : 5 : 6 : 7 : 8 : 9 : 10 : 11 : 12: 13 : 14 : 15 : 16B<br />Blue A1 : 2 : 3 : 4 : 5 : 6 : 7 : 8 : 9 : 10 : 11 : 12: 13 : 14 : 15 : 16B<br /><br />Tables can be 16 Wide & 16 Long to advantage ourselves of Byte aligned F16<br /><br />Pixel A to B, Interpolation upscaling<br /><br />AAA<br />ABA<br />AAA<br /><br />Example<br /><br />R,G,B Value of A<br />R,G,B Value of B<br />RCv = Value per pixel of 16<br /><br />Which is higher RA or RB<br />if RA<br />RA - RB = RC<br />If RB<br />RB - RA = RC<br /><br />RB{1 to 16} repeat +- RCv<br /><br />Sorry about the coding RS<br /><br />Rupert S</div><div><br /></div><div>*</div><br /><h4 style="text-align: left;">FMA AVX Performance table: 2Flops per Cycle per FMA Unit<br />Architecture Fast Instructions for FMA</h4><br />Reference Tables <a href="https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf">https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf</a><br /><br />Operators in C<br />● Arithmetic<br />a + b, a – b, a*b, a/b, a%b<br />● Bitwise <br />a | b, a & b, a ^ b, ~a<br />● Bit shift <br />a << b, a >> b (signed), a >> b (unsigned)<br />● Logical operators <br />a && b, a || b, !a<br />● Comparison operators<br />a == b, a != b, a < b, a <= b, a > b, a >= b<br />● Tertiary operator <br />x = a ? b : c<br />● Special functions:<br />sqrt(x), abs(x), fma(a,b,c), ceil(x), floor(x) <br /><br />Fast division for constant divisors<br /><br />Calculate r = a/b where b is a constant<br />With floating point we precompute (at compile time <br />or outside of the main loop) the inverse ib = 1.0/b.<br />r = ib*a<br />Floating point division with constant divisors <br />becomes multiplication<br />With integers the inverse is more complicated<br /> ib,n = get_magic_numbers(b);<br />r = ib*a >> n<br /><br />Integer division with constant divisors becomes<br />multiplication and a bit-shift<br /><br />Fast Division Examples<br />● x/3 = x*1431655766/2^32<br />27*1431655766/2^32 = 3<br />● x/1000 = x*274877907/2^38<br />10000*274877907/2^32 = 10<br />● x/314159 = x*895963435/2<br />7*314159*895963435/2^48 = 7<br /><br />Dividing integers by a power of two can be done with a bit shift which is very fast.<br /><br />RS</div><div><br /></div><div><a href="https://en.wikipedia.org/wiki/FMA_instruction_set">https://en.wikipedia.org/wiki/FMA_instruction_set</a><br /><a href="https://en.wikipedia.org/wiki/Advanced_Vector_Extensions">https://en.wikipedia.org/wiki/Advanced_Vector_Extensions</a><br /><a href="https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE)">https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE)</a></div><div><br /></div>High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves<br /><a href="https://www.lasca.ic.unicamp.br/media/publications/FazHernandez_Armando_D.pdf">https://www.lasca.ic.unicamp.br/media/publications/FazHernandez_Armando_D.pdf</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a></div><div><br /></div><div><a href="https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/">https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/</a><br /><div><br />*<div><h4 style="text-align: left;">Triangle 3D Matrix graphs</h4><div><br /></div><div>C</div><div>|</div><div>|</div><div>_____b</div><div>\</div><div> \</div><div> A</div><div><br /></div><div>Vector table for audio & video or graphics..</div><div><br /></div><div>We will use integers for the 3D audio presentation & SiMD fpu for MP4 & AC4 & Alac decompression..</div><div><br /></div><div>RS</div><div><br /></div><div>So we will be using a form of float unit called..</div><div><br /></div><div>RollINT</div><div><br /></div><div>We are using roll to roll a zero on or off an integer,</div><div><br /></div><div>Therefore we are able to divide and multiply and add so that..</div><div><br /></div><div>101-0 > 10.1+0 No can range practically from 0 to 00000000 practically.</div><div><br /></div><div>So 10023-000 > 10.023+000</div><div><br /></div><div>We can then store floating point numbers in integer.</div><div><br /></div><div>(C) Rupert S,</div></div><div><br /></div>Reference Int & FP Value Sizes; A reminder that Floats are 50% of highest Integer Value,<br />ROLLInt floats still have an amazing additional value!<br /><br />https://learn.microsoft.com/en-us/dotnet/standard/numerics<div><br /></div><div>*</div><h4 style="text-align: left;">ECC elliptic curves & Gradients : RS</h4><div><br /></div><div><div>Leveraging FMA fused MUL ADD on Internet & Software ...</div><div><br /></div><div>For examples:</div><div><br /></div><div>Gradients vector compression..</div><div><br /></div><div>Colour A to colour B</div><div><br /></div><div>Compare dif {A:B}</div><div>Transform A over steps B</div><div><br /></div><div>Same colour ranges {R,G,B}</div><div><br /></div><div>(A - B) = Dif</div><div>Shift B over steps = A</div><div><br /></div><div>Store Vec VTable = steps</div><div><br /></div><div>VTable:</div><div><br /></div><div>Steps S1 to Sn</div><div><br /></div><div>Colour B1 to Bn + S1 to Sn</div><div><br /></div><div>S1,Sn</div><div>B1,Bn</div><div>B1,Bn</div><div>B1,Bn</div><div><br /></div><div>Same with time & dimensions in the ECC elliptic curve..</div><div><br /></div><div>S=T*D</div><div>Vector= {B1,Bn}</div><div><br /></div><div>(T*D)+Bn</div><div><br /></div><div>VTable:</div><div><br /></div><div>Steps S1 to Sn</div><div><br /></div><div>Colour B1 to Bn + S1 to Sn</div><div><br /></div><div>S1,Sn</div><div>B1,Bn</div><div>B1,Bn</div><div>B1,Bn</div></div><div><br /></div><div>Rupert S</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">Einstein : Quad:20x30 Matrix table</h4><br />With Einstein Formula being around 20 operations wide, 30 Lines long..<br />Single Operation Formula Matrix Tables could be popular,<br /><br />Consequently matrix math : MTU/MAP processor features should be popular...<br /><br />I take the view that 8 x 30 is about manageable on the Epyc & M2..<br />Bearing mind that a 32 Wide x 32 Long Operations SiMD is achievable...<br /><br />An AVX512 SiMD could run Quad operations (128Bit AVX) x 4,<br />So 20/4 = 5x; So 6x AVX512(128Bit Operation); Now there is; I believe; 1 AVX core per 2 Core Groups!<br /><br />So 24 Core has 8x or 4x or 2x (8 or 4 Cores per die unit)!<br />So 84 Core units should have enough AVX512?<br /><br />But one Mac M2... :D</div><div><br /></div><div><div>Einstein : Quad:20x30 Matrix table</div><div><br /></div><div>With Einstein Formula being around 20 operations wide, 30 Lines long..</div><div>Single Operation Formula Matrix Tables could be popular,</div><div><br /></div><div>Consequently matrix math : MTU/MAP processor features should be popular...</div><div><br /></div><div>I take the view that 8 x 30 is about manageable on the Epyc & M2..</div><div>Bearing in mind that a 32 Wide x 32 Long Operations SiMD is achievable...</div><div><br /></div><div>An AVX512 SiMD could run Quad operations (128Bit AVX) x 4,</div><div>So 20/4 = 5x; So 6x AVX512(128Bit Operation); Now there is; I believe; 1 AVX core per 2 Core Groups!</div><div><br /></div><div>So 24 Core has 8x or 4x or 2x (8 or 4 Cores per die unit)!</div><div>So 84 Core units should have enough AVX512?</div><div><br /></div><div>But one Mac M2... :D</div><div><br /></div>In our case Einstein, the table is 20 Wide & 35 Long (roughly)<br /><br />So : Einstein = Quad:20x35 | Alternative Quad:8x16, More manageable in<br />SiMD Parallel Executions; Quad:8x16 x 3, ....<br /><br />One presume strict aligned multiple multiplication<br /><br />4X4 Tables are still utility for Science maths; But we need<br />to get the point across what we need for Einstein! The Subject of 4x4<br />tables,<br /><br />The Subject of 4x4 tables,<br /><br />We are obviously looking for more like 16x16 for Physics maths!<br />The matrix processor is a large data set; Divisible into 4x2 & 4x4 &<br />8x8 groups for execution speedups,<br />Aligned Parallel processing....<br /><br />Aligned Matrix tables need to be larger than 4x4 for Physics &<br />Chemistry; So a matrix processor ideally can at a minimum:<br /><br />Matrix Table<br /><br />x1<br />16x16<br /><br />16/2<br />x2<br />8x8,8x8<br />8x8,8x8<br /><br />8/4<br />x4<br />4x4,4x4<br />4x4,4x4</div><div><br />RS<br /><br />*<div><br /></div><h4 style="text-align: left;">Triangle 3D Matrix graphs : a+b+c : Rotational algebra : ax+by+c=0 | e1, e2, e3</h4><br /><a href="https://www.icalculator.com/matrix-calculators.html">https://www.icalculator.com/matrix-calculators.html</a><br /><a href="https://academic-accelerator.com/encyclopedia/quaternions-and-spatial-rotation">https://academic-accelerator.com/encyclopedia/quaternions-and-spatial-rotation</a><br /><a href="https://stackoverflow.com/questions/tagged/matrix">https://stackoverflow.com/questions/tagged/matrix</a></div><div><a href="https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/">https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/</a><br /><br /><a href="https://marctenbosch.com/quaternions/">https://marctenbosch.com/quaternions/</a><br /><a href="https://arxiv.org/abs/1101.4542">https://arxiv.org/abs/1101.4542</a><br /><br />Quaternions > PGA Geometric : a+b+c : Rotational algebra : ax+by+c=0 | e1, e2, e3<br /><a href="https://www.youtube.com/watch?v=0i3ocLhbxJ4">https://www.youtube.com/watch?v=0i3ocLhbxJ4</a><br /><a href="https://www.youtube.com/watch?v=Idlv83CxP-8">https://www.youtube.com/watch?v=Idlv83CxP-8</a><div><br /></div>Improving Structured Grid-Based Sparse Matrix-Vector Multiplication and Gauss–Seidel Iteration on GPDSP<br /><a href="https://www.mdpi.com/2076-3417/13/15/8952">https://www.mdpi.com/2076-3417/13/15/8952</a><br /><br />SiMD Matrix Maths - Performance Portable SIMD Approach - Implementing Block Line Solver For Coupled PDEs<br /><a href="https://www.osti.gov/servlets/purl/1602621">https://www.osti.gov/servlets/purl/1602621</a><br /><br />SiMD Matrix Maths - Operations Details HIP AMD<br /><a href="https://rocm.docs.amd.com/_/downloads/en/latest/pdf/">https://rocm.docs.amd.com/_/downloads/en/latest/pdf/</a></div><div><br /></div><div>SiMD double tables, M1 Matrix<br /><a href="https://developer.apple.com/documentation/accelerate/working_with_matrices">https://developer.apple.com/documentation/accelerate/working_with_matrices</a><div><br /></div><div><a href="https://en.wikipedia.org/wiki/Advanced_Vector_Extensions">https://en.wikipedia.org/wiki/Advanced_Vector_Extensions</a></div><br />FMA AVX Performance table: 2Flops per Cycle per FMA Unit<br />Architecture Fast Instructions for FMA<br /><a href="https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf">https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf</a><br /><br />#RIP (Intro interesting!) Optimizing massively parallel sparse matrix computing on ARM many-core processor<br /><a href="https://www.sciencedirect.com/science/article/abs/pii/S0167819123000418">https://www.sciencedirect.com/science/article/abs/pii/S0167819123000418</a><br /><br /><a href="https://www.gamedeveloper.com/programming/implementing-a-3d-simd-geometry-and-lighting-pipeline">https://www.gamedeveloper.com/programming/implementing-a-3d-simd-geometry-and-lighting-pipeline</a><br /><a href="https://developer.apple.com/documentation/accelerate/working_with_matrices">https://developer.apple.com/documentation/accelerate/working_with_matrices</a><br /><br />CGal is a Matrix Math library for C; Luckily OpenBLAS is a compatible library & AMD Makes a version in HIP<br /><a href="https://cpp.libhunt.com/cgal-alternatives">https://cpp.libhunt.com/cgal-alternatives</a><br /><br />Matrix Libs : L1 means compatible with CGAL, A+ means i rate them highly on science community use : RS<br /><br />CGAL (L1)<br />GLM (L1)<br />QuantLib (L1)<br />Ceres-Solver (L1)<br /><br />OpenBLAS (A+)<br />Eigan (A+)<br />MiraCL (A+)</div><div><br />Github 3D Matrix AVX with alternatives<br /><a href="https://swiftpackageindex.com/fireblade-engine/math">https://swiftpackageindex.com/fireblade-engine/math</a><br /><br /><a href="https://github.com/ToruNiina/mave">https://github.com/ToruNiina/mave</a><br /><a href="https://github.com/fireblade-engine/math.git">https://github.com/fireblade-engine/math.git</a></div><div><br /></div>C++ Matrix Maths<br /><br />MPPT is Camera & FFMPeg complex install<br />https://docs.mrpt.org/reference/latest/compiling.html<br /><br />C++ Matrix Maths : Simple<br /><a href="https://sourceforge.net/projects/arma/">https://sourceforge.net/projects/arma/</a><br /><br />C++ conversions between Numpy arrays and Armadillo matrices; Converts Into Numpy Py not out (needs work)<br /><a href="https://github.com/RUrlus/carma">https://github.com/RUrlus/carma</a><br /><br /><a href="https://sourceforge.net/software/product/NumPy/">https://sourceforge.net/software/product/NumPy/</a><br /><a href="https://sourceforge.net/software/product/NumPy/integrations/">https://sourceforge.net/software/product/NumPy/integrations/</a><div><br /></div><div>Motivated applications of 3D Matrix Database ML</div><div><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br />Matrix-Blas_Libs-Compile<br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a></div><div><br />RS</div><div><br /></div><div>Just shows how fast Blas & these NumPy & Arma & Mave is! 1998-man SigRS<br />Parallel matrix multiplication & diagonalization<br /><a href="https://www-users.york.ac.uk/~mijp1/teaching/grad_HPC_for_MatSci/Lecture4.pdf">https://www-users.york.ac.uk/~mijp1/teaching/grad_HPC_for_MatSci/Lecture4.pdf</a></div><div><br /></div><div>Wasm Inefficiency<br /><a href="https://news.ycombinator.com/item?id=37387629">https://news.ycombinator.com/item?id=37387629</a><div><br /></div><div>*</div><br /><h4 style="text-align: left;">3D Matrix Web Codecs</h4><br />Are presented as being JIT Compiler re-encoded when required; Frequently WebASM, WebGPU Code, JS...<br />Audio, Video, Sensation, Code Runtimes.<br /><br />Web Codecs for devices are a modern concept & are available for common websites such as news & music,<br />devices such as Alexa Echo & Google Dot & Bluetooth Devices?<br /><br />Media players & BT devices particularly suffer from small Storage potential!<br />So Web Codecs downloaded to the device from a source; Such as a smart phone or computer..<br />Are a clear-minded solution!<br /><br />JIT Compiler<br /><br />3D Matrix Tables in FMA, Mul & ADD code to be automatically recompiled locally when required!<br />Directed to a common API, Direct Compute, WebGPU, WebASM, Jit Compiler OpenCL<br /><br />Many Operations can be done from unique device specific optimisation; Examples:<br /><br />API, DirectX & OpenCL & Vulkan & WebGPU & WebASM<br />Texture & Audio Shaders.<br />Digital Streaming<br /><br />Bluetooth NANO SiMD & API<br />Digital TV in H266, VP9 & AV1,<br /><br />Locally compiled accelerators should be respected first; Such as the output & input 3D Matrix & CPU & GPU Acceleration engine..<br /><br />Code can include Matrix converters into common output format such as WebP & Textures & BC, DXT Compression presentation; Vulkan, OpenCL & DirectX & Texture & Audio Shaders.<br /><br />Java, JS & WebASM are examples with operator mechanisms & JIT Compiler optimisation..<br />Minimising storage requirements for good compatibility while maximising performance.<br /><br />RS</div><div><br /></div><div>Requirements:<br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />*<h4 style="text-align: left;">TPU & SiMD Parallel wavetables Pre-Calculation Meta-Data : RS</h4>{ For data expansion & Precomputed Upscaling through meta data per frame sequence }<br />#MetaDATA #PreProcessing Parallel Text loading and machine learning processing : RS 23/07/2023<br /><br />Pre-calculation table; For Example the Amiga uses tables for maths!<br />Pi, Common conversion maths & float results in higher precision...<br /><br />Parallel Text loading and machine learning processing is one of the wonders of TPU & SiMD Parallel wavetables,<br /><br />Pre Calculate Tables that reduce a workload to simple process. and use...<br /><br />For example if you Upscale a movie & use dynamic settings, Such as: <br />Localised Sharpening & Selective Gaussian filtering; Such as Gimps Edge detection Gaussian?<br />We compress information on the maths of selection..<br /><br />The edges we selected, The methods we used & if those methods are dynamic then our selections...<br />Such a method is called a ..<br /><br />Pre-calculation table; For Example the Amiga uses tables for maths!<br />Pi, Common conversion maths & float results in higher precision...<br /><br />Common ones are learned at school<br />the log tables<br />Multiplication Tables<br />Common values such as gravity & Pi<br /><br />Pre Computation<br />Upscaling<br />3D Audio basic resonance profile<br />Pre Computed values for a realistic world...<br />Experience & Learning to pre compute values...<br />This saves effort later in the process<br /><br />This is available to providers & game developers for:<br /><br />TV Upscaling through Compressed Numeric Add table downloading<br />All streaming services processing such as netflix, youtube & amazon prime!<br />Partial pre-computed upscaling for game, application & processing..<br /><br />Through TopCloud & HPC Pack<br /><br />Data Stored as meta-data and saves on repeat processing time!<br />By creatively Pre Computing processes such as 3D Audio, VR Audio, Haptic 3D Maths..<br />Work such as Decompression & Compiling<br /><br />Affects the efficiency of any process that will Pre Calculate Tables that reduce a workload to a group of simple processes.<br /><br />We can majorly improve quality of both visuals & Audio; Any Pre-Calculatable element<br /><br />The logic is that Upscaling, Colour enhancements & sharpening have pre-calculatable logic,<br />We can save many seconds of processing per frame, <br />We can reduce energy footprint<br />We can improve latency & frame rate<br />Works for games also,<br />Education media or Theaters & mass media content such as News & commonly watched content or movies or visited websites or fonts & media<br /><br />We can improve at a very minimum, Cutscenes & non motional backdrops & tangible Animation repeating assets & Effects...<br /><br />(c)Rupert S<div><div><br /></div><h4>FMA : Fused Multiply ADD : MUL+ADD & Precision functions</h4><br />You may be assuming that only modern GPUs such as RTX 2080+ & RT 5700+ has this?<br /><br />FMA is a feature of the business editions & FX Series on AMD & exists in granite ridge & other Intel,<br />So FMA F16 is possible with the F32 : F16 conversion features present in for example FX8320E...<br /><br />So what does this mean? In terms of: <br /><br />Chrom that Emulates a lot of its GPU functions in CPU..<br />In terms of Python ML that F16 feature combined with FMA is very helpful in learning & efficiency!<br /><br />In terms of CPU; mostly using 32Bit, F32, 64Bit, F64 is very helpful; in terms of SiMD,<br />F16 exists though; Even on the yee FX8320E!<br /><br />So we can use potentially: Int8, Int32, Int64, F64, F32, F16 & Float 182Bit as with FPU!<br />Best to do DEEP work with the CPU FPU & SiMD...<br /><br />We do have these functions though!, But Deep work FPU 182Bit? CPU! Some GPU have double precision also!<br /><br />What do we use this variety for? Many things!<br /><br />Defined by our precision requirements; not all things are INT64 & FPU But not every issue is covered by..<br />The MP4v, MP4a F16! AC3 & AC4 for example F32; A glass? FPU 182... or many F32 or even more F16 work units.<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">Exponent factorisation : RS</h4>8Bit, 16Bit, 32Bit, 64Bit Exponent theory.<br />Available to you-(EF)<br /><br />A value in 8Bit is no use in a 16 Bit operation... or is it?<br /><br />Firstly 8 Bit values can be loaded with Zeros into higher math precisions,<br />In normal maths we use a remainder; So we can load 8Bit values into 32Bit Int & that works...<br /><br />2 F16 blocks would be 32Bit; As 2 16Bit Blocks? So what use is this ?<br />in a 64Bit & 32Bit processor storage of FPU-182Bit values is possible ...<br />32Bit Blocks * 6 with XOR 00<br />64Bit Blocks * 3 with XOR 00<br />2 * Largest value...<br /><br />But parallelising F64 on groups for 182Bit? with multiplications roll left <> Right .. & Additions +- ...<br />Possible.<br /><br />But if the resultant is beyond 8Bit ? & we wanted to save as 8Bit?<br /><br />Factorisation of a 32Bit value into 8Bit is possible; But we need to factor it!<br />Well:<br /><br />32Bit to 8Bit is 6:1, So we have to random roll 6 Bits for every 1<br />We can factor in HighLow with 1 bit or use 8Bit fator 256 & 8Bit Number...<br /><br />We can Multiply, Add, Subtract or divide or fraction:<br /><br />256(*/-)1>256, leaving us with a 32Bit value? Well what can we use this for ?<br /><br />Example complex : N/(240*50); See the maths can roll into 16Bit values..<br />We can use them, Or load a particular object, Classifier, HASH, AES, EEC...<br />We can quickly classify as 16Bit resultant & still save as a particular 8Bit value!<br /><br />Images<br />Gains<br />Memories<br />Load file<br />load value<br />Random<br />Table Value<br />Compression!<br /><br />(c)Rupert S,</div><div><br /></div><div><div>Reference Int & FP Value Sizes; A reminder that Floats are 50% of highest Integer Value,</div><div>ROLLInt floats still have an amazing additional value!</div><div><br /></div><div><a href="https://learn.microsoft.com/en-us/dotnet/standard/numerics">https://learn.microsoft.com/en-us/dotnet/standard/numerics</a></div><div><br /></div><div>https://science.n-helix.com/2023/02/smart-compression.html<br /><h4>F16b Adaptive Float value : Texture Color Palette Example : RS</h4><br /><br />Basic Example of F16b float in action on a colour pallet: {F16b,F32b, F64b}<br /><br />F16b is short remainder F16 & it has 8 Bits of 0.01 point value rather than 16,<br />So what do we mean ? What is significant about this?<br /><br />F16b Has 24Bit precision integer with an 8 bit remainder!<br />So? So 16Bit + 8Bit = 24Bit! & 8bit point value...<br /><br />In colour representation point values contribute to subtle blending;<br />So a full 24Bit contributes to 90% of the Color Palettes<br /><br />So the 24Bit colour pallet is 32Bit Colour Minus Alpha;<br />We can use F16b in HDMI & DisplayPort & inside the GPU & Also for textures & JPG'S..<br />Thereby i present F16b & F24Bit colours in F16b<br /><br />This saves all data in single 32bit Spaces & therefore is both faster & higher resolution than comparable float value presentations.<br /><br />Bound to make a big difference to BlueRay, but particularly DVD & AC3 & AC4; <br />F16b Adaptive Float value : Texture Color Palettes Example; <br /><br />(you can use F16b * R,G,B,A) in HDMI a& DisplayPort, Massive colour improvements; Lower RAM Costs<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">AnPa_Wave - Analogue Pattern Wave Vector SiMD Unit : (c)RS</h4><br />The base symphony is harmony, In other words waveforms; There are a couple of Simple methods that really work:<br /><br />High performance Float values F16, F32, F64, FPU<br /><br />Q-Bit Quantum; All forms of Quantum wave work<br />Radio waves; <br />Light patterns<br />Photon wave patterns; single & multiple<br />Sound hardware; 1 to 3 Bit DAC; Audio conversions; Sample range<br />Analogue chips that work on harmony & frequency<br />SVM Elliptic curve maths<br />Sin, Arc, Tan, Time, Vector<br /><br />In essence Harmony & frequency is the equivalent of Complex Elliptic curve maths<br /><br />A Music note score suffices to specify harmony basics:<br /><br />Waveform shape in 3D<br />Harmony / Disharmony<br />Vibration High / Vibration Low<br />Power High / Power Low<br />Volts High / Volts Low<br />Watts High / Wats Low<br /><br />(c)Rupert S<br /><br /><a href="https://science.n-helix.com/2023/07/3dchiplet.html">https://science.n-helix.com/2023/07/3dchiplet.html</a><br /><br />Wonderful Wave-Pattern Analogue waveforms in meta materials - Pattern recognition in reciprocal space with a magnon-scattering reservoir<br />https://www.nature.com/articles/s41467-023-39452-y.pdf<br /><br />*<div><div><br /></div><div>Vectors & maths<br />https://science.n-helix.com/2022/08/simd.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</div><div>https://science.n-helix.com/2023/02/smart-compression.html<br /><br />Networking & Management<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/06/map.html</div><div>https://science.n-helix.com/2023/02/pm-qos.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html</div>https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2022/01/ntp.html</div><div><br /><div>Faster Maths & ML<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Focus on Quality<br />https://science.n-helix.com/2022/09/ovccans.html<br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br />https://science.n-helix.com/2022/03/fsr-focal-length.html</div><div><br /></div>For when {U, X, Y, Z} = N Expressions https://is.gd/ForWhen_UXYZ_N<br />For when {(A+B/2)} = C Expressions https://is.gd/ForWhen_ABx2_C<div><br /></div>Hallelujah RS Light-Wave SiMD https://www.allaboutcircuits.com/news/lightelligence-reports-worlds-first-optical-network-on-chip-processor/<div><br /></div>RS Spectra Mitigations https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html<br />ZenBleed Parallel Solvent RS 2023 https://science.n-helix.com/2023/07/zenbleed.html<br /><br />Core/CPU/GPU security core SSL/TLS BugFix <br />https://science.n-helix.com/2020/06/cryptoseed.html<br />https://science.n-helix.com/2019/05/zombie-load.html<br /><br />Secure Configuration:<br />https://is.gd/SSL_NetSecurity_NTP_PTP<br />https://is.gd/EthernetTunnelOpt<br />https://is.gd/SSL_Optimise<br /><br />PTP & NTP Improve security WW https://is.gd/PTP_TimeStream</div><div><div><br /></div>*****<br /><br />Running Code</div><div><br /></div><div>https://is.gd/UpscaleWinDL</div><div><br />https://is.gd/HPC_HIP_CUDA</div><div><br /></div>PoCL Source & Code<br />https://is.gd/LEDSource<br /><br />PoCL-Direct<br />https://is.gd/PoCL_Source<div><br /></div><div><div>X86Features-Emu</div><div>https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing</div><br />https://www.amd.com/en/developer/rocm-hub/hip-sdk.html#tabs-ddafbba141-item-c6b9ce2aab-tab<br />https://rocm.docs.amd.com/en/docs-5.5.1/deploy/windows/quick_start.html<br /><br />AMD 23.Q3Pro_HIP #HPC #DirectML MatrixMathOps 'Release unto me the great! Chobokniki' Thine Prayers Answered https://is.gd/AMD23Q3PRO_HIP<br />Run the .reg after install; Before reboot https://is.gd/AMDRebarReg</div><div><br /><div>**********</div>https://en.wikipedia.org/wiki/Cell_(processor)<br /><br />https://www.khronos.org/news/permalink/ibm-releases-opencl-drivers-for-power6-and-cell-b.e/<br /><br />Not Accessible<br />https://www.alphaworks.ibm.com/tech/opencl<br />**********<div><br />AI: Artificial Intelligence <br />ML: Machine Learning <br />PULP: Parallel Ultra Low Power<br /><br /><h4 style="text-align: left;">ML Network Types</h4><br />DNN: Deep Neural Network<br />CNN: Convolutional Neural Network <br />QML: Quantum Machine Learning <br />QPU: Quantum Processing Unit <br /><br />RNN: Recurrent Neural Network<br />SNN: Spiking Neural Network <br />MLP: Multi-Layer Perceptron <br /><br />NN: Neural Network <br />TNN: Ternary Neural Network <br />QNN: Quantized Neural Network<br /><br />HDL: Hardware Description Language <br />HLS: High Level Synthesis <br /><br /><h4 style="text-align: left;">Maths Operations</h4><br />FMA: Fused Multiply-Add <br />GEMM: General Matrix Multiply<br />SIMD: Single Instruction Multiple Data <br />SIMT: Single Instruction Multiple Thread<br /><br />SP: Single Precision <br />DP: Double Precision<br />FLOPS: Floating Point Operations per Second<br /><br /><h4 style="text-align: left;">Processor Types & RAM</h4>ASIC: Application Specific Integrated Circuit <br /><br />SoC: System on Chip<br />PCU: Programmable Computing Unit<br />NoC: Network on Chip<br /><br />CPU Central Processing Unit<br />VPU: Vector Processing Unit <br />NPU: Neural Processing Unit<br />TPU: Tensor Processing Unit<br />FPGA: Field-Programmable Gate Array<br /><br />RISC: Reduced Instruction Set Computer<br />CISC: Complex Instruction Set Computer<br /><br />NDP: Near Data Processing<br /><br />PIM: Processing In-Memory<br />IMC: In-Memory Computing <br /><br />SRAM: Static Random Access Memory <br />VRAM: Video Random Access Memory<br />DRAM: Dynamic Random Access Memory <br />PCM: Phase Change Memory<br />BRAM: Block Random Access Memory<br />RAM: Random Access Memory <br />RRAM: Resistive RAM<br /></div><div><br /></div><div>*****<h4 style="text-align: left;">Matrix Array Processor Unit (c)RS</h4><br />[M.A.P] [=====] [H.P.C] - Matrix Array Processor Unit (c)RS<br /><br />This document describes the design and implementation of a novel computing device called the Matrix Array Processor Unit (M.A.P.U).<br /><br />The M.A.P.U is a co-processor that can perform high-speed parallel operations on multi-dimensional arrays of data, such as those used in quantum computing, machine learning, and computer graphics,<br /><br />A novel co-processor that can perform high-performance computing tasks using quantum-inspired principles.<br /><br />The Matrix Array Processor is a type of processor that is designed to handle multi-directional and multi-dimensional arrays per Qbit.<br /><br />It is used in quantum computers and relies on percentage-based 3D processing to handle all 3D array processing.<br /><br />The central tasks map to probability over networks and MAP units in arrays.<br /><br />The M.A.P is composed of multiple interconnected units that can process multi-dimensional arrays in parallel, using a percentage-based 3D processing scheme.<br /><br />The M.A.P can be integrated with existing CPU, GPU and DPU architectures, as well as with other M.A.P units, to form a scalable and flexible computing platform.<br /><br />The differences of Some Matrix Array Processor and other processors such as: <br /><br />SIMD (Single Instruction Multiple Data), <br />SISD (Single Instruction Single Data), <br />MISD (Multiple Instruction Single Data), <br />MIMD (Multiple Instruction Multiple Data), <br />Vector processors, <br />Systolic Arrays, <br /><br />Is that the Matrix Array Processor is designed to handle multi-directional and multi-dimensional arrays per Qbit...<br /><br />While other processors are designed to operate efficiently and effectively on large one-dimensional arrays of data called vectors<br /><br />The M.A.P.U consists of three main components: <br /><br />The Matrix Array Processor (M.A.P), <br />The High Precision Central Core (H.P.C), <br />The Bus Connections and Networking (=====).<br /><br />Core Definitions 3D M.A.P:<br /><br />[H.P.C]: <br /><br />A high-precision central core that can handle complex tasks such as probability mapping, network routing and memory management.<br /><br />The H.P.C is the central controller of the M.A.P.U.<br /><br />It coordinates the execution of tasks across the M.A.P units, assigns probabilities to different outcomes, and handles complex calculations that require high precision or accuracy.<br /><br />Each [H.P.C] unit can connect to 8 [M.A.P] units and optionally to other [H.P.C] units in different layers of the 3D matrix.<br /><br />The [H.P.C] can also communicate with external devices such as CPUs, GPUs, DPUs, or networks via the bottom layer of the wafer.<br /><br />[M.A.P]: <br /><br />The M.A.P is a specialized processing unit that can execute multiple arithmetic and logical operations on a single array element in one clock cycle.<br /><br />A unit that can perform arithmetic operations on multi-dimensional arrays using a dot product-like algorithm.<br /><br />Each M.A.P has 8-way interconnects to communicate with neighboring M.A.P units and a central [H.P.C] unit.<br /><br />The M.A.P has eight-way interconnects to communicate with other M.A.P units in the same layer or adjacent layers.<br /><br />The M.A.P can also access local cache or RAM for storing intermediate results or constants.<br /><br />[=====]: <br /><br />A bus connection that enables data transfer and networking among the M.A.P units and the [H.P.C] units.<br /><br />The bottom layer of the wafer contains a high-resolution bus that connects to the onboard controllers and networks and the external CPU, GPU and DPU devices.<br /><br />The ===== supports different communication protocols and topologies, such as mesh, torus, or hypercube.<br /><br />The ===== also provides fault tolerance and load balancing mechanisms to ensure reliable and efficient performance.<br /><br />The M.A.P.U is designed to be scalable and modular.<br /><br />It can be stacked in three dimensions to form a larger array of processors that can handle more complex and diverse tasks.<br /><br />The M.A.P.U can also be customized for different applications by changing the size, shape, or configuration of the M.A.P units, the H.P.C cores, or the ===== network.<br /><br />The following diagrams illustrate the structure and functionality of the M.A.P.U.<br /><br />Top View<br /><br />[M.A.P][M.A.P][M.A.P]<br />[M.A.P][H.P.C][M.A.P]<br />[M.A.P][M.A.P][M.A.P]<br /><br /><br />Side View 3D<br /><br /><br />[M.A.P][H.P.C][M.A.P]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br />[M.A.P][=====][M.A.P]<br />[=====][H.P.C][=====]<br /><br />Each [H.P.C] Central Contains RAM & connections to the 8 [M.A.P] & Optionally to layers above & bellow in 3D Matrix,<br />Bottom of wafer contains high resolution buss to onboard controllers & networks & DPU/GPU/CPU's<br /><br />Array = Matrix Array Processor Unit (c)RS<br /><br />ffffffff ffffffff ffffffff<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br /><br />f=fp,unit<br />*=mul<br />+=add<br />.=Cache/Ram</div><div><br /></div><div>Simple absolver table for MUL:ADD : MUL* Only = +0, +- Only = N*1 then +-<br />% = / 100 + ADD Table {N1 <> N...} : Result!</div><div><br />The M.A.P unit can perform operations on multi-dimensional arrays using a combination of: <br /><br />Floating-point units (f), Multiplication units (*), Addition units (+) and cache/ram units (.).<br /><br />The M.A.P unit can support different data types such as DOT4, INT8, INT16, F16, F32 and F64.<br /><br />The M.A.P co-processor is a cutting-edge technology that can enable new applications in fields such as artificial intelligence, machine learning, scientific computing and more.<br /><br />(c)Rupert S<br /><br />References: DOT4, INT8, INT16, F16, F32, F64 (c)Rupert S<br /><br />https://is.gd/LEDSource<br /><br />https://science.n-helix.com/2023/06/map.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Sparse matrix multiplication in SRM array<br />https://www.science.org/doi/10.1126/sciadv.adf7474<br /><br />Error Correction Options & Mitigation<br />https://futurism.com/ibm-breakthrough-quantum-computing<br /><br /></div><div>**********<br /><h4 style="text-align: left;"><br /></h4><h4 style="text-align: left;">Light Processors (c)Rupert S https://science.n-helix.com</h4><br />Light processors : Access to advanced : Storage Cache, Random Access RAM Cache & Processor architecture: Starting with SiMD Simple Vector Instruction Set<br /><br />Complex forms are a goal, Start simple : The world will thank you!<br />Simple as SiMD appears there are many uses, <br />Considering that higher instruction sets are delayed by SiMD space & speed priorities..<br /><br />Array = Matrix Array Processor Unit (c)RS<br /><br />ffffffff ffffffff ffffffff<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br />........+ ........*+ ........*<br /><br />f=fp,unit<br />*=mul<br />+=add<br />.=Cache/Ram</div><div><br /></div><div>Simple absolver table for MUL:ADD : MUL* Only = +0, +- Only = N*1 then +-<br />% = / 100 + ADD Table {N1 <> N...} : Result!</div><div><br />Array = Matrix Array Processor Unit (c)RS<br /><br />Cache is also a priority with manyfold application of simple data transfer & buffering to solid storage,<br />Power outage is our main concern so that we save all our work.<br /><br />SSD is an obvious solution to backing up speedily, <br />However we do use RAM Cache for this goal..<br /><br />The goal of speeding storage access up, <br />Light does all the work types we need:<br /><br />List:<br />Data transit<br />CacheProcessing via dimensions & signal variance<br />RAM (Cyclic light transfer) Same principle as fibre optic cable over large distances.<br /><br />(c)Rupert S https://science.n-helix.com<br /><br />Quantum ! Light Compute : Reference material : RS<br /><br />Yes we can solve classic problems with light computers, Light computers perform geometry & quantitative sampling (Comment by inventor) Rupert S <br /><br /></div><div>Light Compute : Reference material : RS<br />https://science.n-helix.com/2012/09/geometric-calculating-machines.html<br /><br />https://science.n-helix.com/2020/03/single-photon.html<br /><br />https://science.n-helix.com/2014/07/the-formula-of-geometric-volumes.html<br /><br />https://science.n-helix.com/2018/07/universeal-algebra-paper.html<br /><br />https://science.n-helix.com/2018/06/compression-libraries-index-prime.html<br /><br />https://science.n-helix.com/2013/08/light-theory-on-creation-of-3d-image.html<br /><br />https://science.n-helix.com/2018/06/uses-for-micro-laser-light-emitting.html<br /><br />https://science.n-helix.com/2020/04/render.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html<br /><br />https://science.n-helix.com/2019/05/compiler-optimisation.html<br /><br />https://science.n-helix.com/2018/09/hpc-pack-install-guide.html<br /><br />https://science.n-helix.com/2020/04/cern.html<br /><br />"Let's Play" Station NitroMagika_LightCaster<br /><br />Lets face it, Realtec could well resource the "Original QFFT Audio device & CPU/GPU"<br /><br />The mic works by calculating angle on a drum... <br />Light.. and timing & dispersion...<br />The audio works by QFFT replication of audio function..<br />The DAC works by quantifying as Analog digital or Metric Matrix..<br />The CPU/GPU by interpreting the data of logic, Space & timing...<br /><br />We need to calculate Quantum is not the necessary feature; <br /><br />But it is the highlight of our:<br /><br /></div><div>Data storage cache.<br />Our Temporary RAM<br />Our Data transport..<br />Of our fusion future.<br /><br />(c)Rupert S https://science.n-helix.com<br /><br />"Weedbrook points out that as yet, and in contrast to Google’s Sycamore, the Chinese team’s photonic circuit is not programmable, so at this point “it cannot be used for solving practical problems”."<br />https://www.nature.com/articles/d41586-020-03434-7<br /><br />https://scitechdaily.com/ai-boosted-by-parallel-convolutional-light-based-processors/<br /><br />https://interestingengineering.com/worlds-fastest-most-powerful-neuromorphic-processor-for-ai-unveiled<br /><br />Physicists in China challenge Google’s ‘quantum advantage’<br />Photon-based quantum computer does a calculation that ordinary computers might never be able to do.<br />Philip Ball<br /><br />PDF version<br />The interferometer part of our experiment.<br /><br />This photonic computer performed in 200 seconds a calculation that on an ordinary supercomputer would take 2.5 billion years to complete.Credit: Hansen Zhong<br /><br />A team in China claims to have made the first definitive demonstration of ‘quantum advantage’ — exploiting the counter-intuitive workings of quantum mechanics to perform computations that would be prohibitively slow on classical computers.<br /><br />They have used beams of laser light to perform a computation which had been mathematically proven to be practically impossible on normal computers. The team achieved within a few minutes what would take half the age of Earth on the best existing supercomputers. Contrary to Google’s first demonstration of a quantum advantage, performed last year, their version is virtually unassailable by any classical computer. The results appeared in Science on 3 December1.<br /><br />“We have shown that we can use photons, the fundamental unit of light, to demonstrate quantum computational power well beyond the classical counterpart,” says Jian-Wei Pan at the University of Science and Technology of China in Hefei. He adds that the calculation that they carried out — called the boson-sampling problem — is not just a convenient vehicle for demonstrating quantum advantage, but has potential practical applications in graph theory, quantum chemistry and machine learning.<br /><br />“This is certainly a tour de force experiment, and an important milestone,” says physicist Ian Walmsley at Imperial College London.<br /><br />Quantum advantage challenged<br /><br />Teams at both academic and corporate laboratories have been vying to demonstrate quantum advantage (a term that has now largely replaced the earlier ‘quantum supremacy’).<br /><br />Last year, researchers at Google’s quantum-computing laboratory in Santa Barbara, California, announced the first-ever demonstration of quantum advantage. They used their state-of-the-art Sycamore device, which has 53 quantum bits (qubits) made from superconducting circuits that are kept at ultracold temperatures2.<br /><br />But some quantum researchers contested the claim, on the grounds that a better classical algorithm that would outperform the quantum one could exist3. And researchers at IBM claimed that its classical supercomputers could in principle already run existing algorithms to do the same calculations in 2.5 days.<br /><br />To convincingly demonstrate quantum advantage, it should be unlikely that a significantly faster classical method could ever be found for the task being tested.<br /><br />The Hefei team, led by Pan and Chao-Yang Lu, chose a different problem for its demonstration, called boson sampling. It was devised in 2011 by two computer scientists, Scott Aaronson and Alex Arkhipov4, then at the Massachusetts Institute of Technology in Cambridge. It entails calculating the probability distribution of many bosons — a category of fundamental particle that includes photons — whose quantum waves interfere with one another in a way that essentially randomizes the position of the particles. The probability of detecting a boson at a given position can be calculated from an equation in many unknowns.<br /><br />200 seconds<br /><br />But the calculation in this case is a ‘#P-hard problem’, which is even harder than notoriously tricky NP-hard problems, for which the number of solutions increases exponentially with the number of variables. For many tens of bosons, Aaronson and Arkhipov showed that there’s no classical shortcut for the impossibly long calculation.<br /><br />A quantum computer, however, can sidestep the brute-force calculation by simulating the quantum process directly — allowing bosons to interfere and sampling the resulting distribution. To do this, Pan and colleagues chose to use photons as their qubits. They carried out the task on a photonic quantum computer working at room temperature.<br /><br />Starting from laser pulses, the researchers encoded the information in the spatial position and the polarization of particular photon states — the orientation of the photons’ electromagnetic fields. These states were then brought together to interfere with one another and generate the photon distribution that represents the output. The team used photodetectors capable of registering single photons to measure that distribution, which in effect encodes the calculations that are so hard to perform classically.<br /><br />In this way, Pan and colleagues could find solutions to the boson-sampling problem in 200 seconds. They estimate these would take 2.5 billion years to calculate on China’s TaihuLight supercomputer — a quantum advantage of around 1014.<br /><br />Practical problems<br /><br />“This is the first time that quantum advantage has been demonstrated using light or photonics,” says Christian Weedbrook, chief executive of quantum-computing startup Xanadu in Toronto, Canada, which is seeking to build practical quantum computers based on photonics.<br /><br />Walmsley says this claim of quantum advantage is convincing. “Because [the experiment] hews very closely to the original Aaronson–Arkiphov scheme, it is unlikely that a better classical algorithm can be found,” he says.<br /><br />However, Weedbrook points out that as yet, and in contrast to Google’s Sycamore, the Chinese team’s photonic circuit is not programmable, so at this point “it cannot be used for solving practical problems”.<br /><br />But he adds that if the team is able to build an efficient enough programmable chip, several important computational problems could be solved. Among those are predicting how proteins dock to one another and how molecules vibrate, says Lu.<br /><br />Weedbrook notes that photonic quantum computing started later than the other approaches, but it could now “potentially leap-frog the rest”. At any rate, he adds, “It is only a matter of time before quantum computers will leave classical computers in the dust.”<br /><br />https://scitechdaily.com/ai-boosted-by-parallel-convolutional-light-based-processors/<br /><br />"AI Boosted by Parallel Convolutional Light-Based Processors<br /><br />TOPICS:Artificial IntelligenceElectrical EngineeringEPFLMachine LearningOpticsPhotonicsPopular<br /><br />By EPFL JANUARY 7, 2021<br /><br />Matrix Multiplications Light Processor<br /><br />Schematic representation of a processor for matrix multiplications which runs on light. Credit: University of Oxford<br /><br />The exponential growth of data traffic in our digital age poses some real challenges on processing power. And with the advent of machine learning and AI in, for example, self-driving vehicles and speech recognition, the upward trend is set to continue. All this places a heavy burden on the ability of current computer processors to keep up with demand.<br /><br />Now, an international team of scientists has turned to light to tackle the problem. The researchers developed a new approach and architecture that combines processing and data storage onto a single chip by using light-based, or “photonic” processors, which are shown to surpass conventional electronic chips by processing information much more rapidly and in parallel.<br /><br />The scientists developed a hardware accelerator for so-called matrix-vector multiplications, which are the backbone of neural networks (algorithms that simulate the human brain), which themselves are used for machine-learning algorithms. Since different light wavelengths (colors) don’t interfere with each other, the researchers could use multiple wavelengths of light for parallel calculations. But to do this, they used another innovative technology, developed at EPFL, a chip-based “frequency comb,” as a light source.<br /><br />Matrix Multiplications Light Processor Schematic<br /><br />Schematic representation of a processor for matrix multiplications which runs on light. Credit: University of Oxford<br /><br />“Our study is the first to apply frequency combs in the field of artificial neural networks,” says Professor Tobias Kippenberg at EPFL, one the study’s leads. Professor Kippenberg’s research has pioneered the development of frequency combs. “The frequency comb provides a variety of optical wavelengths that are processed independently of one another in the same photonic chip.”<br /><br />“Light-based processors for speeding up tasks in the field of machine learning enable complex mathematical tasks to be processed at high speeds and throughputs,” says senior co-author Wolfram Pernice at Münster University, one of the professors who led the research. “This is much faster than conventional chips which rely on electronic data transfer, such as graphic cards or specialized hardware like TPU’s (Tensor Processing Unit).”<br /><br />After designing and fabricating the photonic chips, the researchers tested them on a neural network that recognizes of hand-written numbers. Inspired by biology, these networks are a concept in the field of machine learning and are used primarily in the processing of image or audio data. “The convolution operation between input data and one or more filters — which can identify edges in an image, for example, are well suited to our matrix architecture,” says Johannes Feldmann, now based at the University of Oxford Department of Materials. Nathan Youngblood (Oxford University) adds: “Exploiting wavelength multiplexing permits higher data rates and computing densities, i.e. operations per area of processer, not previously attained.”<br /><br />“This work is a real showcase of European collaborative research,” says David Wright at the University of Exeter, who leads the EU project FunComp, which funded the work. “Whilst every research group involved is world-leading in their own way, it was bringing all these parts together that made this work truly possible.”<br /><br />The study is published in Nature this week, and has far-reaching applications: higher simultaneous (and energy-saving) processing of data in artificial intelligence, larger neural networks for more accurate forecasts and more precise data analysis, large amounts of clinical data for diagnoses, enhancing rapid evaluation of sensor data in self-driving vehicles, and expanding cloud computing infrastructures with more storage space, computing power, and applications software.<br /><br />Reference: “Parallel convolutional processing using an integrated photonic tensor core” by J. Feldmann, N. Youngblood, M. Karpov, H. Gehring, X. Li, M. Stappers, M. Le Gallo, X. Fu, A. Lukashchuk, A. S. Raja, J. Liu, C. D. Wright, A. Sebastian, T. J. Kippenberg, W. H. P. Pernice and H. Bhaskaran, 6 January 2021, Nature."<br /><br />https://interestingengineering.com/worlds-fastest-most-powerful-neuromorphic-processor-for-ai-unveiled<br /><br />"A new optical neuromorphic processor developed by Swinburne University of Technology can operate more than 1000 times faster than any previous processor. The processor for artificial intelligence (AI) functions faster than 10 trillion operations per second (TeraOPs/s).<br /><br />RELATED: HUAWEI LAUNCHES WORLD'S MOST POWERFUL AI PROCESSOR<br /><br />Optical micro-combs<br /><br />The invention could revolutionize neural networks and neuromorphic processing in general. “This breakthrough was achieved with ‘optical micro-combs', as was our world-record internet data speed reported in May 2020,” said in a statement Swinburne’s Professor David Moss.<br /><br />Micro-combs are new devices made up of hundreds of infrared lasers all held on a single chip. Compared to other optical sources, they are much smaller, lighter, faster, and cheaper.<br /><br />The new innovation demonstrated by the Swinburne team uses a single processor while simultaneously interleaving the data in time, wavelength, and spatial dimensions through a single micro-comb chip.<br /><br />“In the 10 years since I co-invented them, integrated micro-comb chips have become enormously important and it is truly exciting to see them enabling these huge advances in information communication and processing. Micro-combs offer enormous promise for us to meet the world’s insatiable need for information," added Moss.<br /><br />Co-lead author of the study Dr. Xingyuan (Mike) Xu explained how this innovative use of micro-combs is giving the researchers a glimpse into the processors of the future. <br /><br />Cost and energy reductions<br /><br />Distinguished Professor Arnan Mitchell from RMIT University added that the "technology is applicable to all forms of processing and communications" and will result in significant future cost and energy consumption reductions.<br /><br />“Convolutional neural networks have been central to the artificial intelligence revolution, but existing silicon technology increasingly presents a bottleneck in processing speed and energy efficiency,” said key supporter of the research team, Professor Damien Hicks from Swinburne and the Walter and Elizabeth Hall Institute.<br /><br />“This breakthrough shows how a new optical technology makes such networks faster and more efficient and is a profound demonstration of the benefits of cross-disciplinary thinking, in having the inspiration and courage to take an idea from one field and using it to solve a fundamental problem in another.”"</div></div></div></div></div></div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-35652607129666146172023-06-13T03:06:00.017+02:002024-02-06T01:47:53.218+01:00Theory of mind - TOPCloud<h4 style="text-align: left;">[Theory of mind - TOPCloud +2021-03 RS]</h4><div><br /></div>Theory of mind : LLM:ML & us : RS<br /><br />Theory of mind : Clearly the Problem Sort Tree & Theory of mind; But also of the industrial age+(stone)<br />LLM - Large Language Models as tool makers<br /><br /><div>https://www.youtube.com/watch?v=qWI1AJ2nSDY<br /><br />To sum the content directly within the Layers of TOPCloud..<br /><br />Work Unit Cost Average = { <br /><br />Work Blocks : Work Unit Allocations per task<br /><br />WATTS, <br />TIME, <br />Effort, <br />Accuracy, <br /><br /></div><div>}<br /><br /><br />Basic LLM-Hive={<br /><br />LLM : The Mind or Hive:<br /><br />Direct knowledge gathering,<br />Basic Tool use : MathML, PyMath, OpenCL, Programming<br /><br />Tool making is the stone age step<br />Tool on tool is Industrial<br /><br />Too Big To Fail ;-)<br /><br />}<br /><br />Rupert S</div><div><br /></div><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2023/06/tops.html">https://science.n-helix.com/2023/06/tops.html</a><br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><div><br /></div><div><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2023/06/ptp.html">https://science.n-helix.com/2023/06/ptp.html</a></div><div><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><br /><a href="https://is.gd/TheSelfInSelf">https://is.gd/TheSelfInSelf</a></div><div><br /></div><div>***********<br /><br />Fully Autonomous NPC : Research Paper - https://arxiv.org/pdf/2304.03442.pdf<br /><br />Fully Autonomous Real-World Reinforcement Learning with Applications to Mobile Manipulation https://arxiv.org/pdf/2107.13545.pdf<br /><br />TOPCloud Heuristic Machine Learning<br />https://is.gd/LEDSource<br /><br />Fully Autonomous NPCs - Putting "Open World" To Shame (ChatGPT-Powered) : TOPCloud<br /><br />https://www.youtube.com/watch?v=Se6KFn1Nni4<br /><br />Autonomous agents are:<br /><br />Angels In Disguise : Secret underflow missions, Emotive resonances & Shared information such as local logs,<br />How well do 'Autonomous NPC' handle information about & from others ?<br /><br />Repeating? Common goals become daily tasks, Heuristics is like this! in Rogue<br /><br />Expressive? Allow interactions from such functions as Educators & News channels that they watch...<br />Treat some of the content like dreams or surreal interactions & narrative...<br />Not all content is believed; Not all dreams were unreal...<br /><br />Some are made; Some fall!<br /><br />Life is a function & has mechanics! Not all events suffer from a proof that nothing is or was programmed...<br /><br />TOPCloud; Outside influences & Larger pools of experience such as dream; role play; Interactions; Moving home to another 'persons device' (Such as Beijing)<br /><br />Interaction creation & perfection; TOP Cloud.<br /><br />Example Material : TOPCloud Text Translate & Associate<br /><br />Soule<br />https://www.youtube.com/watch?v=KBqPIcQV3hk<br />https://www.youtube.com/watch?v=ICGuGONrNzk<br />https://www.youtube.com/watch?v=UorRxnx-dsw<br /><br />************<br /><br /><h4 style="text-align: left;">TOP BOOSTER Cloud Enemy(tm) Provided by potentially DLSS Cloud Founder : </h4><br />*<br />TOPCloud & BlueTooth & Device : Localised & Cloud Computing JITCompiler:<br /><br />I have to be specific about TOPCloud & BlueTooth; Due to data bandwidth constraints..<br />Phone & Device direct provision of Computing power to Bluetooth devices is hard!<br /><br />Bandwidth is often only 250Kb & that is including the Codec data such as SBC & LCPlus & HE AAC 3D Audio!<br />So we need to save data & also Compute! Presenting TOPCloud..<br /><br />TOPCloud provides ML TOPS & Computing power to devices through Protocols known as the JITCompiler GPU RTP/RDP Device-Chain Stack<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />RS<br />*<br /><br />We cannot all Buy a founders GPU But we can all use your Founders Edition low price Cloud plugin for MMO & Online activated play Gaming : <br />Cloud Enemy(tm) - TENSOR CORE + TOPS + We cannot all buy your cloud GPU Founders edition... <br /><br />for reasons that AMD & NVidia and ARM & Intel do not directly buy a RTX3080TI Founders edition :p ^^ but we can all use your : <br /><br />Cloud Enemy(tm):(c)RS TENSOR CORE : All GPU of note have TOPS and obviously we all specialise <3<br /><br />My proposal is simple : All special console MMO need a 370 Tensor core server side :<br /><br />Enemy, Friend,Pet, Emoti play(tm)<br /><br />(read at the bottom of the post please, Bear in mind this does not mean NVidia is the best at RayTracing..<br />But it does mean we can truly afford to activate the full benefits of having ML TOPS..<br />Mobile phones often only have 4 TOPS or even 2! at the most 10 and specialists like IPhone 20>30<br /><br />But could all afford a small compliment to the Founders Cloud in that ML is dealt with for the entire MMO by the cloud; That way no one needs to know that ..<br /><br />MLT_RTP:RS<br />Machine Learning TOPS RTP Is a protocol specifically for the Mapping & implementation of AI<br />Upscale your machine parameters with living system ML<br /><br />Packets are intended to be between 15KB & 1MB light load over 1 minute<br />256KB to 4MB load over 1 minute..<br />Containing pre mapped dynamic logic & operations procedure calls that enhance for example:<br /><br />Game environment<br />Game AI<br />Robot logic<br />Driver logic<br />NPC Logic<br /><br />Research & Logistics<br />Mapping & Terrain<br />Radar & Drive By Wire<br />Traffic control & routing<br />Landing & takeoff<br /><br />GPU RTP (Complex 3D RTP, Simple message, local cache, Monster cloud render + local)(c)RS<br />Exists specifically for You the client:<br /><br />NVidia<br />Microsoft..<br />Google<br />Apple<br />AMD<br />Cloud gaming and service providers<br /><br />Linux VM<br />Windows VM<br />Mac VM<br /><br />Cloud Machine learning at GPU specialist clouds is of very high potency & potential,<br />But for a 1$ a week subscription game like Quake? very hard at large cost!<br /><br />(c)Rupert S https://science.n-helix.com<br /><br />Cloud Enemy(tm)<br /><br />Core strategic advice & adaptable SVM CPU <> GPU<br /><br />SVM/Int List:<br />Hard mode: Smaller refinement<br />Advance Hard mode: Micro model save, Micro model regression<br /><br />Advance BattleMode: Hard mode: Micro model save, Varied challenge (small regression),Indirect reference chat<br />Advance BattleMode: Hard mode: Micro model save, Varied challenge (small regression),Indirect reference chat,Personal chat<br />Advance BattleMode: Hard mode:RND resurgence, Micro model save, Varied challenge (small regression),Indirect reference chat,Personal chat<br /><br />Machine learning,<br />The Advanced SVM feature Set & Development<br /><br />CPU lead Advanced SVM/ML potential<br />GPU refinement & memory Expansion/Expression/Development<br /><br />SVM/ML Logic for: <br />Shaders, <br />Tessellation, <br />Compression, <br />PML Vector Ray-Tracing<br /><br />(c)RS<br /><br />Raising TOP's is JIT OpenCL<br /><br />The main process of internally Raising TOP's is JIT OpenCL<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />*<br />ML_RTP chain events:<br /><br />TPU Main Machine Learning NPC,<br /><br />Micro Enactor Scripts and ML (GPU Server Side)<br /><br />Local Micro Enactor Scripts and ML (Client GPU Side)<br />*<br /><br />The concept is to share processing work further down or up the chain:<br />Display to GPU & then CPU & USB, <br /><br />If there is a USB JIT Dongle such as compute stick that is in the Monitor USB or in a USB Dock on the HDMI/DisplayPort Cable; Then the JIT Compiler will handle OpenCL work units called Kernels...<br /><br />The ML RTP protocol sends work packets to servers; Traditionally in online games Scripts run on the server,<br /><br />MLT_RTP adds depth because the server can run Machine Learning Workloads such as OpenCL JIT & procedural calls to run mobs & pets..<br /><br />The main process is to have the local computer or device such as phone running small Machine Task interpreters; MTI are small machine learning routines that run through script's & diagnose problems with it..<br /><br />For example MOBS/Allies run into walls; With higher latency localised JIT Compiler Tasks can run the MOB/Ally Locally & not have to download from server so frequently..<br /><br />So we reduce latency but can still check the Mob/Ally is doing something we want & is not exploited.<br />We can run 10 Seconds of commands locally; For example on a localised node in Europe while the game runs in Japan...<br /><br />We can execute the thought processes of the Ally/Mob on the powerful TPU / Tensor Cores / Server F16..<br /><br />Individually scripting motions for all characters on another node; As in the Physics, Motions & Animations!<br />TPU are not known for GPU Render capacity & Nodes with both TPU & GPU would be pricey!<br /><br />But we chain events:<br /><br />TPU Main Machine Learning NPC,<br /><br />Micro Enactor Scripts and ML (GPU Server Side)<br /><br />Local Micro Enactor Scripts and ML (Client GPU Side)<br /><br />(c)RS <br /><br />*<br /><br />Low Latency ALLM Direct Render : GPU RTP & GPU RDP Protocols..<br />Specifically designed with GPU & Display Connections, Transport & presentation with..<br /><br />JIT Compiler <br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />Compressed Render VECSR https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2023/02/smart-compression.html<br />https://is.gd/LEDSource<br /><br />*<br /><br /><h4 style="text-align: left;">TOP Cloud Basics for personal help AI</h4><br />Machine learning from the direction of Alexa, Cortana, Siri, Bard<br /><br />Local processing requires RAM & processor time? Yes<br /><br />So we have a planed local process:<br /><br />2 MB Ram<br />700 Cross references on topic you ask...<br />300 Language response process<br />Optimised server access; Point of view is to isolate the connection below 2Mb/s (Probably 50Kb per response)<br /><br />Local library of common topics for you!<br />Local list of items you like; Song types you prefer; Your personal preference over 30 minutes<br /><br />Local data matrix is optimised for you..<br /><br />Most tasks are carried out local first,<br />As you see most requests require less thought & are already optimised for uploading & downloading...<br /><br />Question is; how much server do we need ? & how personal is it?<br /><br />Uses of TOP Cloud : Disabled People Basics:<br />TOP Cloud, is purely the best for all efficient visual & audio damaged people,<br />Can provide heuristics that allow colour blind people to see what they need!<br />Can do many things with a very small bit of time on large TPU & GPU, potentially in 1 Second for many people,<br /><br />Heuristics is all that we need after logic; & we can filter a video with a colour sensitive persons visual range; basic example & with a single WebASM or WebGPU colour layer; Very low CPU use they See..<br /><br />Red, Green, Blue; Enhance or tint.. <br />Single colour layer WebGPU, Shader, WebASM.. not actually on the video! <br />Additive tint.. As to enhance the colour or indicate with another a slight amount truecolour...<br /><br />"I see your true colours shining through" TOPCloud<br /><br />RS<br /><br /><h4 style="text-align: left;">TOPCloud Offload Logic:</h4><br />In terms of WebASM & WebGPU & MathML; TOPCloud provides sufficient advantages to be considered a core utility..<br /><br />While Offloading repeating content such as Siteload core stack (Server) & Localising configuration such as Webpage size & DPI & Dynamic font arrangements that require thought.<br /><br />In terms of Offloaded function & Efficient system load for large configurations.. <br /><br />Especially efficient configurations such as TPU, Coral, GPU work & Cloud CPU that have large optimised stacks & installed drivers.<br /><br />RS<br /><br />#Doctors #HuristicLists #CommonMedicalAdvisory #WebMD #CommonPerscriptionAuditingAdvice #Doctors I do not always know where to go!<br /><br />#HeuristicList<br /><br />#MD<br />#TOPCloud<br />#CommonResource<br />#DiscreteCosign<br />#Doctors<br />#HuristicLists<br />#CommonMedicalAdvisory<br />#WebMD<br />#CommonPerscriptionAuditingAdvice<br />#InfogramaticSortLists<br />#CommonErrorsTipNotes<br />#SugestedStaffLevels<br />#NonObligatoryMandate<br /><br />https://is.gd/LEDSource<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">#TheTOPCloudEdit (c)RS : Principle of data saving non localised Machine aided design & workflow (c)RS</h4><br />We really have to think about all the offloading strategies we can; Our network & storage footprint should be minimal..<br /><br />To name the philosophy completely we need to start with our most compressible assets!*<br /><br />Very high precision Float operations<br />high complexity offloaded ML<br />Long term strategies; Minutes to hours!<br /><br />Basic operation to offload are complex ones..<br /><br />We need multiple shape cuts in a single pass; Preferably vectors!<br />But those shapes shall be multiple factor complexity!<br /><br />The offloading of simple operations with KB of image or file per operation has higher latency & bandwidth!<br />Complex operations also may require that the HPC configuration has the image, video or data..<br />But we DO NOT Want to transfer GB/s data on presumption if we do not need to!<br /><br />So our primary source of TOPS performance; Is complexity operations; We no not firstly offload the image, Video, Texture, Complex Vector upload... If we are avoiding that?<br /><br />But we DO Offload:<br /><br />Vector lists<br />Sort lists<br />Memory optimisation lists<br />Khronos Compressed Vector files<br />Complex Math rotations & motions<br />Complex Vectors (in the sense of motion)<br />Elliptic Curves & SVM Maths<br />Multiple Dimensional Vector Arrays<br />Multi point paths & video & 3D Path tracing pre computations<br /><br />The principle is precision, Because what we do with a Photoshop is map a topography, our 3D Space with a complex compressed interpretation that our Facebook Codec can compose into an image edit <br /><br />We do the same Topography with cancer cutting surgical equipment, We need a precise CUT but our robot is 32Bit!<br /><br />Due to complexity we need a larger float value! (example value, Many values exist that we need & Armstrong knows that on Saturn voyage 13)<br /><br />TOPClouds non local edit is an example where the function; for example of the Alexa music player...<br />Is not to send all the data; We Help our local computer think; the same way as a teacher; gives a formula!<br />We do not need to know the Pythagoras value in full; But our operation may require it!<br /><br />We do not just need examples of Pi; We need examples of polynomial shapes, Vectors, Concepts & designs, Requiring less data sent & received than the work total cost of transfer to a trained massive network<br /><br />https://www.youtube.com/watch?v=9ykRV2OMPbE<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">#Sound Strategy game TOPCloud (c)RS</h4><br />PCM & MP4 are 2D/3D Image so GPU Helps there also with 3D Audio mapping!<br />Games do not require cloud processing of images & a lot of local strategies are procedural Heuristic<br /><br />You see RDP has GPU Connect (my innovation i might add) So Bluetooth & Wifi can connect RTP GPU; The port specifics are not particularly important; However a device such as music streamer can have ML TOP's available locally & from the cloud, <br /><br />Due to how the TOPCloud strategy works with localised ML TOPS; Not all data has to be sent or received.. <br />For example all Audio 3D Profiles for HQ Room audio can be done within a few MB of data; With some hard work? 150Kb of data & so in reach of phones & mobile! <br /><br />Gaming is an example here. I give TickTackToe as the example where all that a device like Alexa or Google smart device has to think is Which square? but..<br /><br />No physical picture needs to be sent for the game to be played & if required a small TickTack Strategy ML is desired locally for a quicker response!<br /><br />You see with a low latency GPU RTP & GPU RDP connection to cloud GPU; Most localised thinking TOPS can be carried out in Seconds if not milliseconds & PCM & MP4 are 2D/3D Image so GPU Helps there also with 3D Audio mapping!<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">Core features of TOPCloud:</h4><br />RTP ML TOPS are a processors friend<br /><br />3D audio mapping & spatialization for realistic sound effects<br />3D Vector Support for various audio formats such as PCM, MP4, OGG, and WAV<br /><br />Low latency & high bandwidth connection to cloud GPU servers via RDP<br /><br />Procedural & heuristic algorithms for generating game scenarios & strategies & 3D Audio & Visuals<br />Localized & cloud-based machine learning models for optimizing game performance & user experience<br /><br />RTP GPU Connect technology that allows users to access GPU resources from any device with Bluetooth or WiFi<br /><br />TOPCloud is a revolutionary 'TOPS' way to enjoy & create audio games using your own music & the power of the cloud. Try it today & discover a new dimension of gaming!<br /><br />https://science.n-helix.com/2022/10/ml.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />*<br /><br /><h4 style="text-align: left;">Scaling; We can classify by colour or creativity. (c)RS</h4><br />If you use TOPCloud, you can share between different displays in the TOP's Sense..<br />but mostly you would need cloud presence,<br /><br />Mostly this would be about making the most out of TOP heavy Business GPU & personal ones in your computer or consoles.<br /><br />But sharing common tasks such as scaling movies by type or by identifying a single movie to upscale...<br /><br />Now you might be asking what we would be doing there?<br />Well a single movie uses the same materials in our ML; We can analyse the class & optimise the scaling by class..<br /><br />For those familiar with games & FSR; We familiarise our code with a single game!<br />By doing this we improve our product and can therefore classify by:<br /><br />Resolution<br />Style<br />Speed<br />Type, FPS for example & RTS<br /><br />We can classify by colour or creativity...<br /><br />We do not simply have to roll the dice on General Scaling, We can use classifiers:<br /><br />Title<br />Scale<br />Type<br />Speed<br />Frame Rate<br />Colour & Composure<br /><br />PrePlanning<br />With the help of #TheTOPCloudEdit & F16 + DOT4 Classification commitments to:<br /><br />Larger Tables Interpolated & Optimised<br /><br />Pre planning & Optimisation LUT Mapping,<br />Colour & Dynamic range,<br />Dynamic frame rate control & adaptation<br /><br />Sound Dynamic Range,<br />Dynamic Volume<br />Virtual 3D Space<br /><br />Channel balancing; Before you ask:<br />Smoothing the 3D Range over each Speaker & Combined audio space,<br />Space mapping, Head averages such as size & width, Ears & Room Size<div><div><br />Rupert S<br /><br />Agents<br />https://www.youtube.com/watch?v=Se6KFn1Nni4<br />https://www.youtube.com/watch?v=DxxAwDHgQhE<br /><br />https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html</div><div>https://science.n-helix.com/2023/06/tops.html<br /><br />Rupert S</div></div><div><br /></div>*<br /><br /><h4 style="text-align: left;">LUT Table Example {TOPCloud & TOPCloud Edit}</h4><br />The significance of LUT Tables; Colour conversion ICC; Is fundamental to how good a monitor or TV Image looks,<br /><br />But we need to assume that most TV's & Monitors do not have a suitably RAM Loaded GPU;<br /><br />ICC can by themselves take MB of RAM to load & Upto 256MB of conversion Table!<br />TOPCloud & TOPCloud Edit allow for parameter offloading,<br /><br />The basic assumption for offloading is that there is no advantage to offloading a LUT Table to the local GPU?<br /><br />However TOPCloud allows for 3 fundamentally Simple Concepts to be in play,<br /><br />Firstly the use of OpenCL JITCompiler to procedurally unfold & map all LUT Mappings,<br /><br />2 You can remap to different hardware using the Hardware Abstraction Layer; Well in fact JITCompiler makes running the command low latency & super easy!<br /><br />3 You can even offload to cloud (same town for example Cloudflare),<br /><br />RS<br /><br />****************<br /><br />Basic Upscaling Kernel Starter Set, Contains a basic set of what we hope to achieve.<br />Learning from proverb; Future Productions inc<br /><br />OpenCL Kernel Builder<br />https://drive.google.com/file/d/1d_bWbZl9fAZXsLbN_jZdqSxdWzraLSIz/view?usp=share_link<br /><br />Texture Encode Source<br />https://drive.google.com/file/d/1udWU4slmZkUGcagcJl1KwFWh5FJ5ScoN/view?usp=sharing<br /><br />FSR Scaler<br />https://drive.google.com/file/d/1D27MOBYKVkKib1JzP_eFucp8RRrzAhd6/view?usp=share_link<br /><br />Python ML Image denoisers, Very heavy denoising<br />https://github.com/cszn/BSRGAN<br />https://github.com/cszn/SCUNet<br /><br />Crucial Codec source for projects<br />H266 https://drive.google.com/file/d/1Zt0CrP5p8ld7xnki1B9X4wz6Opyv13aH/view?usp=share_link<br />AV1 https://drive.google.com/file/d/179pqqS36v--t_BDjyhe1x_oVeYuxkWBw/view?usp=share_link<br />AAC https://drive.google.com/file/d/1YJy1yAdmEdjSMhtUjvTEU-y9HqJXFzzN/view?usp=share_link<br />LC3 https://drive.google.com/file/d/1_Gnf_PLN81YepCugmaRNofib7zLOHBNO/view?usp=share_link<br />DSC https://drive.google.com/file/d/1hbTFsFqzQTqLbhOaEwY-QkM4y3uAglXX/view?usp=share_link<br /><br />X86Features-Emu<br />https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing<br /><br />PoCL Source & Code<br />https://is.gd/LEDSource<br /><br />Linux HPC Node install<br />https://is.gd/LinuxHPCNode<br /><br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonML<br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonImageFilter<br /><br />https://science.n-helix.com/2022/10/ml.html<br /><br />To Compress using CPU/GPU: MS-OpenCL<br /><a href="https://is.gd/MS_OpenCL">https://is.gd/MS_OpenCL</a><br /><a href="https://is.gd/OpenCL4X64">https://is.gd/OpenCL4X64</a><br /><a href="https://is.gd/OpenCL4ARM">https://is.gd/OpenCL4ARM</a><br /><br />Upscale DL</div><div><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a><br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL</a><br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a><br /><br /><a href="https://is.gd/UpscalerUSB_ROM">https://is.gd/UpscalerUSB_ROM</a><br /><br /><a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a></div><div><br /></div>PoCL<br /><a href="https://drive.google.com/file/d/1Cvq9uQlEedwIXaJEMoD_r4lvOXgCy-Ld/view?usp=drive_link">https://drive.google.com/file/d/1Cvq9uQlEedwIXaJEMoD_r4lvOXgCy-Ld/view?usp=drive_link</a><br /><br />X86Features-Emu<br /><a href="https://drive.google.com/file/d/1iDW0HcpOoJqaSkuZGpHKJfKrI1H68diU/view?usp=sharing">https://drive.google.com/file/d/1iDW0HcpOoJqaSkuZGpHKJfKrI1H68diU/view?usp=sharing</a><div><br />*<br />https://github.com/ssube/diffusers/tree/feature/onnx-upscale<br /><br />https://github.com/huggingface/diffusers<br />https://huggingface.co/ssube/stable-diffusion-x4-upscaler-onnx<br /><br />https://huggingface.co/uwg/upscaler/tree/main<br />https://huggingface.co/nvmmonkey/optimal_upscale/tree/main<br />https://huggingface.co/gmp-dev/gmp-upscaler/tree/main/ESRGAN<br /><br />Neural Engine<br />https://github.com/godly-devotion/MochiDiffusion<br /><br />*<br /><br />PysicsX<br />Isaac Gym - Preview Release<br />https://developer.nvidia.com/isaac-gym<br /><br />CALM: Conditional Adversarial Latent Models for Directable Virtual Characters<br />https://github.com/NVlabs/CALM<br /><br />*</div><div><br />Personality UI : Have a friend<br /><br />Alpaca Character Generation model<br />4Bit for speed, But not precise<br />https://huggingface.co/anon8231489123/gpt4-x-alpaca-13b-native-4bit-128g<br />trained 3Epoc Higher Precision https://huggingface.co/chavinlo/gpt4-x-alpaca<br /><br />Base model https://huggingface.co/chavinlo/alpaca-13b<br />https://github.com/teknium1/GPTeacher<br /><br />Python WebUI<br />https://github.com/oobabooga/text-generation-webui<br />Mac; Mostly MAC but fast<br />https://github.com/ggerganov/llama.cpp<br /><br />how to use & personality sets https://discord.com/invite/aitrepreneur-1018992679893340160<br /><br />On the subject of how deep a personality of 4Bit, 8Bit, 16Bit is reference:<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br />https://science.n-helix.com/2023/06/tops.html</div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-47097343714299145842023-03-24T02:10:00.014+01:002023-05-10T21:28:22.861+02:00Path-trace-RTDL (c)RS - The combination of Ray Tracing & Path Tracing & FSR_DL; The advantage being a combination of RayTrace CU & General SiMD<h4 style="text-align: left;">Path-trace-RTDL (c)RS</h4><div><br /></div>The combination of Ray Tracing & Path Tracing & FSR_DL; The advantage being a combination of RayTrace CU & General SiMD, RS 2023-03 in response to the RS Technology being implemented.<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br /><h4 style="text-align: left;">Path Tracing define: RS</h4><br />Path tracing is when you take an objective viewpoint; A number of viewpoints to the receptor (Observer, such as gamer or camera<br /><br />VP = View Point, Observer is camera, RT Path = RT Core Ray<br /><br />View point Mesh, That is directional<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br />VP : VP : VP : VP : VP {Forward} VP : VP : VP : VP : VP<br /><br />VP : VP : VP : VP : VP {Observer} VP : VP : VP : VP : VP<br /><br />VP : VP : VP : VP : VP {Backward} VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /> VP : VP : VP : VP : VP<br /><br /><br />The location VP initiates a SiMD view directly to & from reflective objects & calculates distortion of view & texture with FSR_DL<div><br /></div><div>In this view i would like you to consider a reflective bounce camera viewpoint & think of the energy that saves you.</div><div><br /><h4 style="text-align: left;">RayTracing Define:</h4><br />Ray is cast from object & calculated to target vector; With Distortion calculation & reflections.<br /><br />We Combine minimum intersection with the VP; Using a cast Ray; So we know the viewpoint is active,<br />We trace the route back as the observer & calculate each intersection as an observer...<br /><br />FSR_DL handles surface distortions & fogs of war...<br /><br />We minimise the viewpoints memory footprint by altering the scale of the viewpoint in respect to the observers screen resolution / Distance .... We can also upscale the pretend frame!<br /><br />We can cache the frame & discard if we wish!<br /><br />Raytracing also provides distortion defines for viewpoints & Ray Distortion & Direction Calculations.<br /><br /><h4 style="text-align: left;">RT-Sparse-Field Pre Calculation Cache : RS & Lisa Lue</h4><br />During the initiation of the frame we calculate polygon placement,<br />We Cache the metrics & use them for our distance fields.<br /><br />Long term Non Volatile Cache<br />Short term recalculation cache<br />Validate Cache & use for ray tracing RayMarch & lighting.<br /><br />Real Time Sparse Distance Fields: https://www.youtube.com/watch?v=iY15xhuuHPQ<br /><br />Distance Fields are defined as Object detection with range finding,<br />In GPU SiMD we can reduce the Field Multiple Recount, <br /><br />Low cache containment Serial processing; Is where we have not got all the Polygon distances counted & in cache...<br /><br />We can however count on the GPU having the Polygon Map in RAM for a small segment of polygons; But due to the fact that we place the polygons in precise locations; We already have Distance.<br /><br />Distance fields are helpful because; Ray-forwarding (Ray March) does not need to do more than,<br />Process; Distortion & Viscosity & Density & transparency & Reflection, <br /><br />But we can do this over larger fields in areas with lower levels of modification property with counts as a lower required precision!</div><div><br />(c)Rupert S</div><div><br /></div><div>Path-trace-RTDL : This could be us : Path Tracing all light reflection, Does not require something as high on GPU as RX6500! Can be CPU SiMD/AVX on the Vectors, So can be a regular thing!<br /><br />We can even super sample our cube maps dynamically; So that we take the vector locations & transform the cube maps into fully RayMaped Polygons.</div><div><br /></div><div>The results are all about how we plan to Dynamically Optimise & Draw Vectors.</div><div><br />RS<br /><br />https://drive.google.com/file/d/14gGMWscMeUSRTDQJumclXfD5hDnHtxb2/view?usp=sharing, https://drive.google.com/file/d/15wZotdIXvctqoNQAc8bXwDHZx9w1VBAR/view?usp=sharing, https://drive.google.com/file/d/1ALi7anoOif5XT6VQYiWw_xfXVrrAedhD/view?usp=sharing, https://drive.google.com/file/d/1AsdsW8c4-sKk4asLOTv8ESCCS3u6Y25X/view?usp=sharing, https://drive.google.com/file/d/1H4VkoyuVVfAN2V0KiEF9VXM3OLadmuXt/view?usp=sharing, https://drive.google.com/file/d/1LIf05i_A7omfELolanN0wEwG2HosIiKz/view?usp=sharing, https://drive.google.com/file/d/1Rt1-4_UKodFnbnaHXYnKRh2G6-k0GCzc/view?usp=sharing, https://drive.google.com/file/d/1X8bprVmk8vtfhJxDtd6zKZBOjOL7CDiS/view?usp=sharing, https://drive.google.com/file/d/1czvKdoE0rAJogQMwMCwOUpYe-Dna9gdN/view?usp=sharing<br /><br /><a href="https://drive.google.com/file/d/1KvCm0rGnzNQ9es0CGj5ITvqGc7V78po9/view?usp=sharing">Mine-Craft-PathTrace</a></div><div>*<br /><h4 style="text-align: left;">Cubic SubSampling reference : </h4><a href="https://science.n-helix.com/2023/03/path-trace.html">https://science.n-helix.com/2023/03/path-trace.html</a><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><br />In simple principle SubS uses Probable interaction PDF & Ray Boxing (Isolated Cell Cube = [SS]/[SubS]),<br />We only therefore only need to Predict Sample for likely cube overflows into adjacent boxes.<br /><br />Resampling first; As we are resampling a ray box for probable intersection with our primary target (viewer),<br />Our motive is that the viewer is the only one to see the rays; Only Science project need to know all; But not always,<br /><br />We need a sample that does interact with the Observer/Viewer!<br />So we simply need a bounding box with a direction mesh (multiply by X) that shows probable cause to interact!<br /><br />We know that Viewer X is the only person seeing that interaction & So we know that if we point a triangle towards a light source; We directly interact with a subsample array,<br />We do not need them all!</div><div><br />PDF Similarity is used with the Ray Box to allocate work to probable cause; Located at User interaction AKA Observer/Viewer.<br /><br /><a href="https://gpuopen.com/download/publications/Efficient_Spatial_Resampling_Using_the_PDF_Similarity.pdf">https://gpuopen.com/download/publications/Efficient_Spatial_Resampling_Using_the_PDF_Similarity.pdf</a><br /><a href="https://gpuopen.com/download/publications/I3D2023_SubspaceCulling_updated.pdf">https://gpuopen.com/download/publications/I3D2023_SubspaceCulling_updated.pdf</a></div><div><br /></div><div>MultiDimensional Raytracing & 3D Visualisation<br /><br />Projection Pursuit (PP) based algorithms were shown to be efficient solutions for performing dimensionality reduction on large<br />datasets by searching low-dimensional projections of the data<br />Accelerating a Geometrical Approximated PCA Algorithm Using AVX2 and CUDA<br /><br /><a href="https://www.mdpi.com/2072-4292/12/12/1918">https://www.mdpi.com/2072-4292/12/12/1918</a><br /><br />Ray Tracing and Volume Rendering Large Molecular Data on Multi-Core and Many-Core Architectures<br /><a href="http://www.sci.utah.edu/~wald/Publications/2013/bnsview/bnsview.pdf">http://www.sci.utah.edu/~wald/Publications/2013/bnsview/bnsview.pdf</a></div><div><br /></div>*<br /><br /><h4 style="text-align: left;">Objective ~= Viewer, Deformation Bounce : Scatter Pattern S{1 : 2 : 3 : 4 } : Repeat</h4><br />GDC 2023 - Two-Level Radiance Caching for Fast and Scalable Real-Time Global Illumination in Games<br />https://www.youtube.com/watch?v=1eLz6WpXvQo<br /><br />the objective is to bounce rays towards viewer in a probability Oblong uneven cube,<br />What we do is mathematically work out how probable that additional light bounces on surface X<br /><br /> <span> </span><span> </span><span> </span><span> </span><span> </span><span> </span><span> </span>/{s}--{surface}<br />{Light Source}---/ \ / \ {viewer}<br /> <span> </span><span> </span><span> </span><span> </span><span> </span><span> </span>\---\{surface}<br /><br /><div>We can take the surface as a cube; Aligning a common detection point along a flat or low polygon count version of the surface...<br /><br />Map from the rays of light intersecting the surface at low resolution & map the average reflection as with path tracing,<br />compensating for shape distortion with calculations...<br /><br />Effectively we treat the light as a polygon & prove probable additional light based on it's likeliness to exist,<br />Low light levels reduce likeliness, Strong sources of light will more likely have rays...<br /><br />Surface deformations require more effort & we will concentrate more processor cycles to deformed areas such as water ripples, <br /><br />However we shall calculate the deformation matrix of the surface & therefore average the rays we measure & Calculate directions from deformation bounce.<br /><br />Because we calculate distortion from arc, sine, tan, Reflection value & variation in reflection dispersion & opacity.<br /><br />Scatter Pattern S{1 : 2 : 3 : 4 } : Repeat<br /><br />For Surface X{1 : 2 : 3 : 4 } + Light Y{1 : 2 : 3 : 4 } = light Z{1 : 2 : 3 : 4 } + Scatter pattern S{1 : 2 : 3 : 4 }<br /><br />Y{1 : 2 : 3 : 4 } / X{1 : 2 : 3 : 4 } = Scatter pattern S{1 : 2 : 3 : 4 }<br /><br />Rupert S<br /><br />*<div><br />PoCL Source & Code<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><div><br /><div>https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />Bus Tec : https://drive.google.com/file/d/1M2ie8Jf_bNJaySNQZ5mqM1fD9SAUOQud/view?usp=sharing</div><div><br /></div><div>FPGA 'Xilinx Virtex-II' HPC application Multiple-Applications & Image-Net & Matrix-Multiplication - H-SIMD machine _ configurable parallel computing for data-intensive HPC<br /><a href="https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations">https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations</a></div><div><br /></div>A SIMD architecture for hard real-time systems<br /><a href="https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2">https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2</a><br /><br />Ideal for 4Bit Int4 XBox & Int8 GPU<br />PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors - Bus-width 8-bit, 4-bit, 2-bit and 1-bit<br /><a href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/">https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/</a><div><br />Audio BT Codec<br /><br />https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html<br /><br />DSC, ETC, ASTC & DTX Compression for display frames<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />https://science.n-helix.com/2022/08/simd.html</div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-3210041717551301482023-02-27T21:15:00.121+01:002023-08-29T20:58:23.500+02:00Smart-Compression<div>Similar Wavelet Conversion with minimal reprocessing : Smart Access : RS</div><div><br /></div>(repeated encoding cost reduction) i know you are a coder, you could help ffmpeg & avx on the FX8320E, Likewise consoles face same issue with FFMPEG & Codecs & likewise with media acceleration by non repetition of encoding<br /><br />Similar Wavelet Conversion with minimal reprocessing : Smart Access : RS<div><br /></div><div>Printing Technology 'When you "Tie" the Knot' : </div><div>We want those Hand drawn Donald duck, Micky & Daffy in true line drawn splendour, </div><div>But hand drawing 8K is hell, </div><div>Remaster printing technology : For all monitors, TV's & Operating systems : DTS, Dolby : Functioning wave conversion</div><div><br /><div><h4>Smart-De-Compression : repeated encoding cost reduction : (c)Rupert S</h4><br />Wavelet Classifiers<br /><br />Audio<br />Video<br />Compressed Data, GZip, BZip, LZH<br /><br />Primarily our goal is to Originate Encode in a form that is Compatable with the hardware chain,<br /><br /><div>For example in the case of HDD > CPU > GPU the right Texture & Number formats, Often 16Bit or 32Bit float & Texture,<br /><br />However with Video we have to expand the frame wavelets into Compatable Texture formats!<br /><br />We convert the Video Wavelet in Smart Access to the closest Texture format wavelet; Or directly play the video! But suppose we are using Bink Video? We directly convert & keep wavelets that are the same in the new texture,<br /><br />We therefore select a texture format like NV12 or ETC2; One that has the most Similar Wavelets & can therefore reduce Conversion Cost of the frame by as much as 100% (If all wavelets are the same)!<br /><br />We know Wavelet types & Colour depth of all texture classes; So we will select one with a good range,<br />In most cases we play MP4+ Wavelets; So we can Use a JPG type texture; So all the compression wavelets remain minimally processed.<br /><br />A single Frame + previous B Frame; Into a single texture of the same Wavelet Compression Classification,<br /><br />The result is minimal processing CPU Cycles.</div><div><br /></div><div>*</div><h4 style="text-align: left;">Overall reducing costs of higher resolution resolving; As available in 264 > 265 > 266/VVC & other Media Encoders : Rupert S</h4><br />You can see that, formats such as 265 & 264 are related, Obviously at a higher resolution in the case of 265! <br />But in many Wavelet transform cases we can minimise the Processing cost, We do however need to know like Google's ML Voice Encoder; The ones we do not need to change (minimum benefaction)<br /><br />My chief challenge of Wavelet thought is a multiple frame picture of an eye (WebP for example),<br />The resolution is 640x480 & We know in most probabilities that; The Eye was transformed to wavelet in HD,<br /><br />So we have a wavelet curve; Black centre & A surrounding Iris!<br />We need to expand that wavelet so we will suppose that the higher precision version of the wavelet will add details?<br /><br />We must explore how the wavelet transforms a Higher Resolution form into a lower resolution form,<br />We can therefore in theory use the same wavelet at higher resolving depth?<br /><br />We might be able to convert a lower resolving wavelet in 12Bit into the 16Bit version & have a better understanding of the higher quality version!<br /><br />We can therefore most probably reuse the wavelet; Transforming from 264 to 265 & upscale & compress more,<br /><br />Overall reducing costs of higher resolution resolving; As available in 264 > 265 > 266/VVC<br /><br />*<br />#WaveletProve Both that the wavelet is infinite & that; The Breton<br />shirt wavelet has a pattern represented in 12Bit but liberating into<br />the profound on 16Bit, 32Bit & more!<br /><br />(To understand wavelet context, in textile & theory & of course Audio & Video)<br /><br />Can we prove the wavelet of a Breton shirt for infinity, like mauri<br />My augment being that we can upscale that Breton shirt! & prove it's<br />17th century values...<br />Both that the wavelet is infinite & that; The Breton shirt wavelet has<br />a pattern represented in 12Bit but liberating into the profound on<br />16Bit, 32Bit & more!</div><br />Example Wavelets to prove upscaling is possible <a href="https://is.gd/WaveletData">https://is.gd/WaveletData</a><div>*</div><div><br />Rupert S<div>*</div><br />Wavelet Upscaling : JPG / Video / Games<div><h4 style="text-align: left;">Example 2 Voxel to High Quality : RS</h4><br />The Story : HP : V-FX Wavelet Voxel Transforms : V-FX-WVT (c)RS (Harry Potter + More)<br /><br />I was wondering what to add to Wavelet transforms; Well i was thinking about Harry Potter,<br />Full body FX are Half Resolution; In Fact they are Depth of Field Voxels,<br /><br />For people who don't know Voxel is when you make a Cube of the right shade from a picture & set it at the right depth!<br /><br />For those criticizing such an act as lazy; You would have to understand how fast technology has developed!<br /><br />Some characters Fly at a very low resolution & Others like Harry Potter & Melfoy Don't!<br /><br />You would have to realise that V-FX is based on the ability of the person to be in the role... They perform ;-)<br /><br />*<br /><br /><h4 style="text-align: left;">V-FX Wavelet Voxel Transforms : V-FX-WVT (c)RS (Harry Potter + More)</h4><br />*<br />Definitions<br /><br />The Wavelet is the JPG Pixel Group of a single Group of pixels at the same size as the composing Voxels of the V-FX<br /><br />A Voxel is a Cube of Pixels set in 3D<br />*<br /><br />When it comes to Transforms; This piece is called:<br /><br />Transforms for classic movies : How you upscale VFX : RS<br /><br />Firstly the VOXEL (Simple Wavelet Cube) needs to be compared to a fully dressed original character,<br /><br />Then you need to map the correct features into The voxel cube space; After you Average Anti-Alias & Upscale the Cube Map (Original V-FX + Original Video Frame Person)<br /><br />You then need to map an effective Wavelet of the Original V-FX with a modifier Layer of transparent Wavelet (The Photo in High Detail, This is also a Wavelet Series)<br /><br />(c)RS<br /><br />*</div><br /><h4 style="text-align: left;">Example 3 : Lessons to learn : Wavelets : Upscaling (c)RS</h4><br />Now about the Voxel 4x4 cube map 'Transform wavelet' is a simple JPG Wavelet <br />(if used properly compressed & older games did not because processors where not very fast (33Mhz)<br /><br />High resolution 'Transform Wavelet' (Overlayed) is a full to higher resolution JPG Wavelet<br />In Upscaling we need to get from one to the other, <br />Transform Wavelet from Voxel Wavelet,<br /><br />Sample Scaling:But supposing we have samples of like minded objects? <br />We can use Machine Learning to imprint a pattern!<br /><br />But great looking as this is, not perfect as seen in Example 3 About Example 2 : HP!<br /><br />Wavelet permutation:<br /><br />Resolve the wavelet to full precision, Workable; But we need to know the result is correct!ML Can help; But that is very subjective..<br /><br />Mostly this works.<br /><br />Identity Follow through:<br /><br />Machine Learning that identifies the subject matter [Samsung & LG TV's 2020+ Example]<br /><br />So what do we do? We Add the lot! haha<br /><br />Rupert S<br /><br />*</div><br />Example 4 : Lessons to learn : Wavelets : Upscaling (c)RS<br /><br /><h4 style="text-align: left;">2 Pattern Matrix Wavelet (c)RS</h4><br />Wavelets are patterns; With Colour infilling (why not a wavelet itself!<br /><br />Well wavelets come in forms (Gif)8Bit, 10Bit, 12Bit, 16Bit(JPG)<br /><br />We can advance the precision by using a higher Precision (16Bit, 24Bit, 32Bit); But we need to save storage space!<br /><br />First thing is to use bF16 & bF32; This keeps the majority of the data from being sub pixels.<br /><br />Second thing is to make maximum use of multiple Precisions, Mix F16 with F32..<br />Google Lyra Codec demonstrates this in Machine Learning.<br /><br />Third : Keep Precision within margins, Small Textures do well in 8Bit Matrix Wavelets...<br />But 16Bit Colour Precision & 16Bit Precision both look good in HD High Quality HDR WCG</div><div><br /></div><div><div>(Usable as encryption archetype): Chaos:A:B:T:Pi:Arc:Sin:Tan</div>Very usable /dev/rnd Random Ring : TRNG : GPU : CPU : Asics : Using Chaos Wavelet</div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a></div><div><br /></div>{Wavelet:Colour Point) A to B as expression of Pi<br />{Wavelet:Colour Point} A to B as expression of Arc, Sin, Tan<div><br /></div><div>[2PMW File Array]<br />[Header : Easy Identifier : Basic Name]<br />{Header Packed Wavelet Groups] [1 Image Wavelet : Colour Shading Wavelet 2, 4, 8 Group]<br /><br />[Image Array lines]<br />|Packed Groups of] : [ Image Wavelet 1 : Colour Shading Wavelet Associations, 1 to 8]<br />[Packed Groups of] : [ Image Wavelet 1 : Colour Shading Wavelet Associations, 1 to 8]<br />[Packed Groups of] : [ Image Wavelet 1 : Colour Shading Wavelet Associations, 1 to 8] <br /><br />[PG],[PG],[PG],[PG],[PG]<br />[PG],[PG],[PG],[PG],[PG]<br />[PG],[PG],[PG],[PG],[PG]<br />[PG],[PG],[PG],[PG],[PG]<br />[PG],[PG],[PG],[PG],[PG]</div><div><br /></div>*<br /><h4 style="text-align: left;">Audio/Video/Image Format : Packing Vectors (c)RS</h4>Several choices of Interpolation; With low computation cost to higher Cycle Performance..<div>Depending on processor feature sets (such as NANO & SiMD & Crypto processor, Manageable in integer)<div><br /></div>Vector Wavelet Examples : Math object<br /><br />Wavelet Curve compress, Normally from left because we code Left to right & that is optimal for our hardware.<br />Can be numeric sequence Direction point 1=D D=1,2,3,4 2=Db = 1,2,3,4 | Displacement Dp = 1,2,3,4 Assuming Left To Right or curve displacement = Time<br /><br />Distance N from source edge, Curve:Sin/Tan<br />(Example) D=1 Db=3 Dp1=2 Dp2=3 | Curve = Tan3+Db2<br /><br />Logarithmic Pack,<br />Integer Comparator : N+N2+N3=N+1+2+3 | Sequence<br />*<div><br /></div><div><h4 style="text-align: left;">Example 5 : Predict Scaling : SiMD/AVX.SSE3 : (c)RS</h4><br />SiMD Interpolation grids & Predict with Raytracing & General SiMD<br />Reference Grid <br />https://science.n-helix.com/2023/03/path-trace.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />With the Interception/Processing of Predict Statements in Frames of Video & Audio; Using a simple Grid:<br /><br />Pr = Predict (motion) Px = Pixel t1:2:3 time period<br /><br />PxPx1PxPxPx3<br />Pr1Pr2PxPx2Px<br />Px1PxPr3PxPx<br />Px1Pr2PxPxPx<br />Px1PxPr2PxPx<br /><br />Basically you can see the pixels move in frame Px1 & Predicted in Pr2 & Pr3,<br />Raytracing SiMD predict future motion though maths; We can use the SiMD to, <br /><br />Both predict & interpolate/Upscale from 8bit, 10Bit, 12Bit, 14Bit to 16Bit values or rather wavelets,<br />Because Raytracing SiMD are high precision maths; They prove advantageous if we have them; SiMD/AVX.SSE3</div><div><br /></div><h4 style="text-align: left;">Interpolation : Prxi Pxri : {PxPrPi} Theory : RS</h4><br />We must present a point between Px (pixel) & Pr (predict); In maths this would be a remainder,<br />We can draw a pixel in the Remainder Point; The Interpolation point (PI); When? When we upscale!,<br />We can use two principles, Px (actual pixel), Pr (Predicted Pixel), PI Pixel Interpolation!<br /><br />We can guess with both Px & Pr on the content of PI & both Predict & Interpolate the pixel...<br />As additional Data; This does not worry us a lot.<br /><br />PxPIPxPxPI<br />PIPxPrPIPx<br />PrPrPxPiPr<div><br /></div><div><div>(c)Rupert S</div><div><br /></div>*<br /><h4 style="text-align: left;">The principle is 2 Stage interpolation with splines:</h4><br />We measure points between 2 values; for examples:<br /><br />Px to Px (Side by side comparison interpolation)<br /><br />Px to Pr, Pr1, Pr2,Pr3 (motion & predicted content), Upward Time & Circumference Interpolation.<br /><br />Px to Px2,Px3 (Time increasing potential interpolation, Both static content & calculated motion)<br /><br />We calculate Pixels between 2 values.<br /><br />Time content comes in 2 categories: <br /><br />Predicted location & Content:Pr<br /><br />Static location: Px (recorded location per frame)<br /><br />Finally comes Pi: Calculated locations & Content between Pixels<br />*<div><br /></div>*<br /><h4 style="text-align: left;">Interpolation & Extrapolation Policy : RS</h4><br />We can conclude Interpolation & Tessellation have requirements : 2D & 3D Spline Interpolation & Extrapolation; Gaussian methods on linear surfaces,<br /><br />We extrapolate the new; Such as blade edge; We can however layout a simple grid to our supposition edge & interpolate.<br /><br />We do not need to extrapolate where we have planed to draw; With so much as a 3cm polygon with 4 Lines & 2 edges,<br /><br />We can however draw a fractal blade; For example : HellSinger from Elric Melbone.<br />*<div><br /></div>https://sg.indeed.com/career-advice/career-development/interpolation-vs-extrapolation<br />Massive Datasets https://www.aimsciences.org/DCDS/article/2023/43/3&4<br /><br />Python Libraries Interpolation:<br /><br />15 Types<br />https://help.scilab.org/section_64fa3f01fdb19353faf0c6806a64a533.html<br /><br />Gaussian<br />https://gmd.copernicus.org/articles/16/1697/2023/<br />https://gmd.copernicus.org/articles/16/1697/2023/gmd-16-1697-2023.pdf<br /><br />SiMD Gaussian Blending & Dithering - Better_Fixed_Point_Filtering_with_Averaging_Trees<br />https://andrew.adams.pub/Better_Fixed_Point_Filtering_with_Averaging_Trees.pdf<br /><br />Vectorization of Kernel and Image Subsampling in FIR Image Filtering<br />http://bncss.org/index.php/bncss/article/viewFile/101/105</div><div><br /></div>Super temporal Resolution Imaging of Membrane Potential via Stroboscopic Microscopy<br />https://pubs.acs.org/doi/epdf/10.1021/cbmi.3c00054<br /><div><br />Implementation of a High-Quality Dolby Digital Decoder Using SiMD MMX™ Technology<br />https://smtnet.com/library/files/upload/dolby-intel.pdf<h4 style="text-align: left;">JIT Compile Displacement Micromap : Interpolation & Extrapolation Policy : RS</h4>Compress its internal geometry representations into the compressed format Just in time,<div>Optimizing, Allocating & de-allocating in accord with Mesh Shaders & Cache availability.<br /><br />VK_NV_displacement_micromap, which for Vulkan ray-tracing can help with added detail<br />No Comment https://www.phoronix.com/news/Vulkan-1.3.245-Released<br />VK_NV_displacement_micromap allows a displacement micromap structure to be attached to the geometry of the acceleration structure,<br />allow the application to compress its internal geometry representations into the compressed format ahead of time.<div><br />*<div><br />Our options for interpolation (don't forget Gaussian)<br /><br />bsplin3val — 3d spline arbitrary derivative evaluation function<br />cshep2d — bidimensional cubic shepard (scattered) interpolation<br />eval_cshep2d — bidimensional cubic shepard interpolation evaluation<br />interp — cubic spline evaluation function<br />interp1 — 1D interpolation in nearest, linear or spline mode<br />interp2d — bicubic spline (2d) evaluation function<br />interp3d — 3d spline evaluation function<br />interpln — linear interpolation<br />linear_interpn — n dimensional linear interpolation<br />lsq_splin — weighted least squares cubic spline fitting<br />mesh2d — Triangulation of n points in the plane<br />smooth — smoothing by spline functions<br />splin — cubic spline interpolation<br />splin2d — bicubic spline gridded 2d interpolation<br />splin3d — spline gridded 3d interpolation<br /><div><br /></div><div><div>*</div><br /><h4 style="text-align: left;">2D-3D Spline Interpolations with background complementary colour layer smooth blend</h4><br />Right on the kindle paper white 2D Spline is good for a single layer, 3D Spline is good if you rasterize a shader behind the text and shade it: The method would not cost over 1% of processing power on a 2 core ARM 400Mhz, If the image is relatively static.<br /><br />On full Colour HDR WebBrowser, The 3D Spline method makes sense with complementary colour blending...<br />On mostly static content; 3% of total page processing costs.<br />On mostly Static Text with mobile images a combination of 2D & 3D Spline; 7% to 15% of cost.<br /><br />interp2d — bicubic spline (2d) evaluation function<br />interp3d — 3d spline evaluation function<br /><br />Rupert S<br /><br />*<br /><h4 style="text-align: left;">High Definition Fusions : HDF Technique:RS (use scaling references example 4+3+2)</h4><br />I know that many of you, Use a machine learning based technique that enhances the sharpness & realism when upscaling,<br />The Voxel technique is very complementary to this view; Taking a 4 Pixel cube & transforming the look with additional details.<br /><br />High Definition Fusions : HDF Technique:RS (use scaling references example 4+3+2)<br /><br />I would call this technique High Definition Fusions : HDF,<br /><br />4 times the size frame buffer with upscaled into the buffer..<br />The Second thread then loads additional high resolution samples into the buffer with a blend.<br /><br />You have to observe the Details such as edges & X-OR mask the data inplace..<br /><br />Merge the data with the High definition component first load & the real details loaded ontop & then Gaussian Sharpen blended & smoothed.<br /><br />Ideally the sample data is from the original source in high resolution.<br />FSR & VSR can potentially work this way.<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">Font Scaling : RS</h4><br />A really good example is downscaling a 300Pt Font into a raster image for the 8pt Version..<br />But we Cache a buffer with all our letters & Gaussian blend from 32Pt to 8pt,<br />For that we need to MipMap a 300pt Vector font.<br /><br />300pt Font Cache<br />Rasterize at 300pt<br />Mipmaps : 300pt, 200pt, 180pt, 96pt, 60pt, 30pt<br />Gausian blend & cache at our size.<br /><br />(our size is probably 96pt or 120pt by screen & 600pt & 300pt by printer)<br /><br />That looks 100's of times better!</div><div><br /></div><div>Rupert S</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">Content Adaptation Dimming Zone Technology</h4><br />Remember Content Adaptation Dimming Zone Technology, <br />works for smaller frame buffers, <br /><br />With many devices 4GB RAM or more than simply enhance 8Bit & 10Bit per channel to 16Bit Smoothing Anti-Aliasing, <br /><br />Micro buffering allows much more, <br /><br />Single Zone [SS][SubS] Buffers could run you into 24MB Thread Buffer with an over head initial Buffer of 256MB Write Back Cached Rewritable Main buffer <br /><br />(So you can align Micro Contrast HDR WCG)<br /><br />RS<br /><br />*<br /><br /><h4 style="text-align: left;">Role : sSSubSampra Micro frame buffers a cube</h4><br />The LED Brightness curve; The logarithmic voltage & WATT brightness & colour variance,<br />In computer chips this is basically the Response in light to the voltage & WATT input..<br /><br />By controlling this upto 16Bit Dithered dynamic voltage control; usually with a modulated resister/ Transistor..<br />Such as a POT Potentiated differentiator; We can control the LED by altering the voltage & input WATT,<br /><br />We can also input a fluctuating digital signal, A signal that we dither,<br /><br />We take the signal of a SiMD or CPU & process this though a DAC or directly modulate the signal from the pin,<br />By analysing the output; We can produce the result of a digital waveform with reduced voltage..<br /><br />Max voltage = 16Bit * 11111>111:16b , Per connection & Usually we would Access the array to DIMM Post the LED,<br /><br />We can also micro array the LED Access with groups of LED & Cable.<br /><br />However we need a method of pre calculating the Digital Dither to 16Bit, <br />But due to the RAM requirements we may be posting 10Bit from the frame buffer!<br /><br />This is where sSSubSampra Micro frame buffers a cube of LED & Gaussian Dithers the colour palette & composes the group of pixels to the LED Electronics.<br /><br />We can quick post from SiMD if they can post DSC codec compressed bytes to the DSC Processor or display LED,<br />All we need are the shapes from DSC to be available for direct posting : DIM Post to screen,<br /><br />Passthrough & recompression can be optimised; Using the DMA & Codec Compression Shapes, Both to Upscale & to speed up the display,<br /><br />For all we need is that DSC has shapes we can refine in SiMD; From 8Bit to 32Bit SiMD Post is potentially possible by directly DMA Writing RAM to output.<br /><br />Speed differences are a few ns for a few more circuits.</div><div><br />RS<br /><br />*</div><div><div><h4 style="text-align: left;">Full Screen Sync, Single Cycle Multithreaded with [SS:SubS]Method : sSSubSampra</h4><br />Line post is traditional on CRT (because of single ray & analogue line by line TV Aerial signal.<br />Digital Age & we TV Aerial receive per frame digital compressed MP4 & H263/4/5/6 & VP9..<br />We still send per frame content as a line in effect,<br /><br />However the Single post method requires a complete Compressed Frame; In HDR WCG 12Bit this requires considerable RAM for frame buffer...<br /><br />You can output a frame; GIMP Uses 500MB of RAM for a single editable image,<br /><br />With single/Multiple line DIM Post a buffer of at least 32MB would be required..<br />Post processing constitutes at best 1/2/3/4/8 lines & memory retention!<br /><br />Full Screen Sync, Single Cycle MultiThread with [SS:SubS]Method<br /><br />The outlined method is my sSSubSampra : Dimming Zone : RS Method<br /><br />Because the Screen is divided into Frame Buffer Cubes : SS & Sub Cubes SubS,<br />We Buffer the frame & Cache & Post in Cubes [SS] with Sub Cubes [SubS]; These Cubes constitute smaller work units with smaller RAM Requirements.<br /><br />4K Image HDR 16Bit x RGBA = 500MB RAM Uncompressed.<br />(3840 X 2160) Image / 64 = 129,600px or (60px by 33.75px) * 64<br /><br />(60px by 33.75px) = * 8<br /><br />[SS] = 480px by 270px<br />[SubS] = 60px by 33.75px<br /><br />As we can see the DIM Post DMA Write is only 8MB to 16MB with full post processing multi-threaded.<br /><br />Rupert S<br /><br />*<h4 style="text-align: left;">sSSubSampra : Dimming Zone : RS</h4>Technique for Dimming Zones on all LED class devices.</div><div><span face="Arial, Helvetica, sans-serif" style="color: #222222; font-size: x-small;"><br /></span>(MipMaps: As AMD has a great MipMap in FidelityFX!:<br />So what advantage in creating our own? Well, let's see!)<br /><br />For a start our MipMap needs to be Higher than screen resolution!<br /><br />So we need to Gaussian Sharpen to a larger frame buffer,<br />Then we need to Sub-Sample > Dimming Zones, So why ? So we can lighten & darken parts of the dimming zone!<br />We can shade [SS] Sample Zones & Sub Sample [SubS]<br /><br />A screen usually needs a linear maximum & minimum light level; So we set these levels.<br />Divide SubS into a waveform filter with 3 to 8 levels of brightness<br /><br />So what do we need? Read above!</div><div><br />Super Sample Frame buffer<br />[SS]<br />For [SS] = 4 [SubS] * N<br /><br />Example Dimming Zone MipMap Zone<br />[SS][SS]<br />[SS][SS]<br /><br />[SubS][SubS][SubS][SubS]<br />[SubS][SubS][SubS][SubS]<br />[SubS][SubS][SubS][SubS]<br />[SubS][SubS][SubS][SubS]<br /><br />Rupert S</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">*Texture [SSSubN] : RS</h4>sSSubTexture<br /><br />[SS Texture with sub parts SubS]<br />N*[SubS Texture](Squares * N)<br />Refer to [SS/(N*SubS)]<br /><br />Packed Layers for filtering<br /><br />[6 * Same Size MipMap Sub Samples, Dark First with light layered ontop]<br />Very Light<br />Light<br />Lighter<br />Darker<br />Dark<br />Very Dark<br />*<br /><br />We can treat each layer using ML, Logical Gaussian Filters & Sharpens & Colour Vividness & Clarity.<br /><br />We DMA Move the frame by priority order, Dark first to very light.<br /><br />DMA Move [Texture Block][ VL, L, Lr, Dr, D, VD] Very Dark Arrives first to paint; This gives us the advantage of only lightening the screen,<br />But we do need the entire block to be DMA Transferred in 1 to 3 Ticks; This has a flashing effect if we don't paint the order in a single frame; So we must.<br /><br />Rupert S<br /><br />*</div><br /><h4 style="text-align: left;">MipMap Brightness Layer Example : sSSubTexture</h4><br />The example of a code:<br /><br />Fetch colour range (of the LED, For example Reds, Greens, Blues),<br />Grouped Colour range fetch saves on loads; But 16Bit SiMD can only load a small range; So a single colour,<br /><br />If we have 16Bit per channel we only load one colour range per Pull, <br />So we perform 3; Red, Green, Blue; Or 4 Red, Green, Blue, Black..<br /><br />When i say range i mean how light the pixel is; But we also blend the colour with the surrounding pixels subtly to anti alias,<br />To Anti Alias we need to bias colour reproduction to brightness closer to the next colour pixels,<br /><br />High Dynamic contrast; Still link colour brightness so the pixels blend, <br />Higher contrast removes waveform similarity, <br /><br />In lower contrast scenarios such as dark walls colours form in waves & therefore are smooth & able to be blended,<br />Lower contrast colour combinations lack distinct details & therefore are well compressed,<br /><br />Sharp high contrast colours are edges & liable to be aliased; We therefore link the local pixels & subtly match colours,<br /><br />For the example 7 shade MipMap we block groups of pixels into textures of different brightness; 7 levels,<br />We can blend & sharpen each level of brightness for optimal expression of vivid visual information.<br /><br />RS<br /><br />*<div><div><br /></div><div>Content Adaptation Dimming Zone Technology can be on 2 fronts:<br /><br />Display Signal Adaptive Content<br />The HDMI & DisplayPort signal can be Dynamically adjusted for Colour & Gamut range,<br />Example 8Bit/16Bit: RGB + Brightness & Darkness peak with on screen Profile & Gamma Curve<br /><br />The Dimming Zone Technology can then adapt to Display Source DDC & Available ICC - Internet Consortium Colour Profile : HDR BT2020, BT2084, BT709<br /><br />Directly on the display, In the firmware.<br /><br />Personally I believe that with Both; We will get the best.</div><div><br /></div><div>RS</div><div><br /></div>By this technique, You are not obliged to have a Micro Dimming Array..<br />But obviously Quality of the screen will be higher with a Micro Dimming array!<br /><br />The idea being that you can contrast and optimize all parts of a screen locally..<br />You will not need a Seperate Tile Micro Dimming Cable system.<br /><br />You will significantly improve Micro Dimming with tiles to be honest & Improve it with sSSubSampra micro contrast & colour.<br /><br />sSSubSampra significantly improves Multiprocessing of all image effects such as sharpening, Smoothing & filtering.<br /><br />RS</div><div><br /></div><div>*</div><br /><h4 style="text-align: left;">Audio, Video & High precision Float ML</h4><br />tensors & full onnx configuration : Upscaling : While we are not sure how much ML we need & at what precision,<br /><br />We can be sure that 32Bit (per channel) Value RGBA (Multiple layer) requires at least 8Bit to 16Bit per channel final precision; So here is a list:<br /><br />Required Value of output, Neural Network precision guide table: RS<br /><br />Input<br />8Bit, 10Bit, 12Bit, 16Bit<br /><br />Input network precision average bit retention (for RAM some error is allowed)<br />6Bit, 8Bit, 10Bit, 14Bit, 16Bit<br /><br />Classifiers as we know can be, <br />Int 2Bit 4Bit, 8Bit, 16Bit, 32Bit<br />2 Bit is unlikely & 32Bit is for Dream Smooth 16Bit+ Precision output</div><div><br />Output Float (Mostly FP & F16b)<br />16Bit = { 8Bit, 10Bit, 12Bit }<br />24Bit, 32Bit, 64Bit = { 16Bit, 32Bit, 48Bit }<br />We can upscale : Audio, Video, Content & Polygons, We classify Quality by expectations & Quantify by percent %<br /><br />Rupert S</div><div><br />*<br /><h4 style="text-align: left;">Classifier Behaviour</h4><br />F16 Compare Object Classifiers { Meta Data such as descriptors for the blind, Colour, Shape to Data }<br />F16:Int8 Compare Shape to table<br />Int8 Identify shape more subtly than Sharpen : Define Shape Sx<br /><br />F16 Compare Database to X<br />F16 Int8 Compare edge alias to X<br />Int8 Define [Edge X & Compare] | Send to Edge Sharpen matrix<br /><br />Set Shape to sharpen Elliptic<br />Sharpen or blur or Gaussian : Define Shape = Sh<br /><br />Sharpen or blur or Gaussian or spline3d interpolation<br />*</div><div><br /><h4 style="text-align: left;">Audio, Video & High precision Float ML : Colour palette example function</h4><br />With the High precision Float ML method we are capable of offering our VESA configuration on a compatible colour profile,<br />sRGB, BT709, BT2020, BT2084 & widen the palette!<br /><br />So why ? 2 reasons:<br /><br />Gaussian blending & Bi Linear pixel blending; We require a very subtle palette to bled well,<br />But we do not have RAM & processors to burn!<br /><br />Gaussian blending is efficient in the [SS][SubS] Pattern; Where we are dealing with patterns of Micro Dimming & adaptive contrast..<br /><br />The smaller pattern & Brightness MipMap layers mean we can blend layers as we need,<br /><br />Dark zones for example are noise hell; So we can Gaussian them; But we can sample details.<br />Brighter parts of the image are sure to have details that we need; But we handle each layer within the matrix..<br /><br />Smaller RAM Loads & faster Writes, Better Caching per frame.<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">Quad pixel is part of the texture format.</h4><br />As described in Example 2, 3, 4<br /><br />The principle of how to work a Quad or Ten Pixels into a shape,<br />Easier to describe in texture format words; A shape is made in a SiMD to be sent to a group of pixels,<br /><br />Grouping pixels means fewer DMA transfers; Because a SiMD is , 8bit, 16Bit, 32Bit, 64Bit..<br />Both the shape & the shade are described in a single request..<br /><br />Alternatively the pixel is subject to higher precision colour (64Bit for example); Therefore we can smooth blend with subtle shading & colour,<br /><br />We can also send 2 frames per send if we divide the SiMD into two lower precision parts..<br />But we have to receive the DMA as if we are interpreting 2 lower bit Integer/Floats; As of:<br /><br />Integer floats with remainder theory : <br /><br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />Wavelet Formation, Write [Px2] from [Px1] overlap as required by motion:<br />Write round in sequence or Write [Px1] Centric Texture to [Px1]>[Px2]</div><div><br />[DMA]<br />[Px2][Px2][Px2]<br />[Px2][Px1][Px2]<br />[Px2][Px2][Px2]<br /><br />Method 2 [DMA] write [Px1][Px2][Px3] & more as required & repeat (Example SiMD 64Bit = 4 x 16Bit)<br /><br />[DMA][Px1][Px2][Px3]<br />[DMA][Px1][Px2][Px3]</div><div><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">Feature Properties Meta Data Tables & Tags DDC</h4><br />LUT Colour Capacity Properties<br /><br />Important Colour & LUT Caps for AMD<br />https://www.phoronix.com/news/AMD-Color-Steam-Deck<br /><br />This reminds us to expose Caps both towards & from the OS & HDMI & DisplayPort,<br />Caps are exposed by the display in the form of LUT Table ICC such as BT2084, BT2020, BT709,<br /><br />Obviously the GPU selects LUT Tables such as BT2084 from the HDMI port, <br />But what about exposure of colour caps from the GPU to the Display ?<br /><br />The method of mutual lock for colour palette is a sure win, <br />Exposing additional capacities such as JIT Compiler, OpenCL, Vulkan & Direct Compute; Directly to the display!<br /><br />But Why? Acceleration & Colour qualities; For example exposing the LUT Compiler from the GPU Directly to the display in DDM Immediate mode ALLM, <br /><br />Colour & Cap exposure Would improve Colour rendering & additionally allow the displays to directly process LUT on the GPU,<br />Other features exposed through meta data could & would improve total rendering capacity & also utilise more of the DisplayPorts Capacity & bandwidth assignment.<br /><br />RS<br /><br />*<br /><br />Upscaling & FMA<br />https://science.n-helix.com/2023/06/map.html<br /><br />For when {(A+B/2)} = C Expressions <a href="https://is.gd/ForWhen_ABx2_C">https://is.gd/ForWhen_ABx2_C</a><br />For when {U, X, Y, Z} = N Expressions <a href="https://is.gd/ForWhen_UXYZ_N">https://is.gd/ForWhen_UXYZ_N</a><br /><br />*</div><div><div><h4 style="text-align: left;">Basic Upscaling Kernel Starter Set, Contains a basic set of what we hope to achieve.</h4>Learning from proverb; Future Productions inc<br /><br />OpenCL Kernel Builder<br />https://drive.google.com/file/d/1d_bWbZl9fAZXsLbN_jZdqSxdWzraLSIz/view?usp=share_link<br /><br />Texture Encode Source<br />https://drive.google.com/file/d/1udWU4slmZkUGcagcJl1KwFWh5FJ5ScoN/view?usp=sharing<br /><br />FSR Scaler<br />https://drive.google.com/file/d/1D27MOBYKVkKib1JzP_eFucp8RRrzAhd6/view?usp=share_link<br /><br />Python ML Image denoisers, Very heavy denoising<br />https://github.com/cszn/BSRGAN<br />https://github.com/cszn/SCUNet</div><div><br />Crucial Codec source for projects<br />H266 https://drive.google.com/file/d/1Zt0CrP5p8ld7xnki1B9X4wz6Opyv13aH/view?usp=share_link<br />AV1 https://drive.google.com/file/d/179pqqS36v--t_BDjyhe1x_oVeYuxkWBw/view?usp=share_link<br />AAC https://drive.google.com/file/d/1YJy1yAdmEdjSMhtUjvTEU-y9HqJXFzzN/view?usp=share_link<br />LC3 https://drive.google.com/file/d/1_Gnf_PLN81YepCugmaRNofib7zLOHBNO/view?usp=share_link</div><div>DSC https://drive.google.com/file/d/1hbTFsFqzQTqLbhOaEwY-QkM4y3uAglXX/view?usp=share_link</div><div><br /></div>X86Features-Emu<br />https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing<br /><br />Upscale DL<br />https://is.gd/UpscaleWinDL</div><div><br /></div>https://is.gd/HPC_HIP_CUDA<div><br /></div><div>https://github.com/GPUOpen-LibrariesAndSDKs/RadeonML<br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonImageFilter<div><br /></div><div>https://science.n-helix.com/2022/10/ml.html<br /><br />*<br />https://github.com/ssube/diffusers/tree/feature/onnx-upscale<br /><br />https://github.com/huggingface/diffusers<br />https://huggingface.co/ssube/stable-diffusion-x4-upscaler-onnx<br /><br />https://huggingface.co/uwg/upscaler/tree/main<br />https://huggingface.co/nvmmonkey/optimal_upscale/tree/main<br />https://huggingface.co/gmp-dev/gmp-upscaler/tree/main/ESRGAN<br /><br />Neural Engine<br />https://github.com/godly-devotion/MochiDiffusion<br /><br />ML List & Services<br />https://huggingface.co/models?sort=downloads&search=upscale<br />https://huggingface.co/models<br />https://huggingface.co/pricing<br />*<div><br /></div><div><h4 style="text-align: left;">Cubic SubSampling reference : </h4><div>https://science.n-helix.com/2023/03/path-trace.html</div><div>https://science.n-helix.com/2023/02/smart-compression.html</div><div><br /></div>In simple principle SubS uses Probable interaction PDF & Ray Boxing (Isolated Cell Cube = [SS]/[SubS]),<br />We only therefore only need to Predict Sample for likely cube overflows into adjacent boxes.<br /><br />Resampling first; As we are resampling a ray box for probable intersection with our primary target (viewer),<br />Our motive is that the viewer is the only one to see the rays; Only Science project need to know all; But not always,<br /><br />We need a sample that does interact with the Observer/Viewer!<br />So we simply need a bounding box with a direction mesh (multiply by X) that shows probable cause to interact!<br /><br />We know that Viewer X is the only person seeing that interaction & So we know that if we point a triangle towards a light source; We directly interact with a subsample array,<br />We do not need them all!<br /><br />PDF Similarity is used with the Ray Box to allocate work to probable cause; Located at User interaction AKA Observer/Viewer.<br /><br />https://gpuopen.com/download/publications/Efficient_Spatial_Resampling_Using_the_PDF_Similarity.pdf<br />https://gpuopen.com/download/publications/I3D2023_SubspaceCulling_updated.pdf</div><div><br />*<br /><br /><h4 style="text-align: left;">ReSTIR Additions</h4><br />Super Sampling is a technique of loading a texture; Upscaling the texture into a 4x to 8x larger size Cache,<br />Lacroze & Gaussian Blends combined with sharpening (Also available in AA & Gaussian Sharpening & 3D Spline Interpolation),<br /><br />Added to sharpening & upscaling is Bi & Tri Linear Interpolation..<br /><br />Interpolation requires that you estimate points between pixels in the texture or image..</div><div><br /></div><div>The implementation of Method Example 1 to 4 including Mipmapping [SS][SubS] Frame buffer With Multithreading Micro Framebuffer Groups..<br /><br />Allows Super-Sampling with Micro-Block Frame Recursive & Forward temporal Predict.<br />The simple storage of a frame in advance enables the technique,<br />Once a frame is in the buffer the next frame is managed with:<br /><br />Included Recursive & Forward frame interpolation.<br />Sharpening & Image Gaussian Blend, Sharpen & Sub-Sampling Anti-Alias<br /><br />In the Micro Frame Buffer & Texture Context & Full Frame colour, WCG & HDR Quality optimisations.</div><div><br />Interpolation methods include:<br /><br />Bit Average differential at higher DPI<br />Gaussian blending at a higher DPI & Sharpening<br /><br />Both methods have an additional Method: ML Identify & Classify ResNet<br /><br />ML Identify ResNet; Identifies the Shape intention & Classifies the object by content.<br />We can guess that a nose is angular down for example or that a Square will stay square..<br />MetaData containing the identity of objects helps a lot in classifying.<br /><br />ML_iRN Resolution Upscale & Texture Scaling<br /><br />Texture 256 | Texture buffer Size * N +<br /><br />{<br />3D Spline Interpolation,<br />Gaussian,<br />AntiAlias,<br />Lacroze<br />}<br /><br />Texture Buffer Final | Size * N<br /><br />(c)RS</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">2 Main approaches to Pixel Blend Dither : RS</h4>Strict Clarity; Very low blend count<br />Alpha Blending; Under 20% colour differentiated Rendering; In fonts as an example the most recommended is 30%.<br /><br />Strictly speaking a blend with more than 20% colour from a predicted location of adjacent pixels is garish,<br />Far too blatant & Directly inaccurate..<br /><br />Potentially 3% to 7% pixel blending is quite subtle on 1024x768 & lower down to 1%,<br />I have a great deal of experience optimising such displays as Combined signaling on wave generators & Radio..</div><br />The Super-Sample Technique; 1% to 7% colour & Luminance & Contrast differential AntiAlias & Super Sampling + mild sharpening (light settings 1 of 10)<div><br />So yes blends of low potential difference make quite a lot of difference to perceptions of quality; Combined with subtle sharpening & AA.<br /><br />Pixel blending & Sharpness in context of Average Pixel density<br /><br />On a 1024x768 Display Pixel blending from a range of 1 Meter just works as a method,<br />At the pixel density of a 1024x768 display discolouring an adjacent pixel with a complementary colour for a predicted sub-location...<br /><br />Alpha blending in effect works for real on an HD 1200x768 resolution or more quite well!<br />On a display with a lower pixel count than 1024x768 ; A pixel is either Yes or No.<br /><br />96px or greater & 720pHD or greater & Pixel blending works well,<br />The higher the resolution is & the larger the distance is to view & the better this works as a method.<br /><br />Rupert S</div><div><br /></div><div>*</div><br /><h4 style="text-align: left;">Pixel format optimization : Pix-AL</h4><br />RGBA & BGRA, We obviously load the texture in 3 colour layers & therefore create an optimal map for dithering & smoothing purposes..<br /><br />Natively aligning all colours to their corresponding pixel bit, Blue, Green, Red..<br /><br />Perfect!</div><div><br /></div><div>Examples:<br /><br />RGB Offset R0.0, G0.5, B1<br />RGB<br />RGB<br /><br />BGR Offset B0.0, G0.5, R1<br />BGR<br />BGR<br /><br />In such examples the textures are aligned | Align = 0.0, 0.5, 1.0<br />Pixels consist of Arrays of colour; We align the colour Mipmap & thus sharpen the Texture & Video, <br />VESA DSC Codec particularly.<br /><br />Remember CRT, Plasma & LED TV's Had alignment firmware automation with analogue..<br /><br />We automate the prospect of aligning Pixels by Colour with Texture formats such as: <br />DSC, DXT5, ETC, ATC, PVRTC, ASTC & DTX Compression for display frames.</div><div><br /></div><div>RS<div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Colour like the angels SESW16 & SESW32 for pixel (c)RS</h4><br />When it comes to demosaicing you are obviously aware of pixel grid from raws; As a photographer myself; I of course researched such topics..<br /><br />But you do need a grid to demosaic; In LED displays you think you need to demosaic; But in reality you are purely mixing light though the spatial anomaly called Air blur,<br />But you really need to demosaic the content of the pixel colour; As the primes red, Green, Blue & shades of them are present in each patch..<br /><br /><div>The principle is that when you call a pixel write; You are improving visual quality prioritizing each colour components priority for processing or patch processed:<br /><br />*<br />To explain patched, see the process of screen write; To either write by line or groups of lines &or Patch Cube,<br /><br />In that you group segments of the Screen DMA refresh into either line writes or Squares in order to make the write process faster during a frame flip.</div><div>*</div><br />mosaicing reasons, Filtering pure colours for less distorted purity,<br />Example common configurations of pixel:<br />RGB<br />GBR<br /><br />when we post an LED group such as this we can use two methods:<br /><br />single energy spike with wavelet<br />Colour Encoded energy Spike with wavelet<br /><br />In principle single energy spike allows a full range 16Bit FP SiMD to post full range channel data with no overheads; But we need 3 R G B<br /><br />In principle 3 RGB code colour DAC Spike needs to be 48Bit to be 12Bit/16Bit Sensor...<br /><br />So in effect as demonstrated here in my thesis; Single Wave 16Bit spike SiMD x 3 but filtered per colour = 16Bit x 3 or 48Bit<br /><br />Data wavelength reduction reduces the method to one simple thing? How to do a patch with 16Bit Energy representation only ?<br /><br />single energy spike Wavelet : SESW16 SESW32 and so on.<br /><br />Colour like the angels SESW16 & SESW32 for pixel (c)RS<br /><br />Rupert S</div><div><br /></div><div>*<br /><br /><h4 style="text-align: left;">Pixel Order: RGBA & BGRA & RGBA_f16 BGRA_f16 : RS Applies to Video & Audio rendering & Delivery</h4><br />Single F16 pulse per R,G,B, F16x3<br />F16 Wave32 10xRGB & 2 Control Filter F16<br />F32 Wave32 10xRGB but 2x F16 & 2 Control Filter F32<br /><br />Depending on how much control a device has over how to draw/light a pixel...<br />The Method of prioritising the colour that is mainly processed; May have advantages.<br /><br />In principle with my display as the example; If we light all 3 colours at the same time per pixel then...<br /><br />BGRA is the apparent order; So a DMA Paint with {BGR}A is going to sharpen the colours in that order & also filter them for noise in that order!<br /><br />So what effect does this have ?<br />All 3 colours can be drawn in a single pass; Although we could separate 3 Passes per frame if we want...<br /><br />3 mono passes with 3 Layers of pure F16 R G B; In my case B G R,<br />Alternatively 3 Pure F16 Energy Rating pulses for the 3 colours per pixel.<br /><br />What is the relevance of F16 x 3 ? Can't we do an F16 Palette with all 3 colours ?<br />Well no because my display is 10Bit so the output would be 30Bit!<br /><br />30Bit is a lot more complex to produce from SiMD; Probably use 32Bit SiMD..<br />So not a problem; But all 3 colours would process in 32Bit & that is more work.<br /><br />F16 Wavelet pure energy levels x 3 R G B means at most 3 cycles or 3 SiMD Units,<br />Bear in mind that SiMD is anywhere from Wave32 32 Operations, Wave64 64 Operations..<br /><br />We could use F16 Wave32 and colour 10 Red, 10 Green, 10 Blue per cycle<br /><br />Single F16 pulse per R,G,B, F16x3<br />F16 Wave32 10xRGB & 2 Control Filter F16<br />F32 Wave32 10xRGB but 2x F16 & 2 Control Filter F32<br /><br />So in essence F16 makes more sense depending on what hardware we use,Filtering each colour in pure F16 Identically & with the same Shader!</div><div>More precise than F32 / 10Bit per R, G, B & 2 Control bits.<br /><br />Rupert S<div><br /></div><div>*</div><br /><h4 style="text-align: left;">6 Way Matrix Spline Interlace Multiplier : RS</h4><br />Matrix consist of a 6 way La{1:2:3} to Lb{1:2:3} Edge Detect & then interpolation with smoothing,<br /><br />Edge detection promotes importance of aligned colour points, <br />This is called a 6 Way Matrix with Lma favouring La & Lmb favouring Lb; Lm is Lma 50/50 Lmb<br /><br />Maths Basic<br />1920x1080 = 1918 lines | 6 way + 2 sides (up down) 3 Way & 1078 | 6 Way + 2 sides (Left Right) 3 Way<br /><br />La{1:2:3}<br />Matrix Interpolation 1 to 3 lines<br />Lb{1:2:3} <br /><br /><span> </span><span> </span><span> </span><span> </span>La 1 2 3<br />Matrix Lma 1 2 3<br />Matrix Lm 1 2 3<br />Matrix Lmb 1 2 3<br /> <span> </span><span> </span><span> </span><span> </span>Lb 1 2 3<br /><br />As you can see the matrix is 6 ways on real lines & multiplies or doubles lines,<br />Matrix can be 1+1/3, 1+2/3, 1+1, Etcetera.<br /><br />This method is relatively simple & fast.<br /><br />Rupert S</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">Identified material ML Shaped Edge Detect Gaussian sharpen & blend (c)Rupert S</h4>When i say fast i mean, MOV {X,Y}stack | add {x + y} DIV {xy}/2 | MOV {stack} {FrameBuffer} : <br />I am afraid that this is about as FAST as Good upscaling under 2Ghz gets</div><div><br /></div>Suitable for WebASM & WebGPU</div><div><br /></div><div>Basic thought Upscaling ASM : RS<br /><br />MOV {X,Y:X2,Y2:Xn,Yn}FrameBuffer1<br />var upscale = add {x + y} DIV {xy}/2 | MOV {XY + upscale}FrameBufferTemp<br />MOV {FrameBufferTemp+FrameBuffer1} LOC {FrameBuffer2(FrameBufferTemp+1 FrameBuffer1+0)}<div><br /></div><div>Var table1 = input<br />Var table2 = interpolate<br />Var table3 = output<br /><br />Var xy = 2/(X+Y)<br />For var table1 = {X1, Y1 : Xn, Yn} Then Var table2 = xy{X1, Y1 : Xn, Yn};<br />Then table3 = ({table1X + table2X+1} + {table1Y + table2Y+1})</div><div><br />*example<br />the tunisian & Ukraine low resolution cam footage has too low a frame rate for eye or hand motion<br />*<br /><br />Interpolation and has lines, probably less than 25fps, the clear minded need to double the frame rate<br /><br />So strangely enough, Double frame rate by copying predict frame & upscale the in-between frame before; Upscaling the previous frame & future frame with frame to frame interpolation & sideways & line to line inter-predicted interpolation..<br /><br />Inter-predict interpolation sounds like a CPU heavy configuration; However the use of Gaussian (heavy or light precision) & spline interpolation, both temporal & resizing...<br /><br />Because applied on top of or under the Identified material ML Shaped Edge Detect Gaussian sharpen & blend,<br /><br />not too CPU heavy on 2Ghz+ AVX2 / SiMD / NANO<div><br />*<br /><br /><h4 style="text-align: left;">Example use of upscaling of non uniform size</h4><br /><div>One way to use this is if you want to change the Vertical/Horizontal plane so that it is more dense,</div><div><br /></div><div>With the MicroLED and MicroLensing formula; you may require something more than a long LED Pixel..</div><div>So the 6 Way Matrix is ideal when you simply want to resize the image in one or two directions...</div><div><br /></div><div>While the screen is still stated as 16:9 for formula; You might have square LED Pixels!</div><div>But you still would prefer not to use a lot of CPU for it; Mind you if you operate per line HD is still 1080 operations per frame.</div><div><br /></div><div>But if you output 16 Lines per send & overlap the last 2 lines in the next write cycle:</div><div><br /></div><div>1920x1080</div><div>77.14 14Line Writes + 2 lines of overlap for 16 Line write.</div><div>AKA 77 dimming zones vertical; With as many modifications as you want on line write.</div><div><br /></div><div>This stops banding, printers show the effect of overlap printing but screens are the inverse; In printing we print slightly less in the banding area.</div><div><br /></div><div>RS</div><br />*</div><br /><h4 style="text-align: left;">MathML & scaling</h4><br />https://www.w3.org/TR/MathML2/chapter2.html<br />https://developer.mozilla.org/en-US/docs/Web/MathML/Examples<br /><br />Additional scaling example is the recently introduced MathML & scaling available in chrome source<br /><br />In reference to scaling in displays & fonts we have two additional sources of internal resolution enhancement,<br />At least in terms of web browsers and Use Interfaces UI<br /><br />With the two manageable systems we could potentially do quite a lot without increasing bandwidth costs..<br /><br />Scaling down slightly higher resolution fonts & images & videos; To stunning details!<br /><br />To be frank MathML appears not to be machine learning optimised; However in CSS markup we could use MathML..<br />To dynamically scale a webpage to DPI & Size & where preferred to a lower scaling & thus improved readability!<br /><br />If we can take scaling as automatic input & read the results internally we could do quite a bit with it,<br />However MathML is quite good for things like price range conversion : £ Euro & $ & yen<br /><br />we can use MathML quite flexibly; But is it a calculator ? It should be,<br />So we shall see!<br /><br />RS</div><div><br /></div>MathML is not only useful for displaying mathematical content, but also for performing calculations and conversions.. <br /><br />This means that mathematical content can be displayed at any size and resolution without pixelation or distortion.<br /><br />Another example of scaling in displays and fonts is the use of internal resolution enhancement techniques, such as subpixel rendering and antialiasing,<br /><br />These techniques improve the appearance and readability of text and images by smoothing out jagged edges and enhancing contrast,<br /><br />For instance, MathML can be used to convert between different currency units, such as pounds, euros, dollars, and yen.<br /><br />MathML can also handle complex calculations involving fractions, roots, powers, trigonometry, and more.<br /><br />RS<div><br /><div>*<br /><br /><h4 style="text-align: left;">TOPCloud Scaled Flexible WebASM & WebGPU & MathML!</h4><br />Quite flexible for use on Monitors & TV's; Light processor load on simple tasks & offloadable such as TOPCloud!<br /><br />You may be thinking Offloading is impracticable because that requires one of two things:<br /><br />JIT Compiler Dongle..<br />USB device such as Firestick or GPU & CPU (With OpenCL Compat)<br /><br />Server! so internet & service provision!<br />Impossible? No; WebAdvert supported TV's need both!<br />So why not HPC TOPCloud? could make a HOT TV a lot cooler & Eco friendly with Server repeating tasks:<br /><br />Scaling<br />Quality Service<br />Service availability<br /><br />TOPCloud Offload Logic:<br /><br />In terms of WebASM & WebGPU & MathML; TOPCloud provides sufficient advantages to be considered a core utility..<br /><br />While Offloading repeating content such as Siteload core stack (Server) & Localising configuration such as Webpage size & DPI & Dynamic font arrangements that require thought.<br /><br />In terms of Offloaded function & Efficient system load for large configurations..<br /><br />Especially efficient configurations such as TPU, Coral, GPU work & Cloud CPU that have large optimised stacks & installed drivers.<br /><br />RS</div><div><br /></div><div>*</div><br /><h4 style="text-align: left;">3D Matrix Web Codecs</h4><br />Are presented as being JIT Compiler re-encoded when required; Frequently WebASM, WebGPU Code, JS...<br />Audio, Video, Sensation, Code Runtimes.<br /><br />Web Codecs for devices are a modern concept & are available for common websites such as news & music,<br />devices such as Alexa Echo & Google Dot & Bluetooth Devices?<br /><br />Media players & BT devices particularly suffer from small Storage potential!<br />So Web Codecs downloaded to the device from a source; Such as a smart phone or computer..<br />Are a clear-minded solution!<br /><br />JIT Compiler<br /><br />3D Matrix Tables in FMA, Mul & ADD code to be automatically recompiled locally when required!<br />Directed to a common API, Direct Compute, WebGPU, WebASM, Jit Compiler OpenCL<br /><br />Many Operations can be done from unique device specific optimisation; Examples:<br /><br />API, DirectX & OpenCL & Vulkan & WebGPU & WebASM<br />Texture & Audio Shaders.<br />Digital Streaming<br /><br />Bluetooth NANO SiMD & API<br />Digital TV in H266, VP9 & AV1,<br /><br />Locally compiled accelerators should be respected first; Such as the output & input 3D Matrix & CPU & GPU Acceleration engine..<br /><br />Code can include Matrix converters into common output format such as WebP & Textures & BC, DXT Compression presentation; Vulkan, OpenCL & DirectX & Texture & Audio Shaders.<br /><br />Java, JS & WebASM are examples with operator mechanisms & JIT Compiler optimisation..<br />Minimising storage requirements for good compatibility while maximising performance.<br /><br />RS</div><div><br />Requirements:<br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />*<div><h4 style="text-align: left;">Scaling; We can classify by colour or creativity. (c)RS</h4><br />If you use TOPCloud, you can share between different displays in the TOP's Sense..<br />but mostly you would need cloud presence,<br /><br />Mostly this would be about making the most out of TOP heavy Business GPU & personal ones in your computer or consoles.<br /><br />But sharing common tasks such as scaling movies by type or by identifying a single movie to upscale...<br /><br />Now you might be asking what we would be doing there?<br />Well a single movie uses the same materials in our ML; We can analyse the class & optimise the scaling by class..<br /><br />For those familiar with games & FSR; We familiarise our code with a single game!<br />By doing this we improve our product and can therefore classify by:<br /><br />Resolution<br />Style<br />Speed<br />Type, FPS for example & RTS<br /><br />We can classify by colour or creativity...<br /><br />We do not simply have to roll the dice on General Scaling, We can use classifiers:<br /><br />Title<br />Scale<br />Type<br />Speed<br />Frame Rate<br />Colour & Composure<br /><br />Rupert S</div><div><br />PoCL Source & Code<br />https://is.gd/LEDSource<br /><br />*</div><div><br /></div>Vector Instructions<br />https://science.n-helix.com/2023/06/map.html<div><div><div><br /></div><div>https://science.n-helix.com/2022/08/simd.html<br />Vector Encoding : VECSR https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />*<div><br />Specification for Open Compute & Gaussian Interpolation & JIT Compile<br />Displacement Micromap : Interpolation & Extrapolation Policy : RS<br />https://science.n-helix.com/2023/02/smart-compression.html</div><div><br /></div><div>Concept of JIT OpenCL<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html</div><div><br /></div><div>Demosaicking DoFP images using edge compensation method based on correlation<br />https://opg.optica.org/oe/fulltext.cfm?uri=oe-31-9-13536&id=529002<br />https://iopscience.iop.org/article/10.1088/1361-6501/accbdd/pdf<br /><br />FPGA 'Xilinx Virtex-II' HPC application Multiple-Applications & Image-Net & Matrix-Multiplication - H-SIMD machine _ configurable parallel computing for data-intensive HPC<br />https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations<br /><br />A SIMD architecture for hard real-time systems<br />https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2<br /><br />Multiple Parallel SiMD Single Cycle - A Multi‐instruction Streams Extension Mechanism for SIMD Processor<br />https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/cje.2017.09.013</div><div><br />Ideal for 4Bit Int4 XBox & Int8 GPU<br />PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors - Bus-width 8-bit, 4-bit, 2-bit and 1-bit<br />https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/</div><div><br />Vulkan's, <br />Useful for Presentation with AA, work Rendering/Upscaling Shaders<br />https://drive.google.com/file/d/1KxxKRLOH01m5IYqAy9DeR9qq8gHIEdSs/view?usp=sharing<br /><br />OpenCL, Hardline minimal code kernels,<br />(Code AA Processing yourself) Useful for work Rendering/Upscaling Shaders<br />https://drive.google.com/file/d/1SYLr0JwWD-DbbXHsrANxkFe2hBrn1cZf/view?usp=sharing<br /><br />Shaders; Useful for texture cache & presentation<br />CL Shaders 2<br />https://drive.google.com/file/d/1c2K5GooOKY-kPHxiqc27A_l3pkcYxvZU/view?usp=sharing<br />V1.6 Shaders<br />https://drive.google.com/file/d/1C3Q9-LvB0T8p6XHpoZynttxuV2Eunwg2/view?usp=sharing,<br /><br />Gaussian Interpolation, Useful for upscaling & AA<br />https://drive.google.com/file/d/1sjMpGVhvULsSloeoQ_zikzX2AzZlUBtY/view?usp=sharing</div><br />Texture Encode Source<br />https://drive.google.com/file/d/1udWU4slmZkUGcagcJl1KwFWh5FJ5ScoN/view?usp=sharing<br /><br /></div><div>*<br />Image Optimisation Training Datasets:(Download Folder to directory)<br /><br />Upscaling Training Sample Set: <br />https://drive.google.com/drive/folders/16Z0izDX0JyajyLgWbH0E2W-RyKv_CckT?usp=sharing<br />Upscaling Training Sample Set, Eco Samples:<br />https://drive.google.com/drive/folders/1_gUJ4F9ibQWCMFX1IDSv708vA7-bmNCp?usp=sharing<br />Space Training Samples Set<br />https://drive.google.com/file/d/10lHycalqZFmsp_gwE5ym47GbEDv36pZJ/view?usp=sharing</div><div>*<div><br />*<div><br /></div><a href="https://is.gd/WaveletData">https://is.gd/WaveletData</a><br /><br /><div>Texture Compressors<br /><a href="https://github.com/BinomialLLC/basis_universal">https://github.com/BinomialLLC/basis_universal</a><br /><a href="https://github.com/darksylinc/betsy">https://github.com/darksylinc/betsy</a></div><div><br /></div><div>Python ML Image denoisers, Very heavy denoising<br /><a href="https://github.com/cszn/BSRGAN">https://github.com/cszn/BSRGAN</a><br /><a href="https://github.com/cszn/SCUNet">https://github.com/cszn/SCUNet</a></div><div><br />To Compress using CPU/GPU: MS-OpenCL<br /><a href="https://is.gd/MS_OpenCL">https://is.gd/MS_OpenCL</a><br /><a href="https://is.gd/OpenCL4X64">https://is.gd/OpenCL4X64</a><br /><a href="https://is.gd/OpenCL4ARM">https://is.gd/OpenCL4ARM</a><br /><br />PoCL Source & Code<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><div><br />https://is.gd/BTSource<br /><br /><a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a><br /><a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby</a><br /><a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a> &<br /><a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a><br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br />DSC, ETC, ASTC & DTX Compression for display frames<br /><br />These are the main XRGB : RGBA Reference for X,X,X,X<br /><a href="https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing">https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing</a><br /><a href="https://drive.google.com/file/d/12vbEy_1e7UCB8nvN3hYg6Ama7HIXnjrF/view?usp=sharing">https://drive.google.com/file/d/12vbEy_1e7UCB8nvN3hYg6Ama7HIXnjrF/view?usp=sharing</a></div><div><br /></div><div><a href="https://github.com/KhronosGroup/Vulkan-Web-Registry/raw/main/specs/1.3-khr-extensions/pdf/vkspec.pdf">Khronos-1.3Extens</a><br /><div>*<br /><div><h4 style="text-align: left;">The Smart-access </h4><br />[Innate Compression, Decompression, QoS To Optimise the routing, Task Management To optimise the process] : Task Managed Transfer : DMA:PIO : Transparent Task Sharing Protocols<br /><br />The following is the initiation of the Smart-access Age<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />Vector Encoding : VECSR https://science.n-helix.com/2022/04/vecsr.html</div><div><br /></div><div>QoS To Optimise the routing:Task Management To optimise the process<br /><br /></div><div>https://science.n-helix.com/2021/11/monticarlo-workload-selector.html<br /><br />https://science.n-helix.com/2023/02/pm-qos.html<br /><br />https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html</div><br />https://science.n-helix.com/2023/03/path-trace.html<div><br /><br /></div>FPGA 'Xilinx Virtex-II' HPC application Multiple-Applications & Image-Net & Matrix-Multiplication - H-SIMD machine _ configurable parallel computing for data-intensive HPC<br />https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations</div><div><br /></div><div>A SIMD architecture for hard real-time systems<br />https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2<br /><br />Ideal for 4Bit Int4 XBox & Int8 GPU<br />PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors - Bus-width 8-bit, 4-bit, 2-bit and 1-bit<br />https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/<div><br /></div><h4 style="text-align: left;">Transversal processing availability : Transparent Task Sharing Protocols</h4><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br /><h4 style="text-align: left;">Machine Learning</h4><br />https://science.n-helix.com/2022/10/ml.html<br /><br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<div><br /></div><div><h4 style="text-align: left;">Innate Compression, Decompression</h4><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html</div><div><br /></div><div>https://science.n-helix.com/2022/09/audio-presentation-play.html<br /><br />https://science.n-helix.com/2022/08/simd.html</div></div></div></div><div><br /></div>Strobe Line by Line Run Length Compression DVB, NTSC, VESA :RS Approved <br /><a href="https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing">https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing</a><div><br /></div>Examples of compression<br /><a href="https://godotengine.org/article/betsy-gpu-texture-compressor/">https://godotengine.org/article/betsy-gpu-texture-compressor/</a><br /><a href="https://github.com/darksylinc/betsy/blob/master/Docs/technical_doc_advanced.md">https://github.com/darksylinc/betsy/blob/master/Docs/technical_doc_advanced.md</a></div></div></div></div><div><br /></div>*<br />Gain the diplomacy of a Scaler Scailing Cause : News on the Gaining<br />Diplomacy World Wide<br /><a href="https://drive.google.com/file/d/1OfG8X_PuqAyICbI-wrLar2trSiz5kFix/view?usp=drive_web">https://drive.google.com/file/d/1OfG8X_PuqAyICbI-wrLar2trSiz5kFix/view?usp=drive_web</a><br /><br />Gain the diplomacy of a Scaler Scailing Cause : News on the Gaining<br />Diplomacy World Wide 2<br /><a href="https://drive.google.com/file/d/1T5Qx_k9EIousRox0H7sixkgEWmBINQIB/view?usp=drive_web">https://drive.google.com/file/d/1T5Qx_k9EIousRox0H7sixkgEWmBINQIB/view?usp=drive_web</a><br />*<div><br /></div>Sound Open Firmware : Supported by Intel, AMD, Realtek, MediaTek, DTS, Dolby, RS & so-on<br />S.O.F provides an open source audio DSP firmware and SDK for audio or signal processing on modern DSPs<br /><br /><a href="https://thesofproject.github.io/latest/algos/index.html">https://thesofproject.github.io/latest/algos/index.html</a><br /><a href="https://www.sofproject.org/">https://www.sofproject.org/</a><br /><a href="https://github.com/thesofproject">https://github.com/thesofproject</a></div></div><div><br /></div>*****<br /><br />Good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />These are the addresses directly of some good ones; DNS & NTP & PTP 2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b 142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111<br /> <br />*****<br /><br />Andro-linux libs : x86 & ARM : Learn<br />https://drive.google.com/drive/folders/1BRQOIK1eAUEMnTTGjsQ0h0g6jGLzWqZI<br /><br />Python Deep Learning:<br /><br />AndroLinuxML : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing<br />Linux : https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing<br />Windows : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing<br /><br />good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-59714030240151731472023-02-23T07:27:00.014+01:002023-07-15T18:35:37.795+02:00PM-QoS - Processor Model QoS Tree for TCP, UDP & QUICC<h4 style="text-align: left;">Quality of Service Protocol & the TCP & UDP & QUICC Protocols : RS</h4><div><br /></div>Extremely good for HDMI & DisplayPort & USB/URT & 2.4G/Bluetooth : In regards to Codec development and flow & device control,<br />Audio, Video, Process & Command<div><br />https://www.ietf.org/archive/id/draft-scheffenegger-congress-rfc5033bis-00.txt<br /><br />Congress - Congestion Control - Combined Network QOS Routing Table Tree-Swarm - Quality of Service Protocol & the TCP & UDP & QUICC Protocols<br /><br />*<br /><br /><h4 style="text-align: left;">Processor Model for TCP, UDP & QUICC : (c)RS</h4><br />To put TCP, UDP & QUICC in a proper place in your minds for application,<br />Think about Applying them to processors; Particularly Neuromorphic, ML & GPU/CPU!<br /><br />How exactly?<br /><br />Address space modelling for data transfer:<br />Between RAM, HDD/SDD & CPU & Internally mapping across cache & Sparse Model NAND Gates.<br /><br />In the situation internal to Device Gates & Logic Circuits; We map address spaces across the processor,<br />We internalize the location logic as a network & utilise TCP, UDP & QUICC,<br /><br />We do not need the sending strategy of Data Transfer to be Random; Random wastes Bandwidth!<br />But we do need a QOS Data Transfer policy & Networking Tactics!<br /><br />Why ? Not all processor functions are directly connected in MultiChip & 3D Model Processor.<br /><br />*<br /><br />By thinking about the Processor Model for TCP, UDP & QUICC : (c)RS<br /><br />We soon find the best light TCP, UDP & QUICC Network Strategy.<br /><br />Think about this model designing the Network Protocols<br /><br />RS<br /><br />*<br /><br />"Kevin Cisco-Kevin<br /><br />Date: Tue, 21 Feb 2023 08:32:03 -0800<br /><br />Subject: Re: To think about the Network Model : Processor Model for TCP, UDP & QUICC : (c)RS<br /><br />What we really need is a transfer layer mechanism modeled after Swarm<br /><br />where packets are broken up into chunks and reassembled after<br /><br />handshaking. But we don't live in that world."<br /><br />Kevin Suggests we think about Swarm : RS : What do i think on average (Swarm)<br /><br /><h4 style="text-align: left;">PM-QoS - Swarm : Networking TCP UDP QUICC NTP DNS</h4><br />I think that Swarm; Multi Target Networking is a primary method under consideration for QUICC & UDP & NTP Responses,<br /><br />Swarm is high noise; High Volume Send & Receive,<br />With alteration though Statistical & Machine rout optimisation... That bandwidth cost reduces, <br />ML : Neural network, Send, Receive & Confirm, Swarm, In effect on globally predictable commodities such as:<br /><br />NTP, DNS (popular), News & Decentralised command...<br /><br />Can work! Network Command requires directly applied logic; What i mean is : Confirmed Command & Reception affirmation & Action!<br /><br />So i propose the following:<br /><br />Combined Network QOS Routing Table Tree-Swarm : CNetQSRT-Tree-Sw : Rupert S 2023-02<br /><br />QOS Applied to QUIC, TCP, UDP Data packet Anagrams<br /><br />What I mean is that QUIC is a protocol that passes data through multiple network adapters like a tree,<br />What we do is send information on the data transfer abilities of each adapter (locally) & prefer a route,<br />We prioritise routes based on data flow statistics & choose thereby optimum routes...<br /><br />By Statistically collating data locally (in network adapter group, per localised network...<br /><br />We will further select a route based on those statistics; Machine Learning is not obligatory & hence there is less to go wrong,<br /><br />Routers do not need to be as modern & We can collect that information for routing tables & Create Optimum routes; Like a tree; With little need for control or modification...<br /><br />All TCP, UDP & QUIC & NTP & DNS packets get to the required destination fast & with low latency.<br /><br />QOS is clearly of advantage to QUIC, Because we can assess the data throughput of the modems/Network adapters & change routes? <div>For optimum performance & minimum error or work.<br /><br />Swarm:ML (Known Receiver : Known Sender)<br /><br />QOS<br />NTP<br />DNS Global Submit <br /><br />Network Tunnelling, For example: Torado, Large Download Acceleration<br /><br />Secure Network Tunnelling, For example: VPN, VPS, Ethernet, 3G, 4G LTE, Volt, 5G Volt, Telecommunications Networking & GPS)<br /><br />Defined routing with QOS Network optimisation (Localised) & Data bandwidth data (Localised)<br /><br />Global Zone routing through tables...<br /><br />Statistic Enhanced Routing & Delivery<br /><br />*<br /><br /><h4 style="text-align: left;">QOS : Quality Of Service protocol : RS https://is.gd/LEDSource</h4><br />Personally I believe QOS : Quality Of Service protocol be introduced<br />to all network traffic,<br />Primarily the Point A to point Z route needs planning first.<br /><br />QOS Datagram<br />Network throughput Capacity of the network card<br />Advertise Capacity in local network<br />Plan routes based on network capacity<br /><br />So the Quality Of Service Protocol needs to send a datagram to the<br />network adapter of site:<br /><br />A to Z<br /><br />A list of local routes needs to be cached & prioritised based on<br />Network point A's network capacity & priority,<br /><br />The rout needs Point A to Z mapped & Z to A<br /><br />We then send data with a packet listing preferred routes<br /><br />[QOS][Origin : Target][Preferred route list forward sent][Network Performance Metric Packet]<br /><br />[Origin : Target][Preferred route list forward sent][Semi Static Route Tunnel]<br /><br />[Packet ID][Origin : Target][Data Packet]<br /><br />Searching for a route with every packet costs processor Cycles; So<br />preferred routes need to be tunnelled & Secured with TLS<br /><br />Rupert S<br /><br />https://is.gd/CryptographicProves<br /><br />Vectors & maths<br />https://science.n-helix.com/2022/08/simd.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />Networking & Management<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2022/01/ntp.html<br /><br />Faster Maths & ML<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Focus on Quality<br />https://science.n-helix.com/2022/09/ovccans.html<br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /></div><div><br /></div><div>Code Speed<br /><br />https://science.n-helix.com/2022/08/simd.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br /><br /><br /></div><div>Chaos<br /><br />https://science.n-helix.com/2022/02/interrupt-entropy.html<br /><br />https://science.n-helix.com/2022/02/rdseed.html<br /><br />https://science.n-helix.com/2020/06/cryptoseed.html<br /><br />Example of a Secure Tunnel System:<br /><br />https://is.gd/SecurityHSM https://is.gd/WebPKI</div><div><br />TLS Optimised <br />https://is.gd/SSL_Optimise<br /><br />Ethernet Security<br />https://is.gd/EthernetTunnelOpt</div><div><br /></div><div>*****<br /><br /><h4 style="text-align: left;">Suitable for codec, Texture, Video Element, Firmware & ROM, Executable, Storage & RAM, DLL & Library runtimes, CSS & JS & HDMI & DisplayPort VESA Specifications : </h4><br /><a href="https://science.n-helix.com/2023/02/pm-qos.html">https://science.n-helix.com/2023/02/pm-qos.html</a><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br />Install and maintain as provided HPC Pack, Exactly as presented with nodes & functions; Be as generous as you can towards our research goals.<br /><br /><a href="https://science.n-helix.com/2018/09/hpc-pack-install-guide.html">https://science.n-helix.com/2018/09/hpc-pack-install-guide.html</a><br /><br />RS</div><div><br /></div><div>*****</div><div><br /></div><h4 style="text-align: left;">PM-QoS - Processor Model QoS Tree for TCP, UDP & QUICC</h4><br />The Method of PM-QoS Roleplayed in a way that Firmware & CPU Prefetch ML Coders can understand.<br /><br />Environment:<br />https://science.n-helix.com/2021/11/monticarlo-workload-selector.html<br />https://science.n-helix.com/2023/02/pm-qos.html<br />https://science.n-helix.com/2022/03/security-aspect-leaf-hash-identifiers.html<br /><br />Multiple Busses &or Processor Features in an Open Compute environment with competitive task scheduling<br /><br />[Task Scheduler] Monticarlo-Workload-Selector<br /><br />We prioritise data traffic by importance & Need to ensure that all CPU Functions are used...<br /><br />In the case of a Chiplet GPU We need to assign function groups to CU & QoS is used to asses available Multiple BUSS Capacities over competing merits,<br />[Merits : Buss Data Capacity, Buss Cycles, Available Features, Function Endpoint]<br /><br />PM-QoS is a way of Prioritising Buss traffic to processor functions & RAM & Storage Busses that:<br /><br />States a data array such as:<br /><br />Buss Width<br /><br />divisibility ((Example) Where you transform a 128Bit buss into 32Bit x 4 Data motions and synchronize the transfers,<br /><br />Data Transfer Cycles Available<br /><br />Used Data Rate / Total Data Throughput Rate = N<br /><br />(c)Rupert S https://science.n-helix.com</div><div><br /><div><br />**************************** Reference Ambition<br /><br />Title: Specifying New Congestion Control Algorithms<br /><br />Date: Fri, 17 Feb 2023 16:39:25 +0100<br /><br />https://rscheff.github.io/rfc5033bis<br /><br />https://github.com/rscheff/rfc5033bis/issues<br /><br /><br /><br /><br />Title: Specifying New Congestion Control Algorithms<br /><br />Document date: 2023-02-17<br /><br />https://www.ietf.org/archive/id/draft-scheffenegger-congress-rfc5033bis-00.txt<br /><br />Status:<br /><br />https://datatracker.ietf.org/doc/draft-scheffenegger-congress-rfc5033bis/<br /><br />Abstract:<br /><br /> The IETF's standard congestion control schemes have been widely shown<br /><br /> to be inadequate for various environments (e.g., high-speed<br /><br /> networks). Recent research has yielded many alternate congestion<br /><br /> control schemes that significantly differ from the IETF's congestion<br /><br /> control principles. Using these new congestion control schemes in<br /><br /> the global Internet has possible ramifications to both the traffic<br /><br /> using the new congestion control and to traffic using the currently<br /><br /> standardized congestion control. Therefore, the IETF must proceed<br /><br /> with caution when dealing with alternate congestion control<br /><br /> proposals. The goal of this document is to provide guidance for<br /><br /> considering alternate congestion control algorithms within the IETF.<br /><br />The IETF Secretariat</div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-41208903435712430942022-12-03T14:42:00.007+01:002023-07-02T09:47:59.929+02:00Precision Differential Rollover Math Error Solve - RS<div>Precision Differential Rollover Math Error Solve - (c)Rupert S</div><div><br /></div>{Solve} : {{Maths Roll Error on 24Bit Audio versus 32Bit} ~= Stutter} : Windows 3D Audio, DTS & Dolby Atmos 2022-11-30 RS https://is.gd/LEDSource<br /><br />Windows 3D Audio, DTS & Dolby Atmos 2022-11-30 RS https://is.gd/LEDSource<br /><br />Solve Basic numeric math rollover errors on float and integer operation in applications; runtimes; applications & DLL & Processors : RS<br /><br />*<br /><br />{Solve} : {Maths Roll Error} : (c)RS<br />{Maths Roll Error on 24Bit Audio versus 32Bit} ~= Stutter<br /><br />Additional roll, Error margin on 32Bit maths Float with 24Bit 5 point margin roundups,<br /><br />A 32Bit float rolls up on a single operation 226526554817.{24Bit float + Error roundup} .9> .49 = .5+ = roll up.. <br /><br />R={5+ or 4- | 0.45+ or 0.44-} : or {0.445, |> 0.444444444445 |> 0.4 N4 +Decimal Places +5}<br /><br />Clipping operation depth of float; Is 3 operations or 2 with Stop count = 1 to 24 bit places + 1 or 2 for error rolling, up or down.<br /><br />Precision Clip<br />Math OP | Clip > Cache {Math OP <> Use}<br /><br />Precision Counter<br />Math OP + Counter(internal to FPU:CPU | Stop > Cache {Math OP <> Use}<br /><br />*<div><br /></div><div>*****<br /><br /><h4 style="text-align: left;">Several Problems that are solved by application of PDRMES: Rollover Error solve:</h4><br />JPG's use 16Bit Wavelets & AVX is 128Bit, So a small bit of precision can be added & more data saved for a reduced storage cost; Additionally Traditional JPG used 8Bit per channel (24Bit) Colour pallet & we can solve a subtle colour differential in the pallet.<br /><br />MP3 14Bit Wavelet; MPG4A used 16Bit wavelets; So wavelet precision improvement means a better audio experience.<br /><br />Any form of Texture or Image or video type that traditionally saves to 8Bit, > 16Bit would see improvements:<br /><br /><h4 style="text-align: left;">Rollover Error High importance Error table:</h4><br />Wavelet: 8Bit to 16Bit & more<br />Colour table<br />Colour Conversion<br />Colour Lookup Table : LUT<br /><br />Down-Sampling & Up-Sampling.<br /><br />Rupert S<br /><br />*****</div><div><br />Windows 3D Audio, DTS & Dolby Atmos should do to at least 32Bit 384Khz 7.1 Channels, <br /><br />There is absolutely no reason a 64Bit processor cannot do 64Bit audio, <br />Mind you 32Bit Integer is around 60% of total CPU Support with 64Bit divided by 2, <br /><br />So 32Bit Audio is 100% speed conformant & there are few reasons to reduce it to 24Bit or 16Bit without processing benefaction; Such as Error management on 24Bit on 32Bit instruction: <br /><br />Both AMD & Intel X64 <br /><br />Rupert S 2022-11-30<br /><br /><div>"State-of-the-art approaches such as OpenMP and OpenCL"<br />https://is.gd/LEDSource<br /><br />FSR_FL RT: Proven<br /><br />ML Training Telescope, Camera, Video & Image Display Enhancement, Produced 2 Hours ago! 2022-12-02 https://www.science.org/doi/pdf/10.1126/sciadv.add3433?download=true<br /><br />https://is.gd/MLCodecShaping<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html<br /><br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2022/03/simd-render.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br /><br />https://science.n-helix.com/2022/10/ml.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html</div></div><div><br /></div><h4 style="text-align: left;">Float IEEE 754 2020-02</h4><br /><a href="https://science.n-helix.com/2020/02/fpu-double-precision.html">https://science.n-helix.com/2020/02/fpu-double-precision.html</a><br /><br /><a href="https://science.n-helix.com/2022/12/math-error-solve.html">https://science.n-helix.com/2022/12/math-error-solve.html</a><br /><br /><a href="https://science.n-helix.com/2021/02/multi-operation-maths.html">https://science.n-helix.com/2021/02/multi-operation-maths.html</a><br /><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-30162502533519607202022-11-20T13:11:00.004+01:002022-11-20T16:01:47.104+01:00The principle of the Bit'...' DAC (c)RS<h4 style="text-align: left;">The principle of the Bit'...' DAC (c)Rupert S</h4><br />(yes since 1992)<br /><br /><br /><div>To the world I presented the 1Bit DAC,<br /><br />Principally it draws waves like a pencil by frequency; So 500Mhz DAC is great!<br /><br />DAC 1Bit :<br /><br /> . . .<br />. .. .. . .<br /> . ..<br /><br />DAC 3Bit : Dithers/Interpolates the pattern with 3 Points per one & averaging<br /><br /> . . .<br />. .. .. . .<br /> . ..<br /><br />A Room Setup : 7.1 for example is 7, 1 Bit, 3Bit, 5Bit,More, DACs...<br /><br />1 per Channel<br /><br />We however place one more DAC between each channel to interpolate/Dither<br /><br />3D Audio is up and down speaker DACs<br /><br />ADC : Analog to digital conversion presents the analogue input into the matrix sum calculator, to collect the bits into groups along the lines of : 8Bits, 16Bits, 32Bits, 48Bits ....N-Bits<br /><br />Right 1 Bit DAC works By two principles: (With Capacitor)<br /><br />1:<br />Vinyl output is varying frequency of a continuous analogue nature & essentially replication of frequency variance, Suitable for a single line instrument of almost infinite frequency variance, defined by the Crystal output Hz multiplier..<br /><br />2:<br />Vinyl output but we use a higher frequency than the output Hz & we interleave the frequency submission over multiple frequencies by a Hz factor : Base Hz = 48Kzh | DAC Frequency = 48Kzh * X | = Notes/Tones Per Hz<br /><br />Interleaved frequency response.<br /><br />We use capacitors to solve WATT related power drops from quiet instruments dominating another 1 Bit DAC on the same line.<br /><br />SBC is our model; MPEG/Codec Banding:<br /><br />52 Bands = 52 Pins | 52 Pins plus 10 band hopping double note 1Bit DAC = 64Bit,<br /><br />64Bit 1Bit DAC Pins has all 52 Bands of SBC Covered in a pure note + 10 Band hoppers,<br /><br />Alternatively 32Bands 1Bit DAC & 32Bit Hopper 1Bit DAC.<br /><br />32Bit Hopper Analog 1Bit DAC = 32Notes continual (WOW)<br /><br />Higher frequency DAC = Interleaved BIT, But it has to overlay every note but need less Bit. <br /><br />Rupert S</div><br /><h4 style="text-align: left;">Banding Monitor, TV & 3D technologies & Codecs: RS</h4><br />The frequency response of the Video DAC is around 600Mhz.<br /><br />The band estimate is in reference to various technologies & Codecs: <br /><br />12Bands to 35Bands on SCART Cable with a 15Mhz to 100Mhz Clock,<br /><br />20Bands to 60Bands VGA Port Digital<br /><br />35 Bands to 250 Bands recommended VGA+ HDMI 1.4a to HDMI 2.1b<br /><br />Each band consisting of blocks of data in : Data Width : 8Bit, 10Bit, 12Bit, 14Bit, 16Bit <br /><br />This consists of a high colour & contrast; WCG & HDR Content.<br /><br />Compression is advised.<br /><br />Rupert S<div><br /></div><div>*<br /><div><br /><a href="https://science.n-helix.com/2021/11/expand-formula-sonarus.html">https://science.n-helix.com/2021/11/expand-formula-sonarus.html</a><br /><br /><a href="https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html">https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html</a><br /><br /><a href="https://science.n-helix.com/2022/11/variable-sensitivity-cable-technology.html">https://science.n-helix.com/2022/11/variable-sensitivity-cable-technology.html</a><br /><br /><a href="https://science.n-helix.com/2021/12/3d-audio-plugin.html">https://science.n-helix.com/2021/12/3d-audio-plugin.html</a><br /><br /><a href="https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html">https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html</a><br /><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br /><a href="https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html">https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html</a><br /><br /><a href="https://science.n-helix.com/2021/11/wave-focus-anc.html">https://science.n-helix.com/2021/11/wave-focus-anc.html</a><br /><br /><a href="https://science.n-helix.com/2021/10/noise-violation-technology-bluetooth.html">https://science.n-helix.com/2021/10/noise-violation-technology-bluetooth.html</a><br /><br /><a href="https://science.n-helix.com/2021/11/ihmtes.html">https://science.n-helix.com/2021/11/ihmtes.html</a><br /><br />********<br /><br />(My work does not guarantee your product is GPL you may share with me) "State-of-the-art approaches such as OpenMP and OpenCL" https://is.gd/LEDSource<br /><br />LC3Plus Source for HDMI & DisplayPort Proposal <a href="https://is.gd/LC3PlusSource">https://is.gd/LC3PlusSource</a><br /><br /><a href="https://www.etsi.org/deliver/etsi_ts/103600_103699/103634/01.03.01_60/ts_103634v010301p0.zip">https://www.etsi.org/deliver/etsi_ts/103600_103699/103634/01.03.01_60/ts_103634v010301p0.zip</a><br /><br /><a href="https://www.etsi.org/deliver/etsi_ts/103600_103699/103634/01.03.01_60/ts_103634v010301p.pdf">https://www.etsi.org/deliver/etsi_ts/103600_103699/103634/01.03.01_60/ts_103634v010301p.pdf</a><br /><br />Free to build!<br /><br />You know you allow LC3Plus upto 500Kb/s? why not smash a load of<br />"terrible codecs" & make a upto 1Mb/s band or even better 1.3MB/s &<br />for DisplayPort & HDMI 7MB/s ...<br /><br />Bound to be a few casualties to Van Brahms! Mastery!<br />& while you are at it, make 3D Audio specifications for Dolby & DTS Available!<br /><br />Sure they would love it.<br /><br />Be lovely!<br /><br />https://www.iis.fraunhofer.de/en/pr/2022/20221011_lc3plus.html<br /><br />https://www.iis.fraunhofer.de/en/ff/amm/communication/lc3.html<br /><br />"State-of-the-art approaches such as OpenMP and OpenCL"<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-91945585630483192832022-11-13T13:43:00.007+01:002022-11-13T15:52:53.838+01:00Variable Sensitivity Cable TechnologyVariable Sensitivity Cable Technology (c)RS<br /><br />USB & HDMI & DisplayPort & Cables Transmitting Data such as PCI & RAM, <br /><br />High priority technology <br /><br />(The actual cable can be any Voltage you need, higher V means faster transmitting & lots more errors) (c)Rupert S<br /><br />Twisted pair cable sets for HDMI & DisplayPort & other cabling need a protocol that does more than Error correct from 2 to 5 tiny cables or twisted cables per pin! with error correction...<br /><br />Can in base mode transmit more than one signal; By filtering data speeds.<br /><br />Transmitting multiple wave lengths; Varying frequencies....<br /><br />Each cable can have a wavelength polarity transmission using quartz timing crystals & transistor energizers (converting to the faster 5v, with a transistor & Crystal)<br /><br />We can do the same for light port, Light port relies on higher frequency fiber optic cable connect..<br /><br />The relative speed of a static pin in a PC is not too much of a problem, frequencies of static pins can be quite high; At least 500Mhz (Shielded),<br /><br />Cables in motion however are the reason we need the cables to be as motionless as possible, So errors are static to Machine Learning & Error correction by statistical observation software & firmware.<br /><br />We can however with a Twisting cable set & a single pin, Multiply the frequency transmission by using per cable selectivity with Quart's timing crystals, these do not need to be complex!<br /><br />Allowing our cable PIN (DP,HDMI,USB Port for example(Static)) to multiply the frequency response by multiple cables per pin.<br /><br />We can however; Multiply the error correction, By varying the output voltage along the side of the pin, By varying the resistance slightly with a 2 to 5 segment pin with tiny response differences regarding frequency or voltage.<br /><br />We may indeed improve classic cable connects therefore by clearly defining each transmitted frequency...<br /><br />Clearly separate..<br /><br />But not a problem with compatibility.<br /><br />We shall see!<br /><br />Rupert Summerskill 2022-11-12<div><br /></div><a href="https://bit.ly/VESA_BT">https://bit.ly/VESA_BT</a><br /><br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html<br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br />https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html<br />https://science.n-helix.com/2022/03/simd-render.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.htmlRed Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-18352278531278699632022-11-06T01:14:00.006+01:002022-11-26T13:17:53.689+01:00Frame Expand GEN 3<h4 style="text-align: left;">Frame Expand GEN 3 - Pre Alpha Frame Prediction Motion Compensation Micro Flow Frame & Sharpen with Texture Preload & Removal (c)RS Development 2022</h4><br />On the Subject for FSR3 & XeSS & ML & TV, Frame generation, Leveraging predict for video between 2 frames would work! H264, H265, VVC, AV1, VP9, DSC; Hardware Codecs all leverage predict!<br /><br />Predict is an 8x8 Pattern & gets the basic ball rolling if you have 2 frames!<br /><br />We can work on 3 : 5 : 8 frame predictions, Latency would be an issue! However by leveraging in what Quantum Computing calls : Undefined Future,<br /><br />We prodigy based on texture locations in reference frame (Pre finalised) & the Defined first wave (output frame)<br /><br />Frame reference Table for Predicted Interframe : { TV & GPU & Renderer }<br /><br />{<br /><br />Past Frame 3 }<br />Past Frame 2 }<br />Past Frame 1 } { Frame Series A }<br /><br />{<br /><br />Finalised previous frame with textures to clear,<br />Current to render Frame<br /><br />}<br /><br />Future frame series; Stable to probable : { 1 : 2 : 3 }<br /><br />(c)Rupert S<div><br /></div><div>******</div><br /><h4 style="text-align: left;">C.P.C : Combined Prefetch & Cache : Frame Delta Predict Optimisation : RS</h4><br />Prediction of frames between our stable frames makes a frame available that is based upon our knowledge of polygon & texture locations,<br /><br />We do not have to base the prediction of video frame (DSC Codec example) upon simply motion,<br />We can also predict upon past frames to smooth output video frame rate/FPS, <br />For we almost always record video from the preceding frame.<br /><br />We therefore can save 'Predict' for the video from our Past, Present & Future frames,<br />We create the Predict for the Frame & BFrame & Delta Frame with knowledge of future frames..<br /><br />We have Future frames because we preload the planned Polygon & texture paths of the GPU Compute Units & Prefetch with Cache..<br /><br />Combining both Prefetch (Cache) & Preframe generation optimisations & predictions.<br /><br />We combine C.P.C with texture, animation & polygon load & unload with Predict for Video/DSC/Codec<div><br /></div><div>We can also predict for frame based upon what we call textures & polygon's in a frame..</div><div>Because we regard the frames content as 3D or 2D saved into a frame or series of frames.<br /><br />(c)Rupert S<div><br /><div>******<div><br /><h4 style="text-align: left;">Frame generation By shape & motion made simple: RS</h4><br />A interframe with prediction (forward leaning) composes forward into the next frame...<br />B Frame (Quality prediction forward leaning) loaded wavelets to reuse<br /><br />Vectors saved to frame (shows likely motion & audio sync)<br />Prediction Vectors & Systematic Stored Motion Vectors<br /><br />This indicates which pixels will need to refresh and we can then start the data loading process & set refresh & leave a refresh pull to our display panel<br /><br />Easing the burdens of frame generation & refresh: Table<br /><br />(Audio & Video Sync properties & Prediction Vectors & Systematic Stored Motion Vectors)<br /><br />Properties : <br /><br />Predict motion, <br />Predict what moves (as in by colour & shape), <br />Predict 3D Motion in 2D with generalised reference material in 2D & 3D.<br /><br />Prediction Vectors & Systematic Stored Motion Vectors<br /><br />Colour properties:<br /><br />Same colour + Predict Vector<br />Different colour : From source colour + Vector<br /><br />Interframe generation (Requires 1 Frame latency, Save 2 frames & Predict 3rd),<br />Interframe generation latency reduction is to make frames faster (fps) initially & follow<br /><br />Save while processing 2 frames a vector prediction for 1:2:3 Interframes,<br /><br />Latency issues are covered by generating a faster initial frame rate for 3 seconds & following this though content.<br /><br />(c)Rupert S<br /><br />******</div><div><br /></div><div>Video Codec Reference : <a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><div><br /><a href="https://science.n-helix.com/2022/03/fsr-focal-length.html">https://science.n-helix.com/2022/03/fsr-focal-length.html</a><br /><a href="https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html">https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html</a><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><div><br /></div><div><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2022/08/simd.html">https://science.n-helix.com/2022/08/simd.html</a><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br />Reference source <a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a></div><div><br /></div><div>Easy Install Codecs: <a href="https://is.gd/DilyWinCodec">https://is.gd/DilyWinCodec</a><br /><br />Main interpolation references:<br /><br />Interpolation Reference doc RS <a href="https://drive.google.com/file/d/1dn0mdYIHsbMsBaqVRIfFkZXJ4xcW_MOA/view?usp=sharing">https://drive.google.com/file/d/1dn0mdYIHsbMsBaqVRIfFkZXJ4xcW_MOA/view?usp=sharing</a><br /><br />ICC & FRC <a href="https://drive.google.com/file/d/1vKZ5Vvuyaty5XiDQvc6LeSq6n1O3xsDl/view?usp=sharing">https://drive.google.com/file/d/1vKZ5Vvuyaty5XiDQvc6LeSq6n1O3xsDl/view?usp=sharing</a><br /><br />FRC Calibration ><br />FRC_FCPrP(tm):RS (Reference)<br /><a href="https://drive.google.com/file/d/1hEU6D2nv03r3O_C-ZKR_kv6NBxcg1ddR/view?usp=sharing">https://drive.google.com/file/d/1hEU6D2nv03r3O_C-ZKR_kv6NBxcg1ddR/view?usp=sharing</a><br /><br />FRC & AA & Super Sampling (Reference)<br /><a href="https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing">https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing</a><br /><br /><div>Audio 3D Calibration<br /><a href="https://drive.google.com/file/d/1-wz4VFZGP5Z-1lG0bEe1G2MRTXYIecNh/view?usp=sharing">https://drive.google.com/file/d/1-wz4VFZGP5Z-1lG0bEe1G2MRTXYIecNh/view?usp=sharing</a><br /><br />2: We use a reference pallet to get the best out of our LED; Such a reference pallet is:<br /><br />Rec709 Profile in effect : use today! https://is.gd/ColourGrading<br /><br />Rec709 <> Rec2020 ICC 4 Million Reference Colour Profile : <a href="https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing">https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing</a><br /><br />For Broadcasting, TV, Monitor & Camera https://is.gd/ICC_Rec2020_709<br /><br />ICC Colour Profiles for compatibility: <a href="https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing">https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing</a><br /><br /><a href="https://is.gd/BTSource">https://is.gd/BTSource</a><br /><br />Colour Profile Professionally<br /><br /><a href="https://displayhdr.org/guide/">https://displayhdr.org/guide/</a><br /><a href="https://www.microsoft.com/store/apps/9NN1GPN70NF3">https://www.microsoft.com/store/apps/9NN1GPN70NF3</a><br /><br />*Files*<br /><br />This one will suite Dedicated ARM Machine in body armour 'mental state' ARM Router & TV https://drive.google.com/file/d/102pycYOFpkD1Vqj_N910vennxxIzFh_f/view?usp=sharing<br /><br />Android & Linux ARM Processor configurations; routers & TV's upgrade files, Update & improve<br />https://drive.google.com/file/d/1JV7PaTPUmikzqgMIfNRXr4UkF2X9iZoq/<br /><br />Providence: https://www.virustotal.com/gui/file/0c999ccda99be1c9535ad72c38dc1947d014966e699d7a259c67f4df56ec4b92/<br /><br />https://www.virustotal.com/gui/file/ff97d7da6a89d39f7c6c3711e0271f282127c75174977439a33d44a03d4d6c8e/<br /><br />Python Deep Learning: configurations<br /><br />AndroLinuxML : <a href="https://drive.google.com/file/d/1N92h-nHnzO5Vfq1rcJhkF952aZ1PPZGB/view?usp=sharing">https://drive.google.com/file/d/1N92h-nHnzO5Vfq1rcJhkF952aZ1PPZGB/view?usp=sharing</a><br /><br />Linux : <a href="https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing">https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing</a><br /><br />Windows : <a href="https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing">https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing</a></div></div></div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-23531305415649796082022-10-19T16:56:00.136+02:002024-03-13T20:00:10.784+01:00Machine Learning Equates Solve Table for Advanced ML<h4 style="text-align: left;">Machine Learning Equates Solve Table for Advanced ML (c)RS</h4><div><br /></div>ML & Code Efficiency Heuristic Search, <br />Python & of course all runtimes of GPU & CPU Firmware & Logical thought, <br /><br />Apologies for not expressly stating all {Mul+ & all} Accumulator strategies, these are hard to work out! But basic edge detection is a SiMD Example RS<div><br /></div><div>*<br /><br /><h4 style="text-align: left;">Core Motivations of ML</h4><br />ML Learning is a branch of artificial intelligence that focuses on using data and algorithms to imitate the way that humans learn & improving ML Method accuracy. <br /><br />ML Learning can be applied to various domains, such as image processing, natural language processing, speech recognition & code optimization. <br /><br />ML Learning can use different techniques; Such as supervised learning, unsupervised learning & reinforcement learning, depending on the type and availability of data.<br /><br />Some of the common techniques used in ML Learning are:<br /><br />Edge detection: a process of identifying the boundaries of objects in images or videos.<br /><br />Accent recognition: a process of identifying the regional or social variation of speech.<br /><br />Language processing: a process of analyzing and generating natural language texts.<br /><br />Code optimization: a process of improving the performance or quality of code by using various methods, Such as compilers, libraries, or heuristics.<br /><br />The Objective is to improve both ML & Minds.<br /><br />RS<div><br /></div><div>I think that considering the stated philosophy, There is more room for education on social conduct.<br />https://www.youtube.com/watch?v=jV4lS0srEVo<div><br /></div>*</div><div><br /><h4 style="text-align: left;">Precision of operations has to be precisely managed:</h4><br />Most precisely we define a thought? <br />While we think precisely of naught,<br />some precision within thought!<br /><br />AVX for example can go upto 512Bit; But we can use 8Bit or 16Bit multiple operations,<br /><br />In the mind of the thinker we chose how we optimise our precision,<br /><br />Coding allows a person to think about how precise the decisions they make are!<br /><br />But precisely what we need in the way of precision is a remark on how difficult that choice is?<br /><br />When at school Pi often stops at 4r; Now in classical work we define absolute precision..<br /><br />But what are we capable of ?<br /><br />As we dream; the thoughts are imprecise; sometimes sharp!<br /><br />The true value of precision is quantified by the desired goal,<br /><br />What we do is achieve a goal in the range of our precision.<br /><br />Schooling is the same; precisely how precise we work for our goals & how we achieve them.<br /><br />RS</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">TOP's are not the only unit in Machine Learning; TOP's are the Objective Definition & Definition Inference of correctness.</h4><br />Role of FPU/SiMD/Vector Unit in TOP's<br /><br />The FPU float unit, Example Dual Pipe 128Bit Float unit PS5<br /><br />While not theoretically TOP's The Maths involved can solve many issues:<br /><br />Once TOP's have thought of:<br /><br />The role of Inferencing could depend on samples; Maths helps define samples,<br /><br />The FPU (Floating Point Unit) and SIMD (Single Instruction, Multiple Data) units are important components of machine learning accelerators.. <br /><br />Because they are responsible for performing the floating-point arithmetic that is required for many machine learning algorithms. <br /><br />The vector unit is also important because it allows machine learning accelerators to perform multiple operations on multiple data points in parallel, Which can significantly improve performance.<br /><br />The mathematics involved in machine learning can be used to solve a wide variety of problems, including:<br /><br />Defining samples: Machine learning models are often trained on data that is represented as samples. <br /><br />The mathematics of probability can be used to define the properties of these samples, <br />Such as their distribution and their size.<br /><br />Bonding atoms: Machine learning models can be used to predict the properties of molecules, <br />Such as their bonding energy and their stability. <br />Bonding atoms a Maths Solve can show bonding.<br /><br />The mathematics of quantum mechanics can be used to calculate these properties.<br /><br />Drawing graphics: Machine learning models can be used to generate realistic images and videos. <br />We can thread load, Polygons, Textures as wave tables, Audio & sounds such as drum kits.<br />We can draw a Ball in 128Bit, Draw a complex polygon; For example Random Shape Flier.<br />We can emulate a 128Bit Audio output.<br /><br />The mathematics of geometry and trigonometry can be used to represent these graphics.<br /><br />Emulating audio: Machine learning models can be used to synthesize sound and music. The mathematics of wavelets and Fourier transforms can be used to represent these sounds.<br /><br />RS</div><div><br />*<div><h4 style="text-align: left;">Int8:SiMD : Maths & Logic</h4><div>This is about how you think about components such as INT8, INT4(Xbox) & SiMD, You have to classify by necessity & optimise the structure.<br /><br />You can shape the game reality with specific control objects & statics!<br />Maths in SiMD & Int8 & Machine Learning in Int8 & SiMD; SiMD is hard maths, Int8 is soft edge inference...<div><br />Both are maths; But soft logic is not a PROOF Math but can be proof; Hard math is not 'Invention & Imagination 'Exactly''<br /><br />But we have both to improve performance.<br /><br />RS<br />*<div><br /></div><div>Solve Table of Statistically provable Machine Equates & Solves : Table of function competitors & Operators.</div><div><br /></div>"I know this is depressing from my end with a FX8320E with AVX but if you multi tune the CPU Kernel for the RX / RTX that 512DL AVX would have meaning, If you are kind you will allow machine learning on the AVX FX8320E Level to work on SiMD Yes / No comparisons !"<div><br /></div><div>#ML Learning: This explains why we teach kids art & reading first! But maths is quickly next, </div><div>Because all else is pointless; That we do not learn with logic & Teach with logic.</div><div><br /></div>Better-Mind <br />Here is how to create a better mind #ML <br />Train your eyes with art on the concepts of edges, curves, Colours & Shading and love,<br />Educate your minds; Learn today & be quite aware how clever & sharp you will be.<div><br /></div>Humain Operations<br /><br />Edge Detection<br />Such as teaching your child edge detect in art ;)<br /><br />Smooth & Blend & Sharpen,<br />All interpretive<br /><br />Accent Recognitions & Language<br /><br />Interpret as follows</div><div><br /></div><div>*<br /><h4 style="text-align: left;">Heuristic Code optimise</h4><br />When it comes to sorting methods, We Identify common techniques..<br />For example frequently used technologies such as:<br /><br />ResNet<br />Language<br />Audio & Visual information<br />Code<br /><br />Primarily we identify common optimisations; Compilers have libraries of them!<br /><br />Audio & Video Encoded data use Wavelet Images, We can ResNet Them & also Edge Detect & Gaussian Detect contrast, Colour, Shape<br /><br />Language is an uncommon syntax, But we have audio commons & Accent identification is also potentially Audio Context.<br /><br />Code context is Logic, Function, Utility, Design, Motive<br /><br />RS<div><br /></div>*</div><div><br /></div><div><h4 style="text-align: left;">M.A.P NPU Matrix Processor Dimensional construct (c)RS</h4><br />Primary reason for expansion of function data sets: 2D, 3D,< nD<br /><br />P.D.C is a worker thread parallel 2D or 3D Grid,<br />Utilising QQ & A, B,C Array maths allows us to collapse or expand dimensions in a flexible way,<br /><br />The same principles as SVM (S.V.M SiMD Vector matrix) can be used to culminate or expand dimensions...<br /><br />That way a M.A.P Processor can expand or collapse all mathematical constructs,<br />We can therefore use all mathematical & statistical arrays for machine Learning & Maths.<br /><br />RS</div><div><br /><div>*</div><div><br /></div><h4 style="text-align: left;">Adams is an example of dimensional flattening, But:</h4><br />Adams is an example of dimensional flattening; But we can use a statistical anomaly called Hallo Far Reach & list dimensions of a series,<br /><br />n layers By n layers : N² & Nn+<br /><br />8Bit : 8 layers By 8 layers:<br />2bit, 4Bit, 8Bit & So on<br />{ 2², 4², 8², 16², 32², 64²<N² }<br /><br />In reality we can use parallel layers in 4Bit to 128Bit relatively easily & advantage is Memory.. alignment,<br /><br />But also in Aligned memory arrangements we can also quantify ideally from<br />{ 2², 4², 8², 16², 32², 64²<N² }<br /><br />So we end up with all processor features used in a single stack; Examples!<br /><br />var Layers 8² = { 1 : {<br />4², 4²<br />4², 4²<br />},<br />2 : {<br />2², 2², 2², 2², <br />2², 2², 2², 2², <br />2², 2², 2², 2², <br />2², 2², 2², 2², <br />},<br />3 : {<br />32² : {<br />8²,8²,8²,8²,<br />8²,8²,8²,8²,<br />8²,8²,8²,8²,<br />8²,8²,8²,8²,<br />};<br /><br />Rupert S<div><br /></div>Example:<br /><br />Adam's Resnet-50 128bit / 8bit or 16bit<br /><br />Resnet-50 is an example of a network ML with an aligned 128bit = 8bit/16bit * (4 * 32) grid, suggested parameters ..<br /><br />Aligned making sense.<br /><br />RS</div><div><br /></div><div>An idea of alignment, Example Coral.ai EdgeTPU & Intel 8Bit 8*8:<br /><br />in an 8Bit restricted machine; 2 Blocks of 2² = 8, 2 Cube(3) = 8, 4² = 8 4 Cube(3) = 2*8 in 4 segments,<br />8² = 8*8 so parallel and ideal for the 8 lane intel function...<br />at the level of 8Bit only operations; 8*8 intel.<br />8*8 and 32Bit SiMD operations; 8²*2, 8² * 4²</div><div><br /></div><div>Inferencing 8Bit example : DOT : U32 8x4 : 32/4, U64 8x8 : 64/8,<br />Cache referencing: Block 4*U32, 2*U64, U128<br /><br />So an 8Bit access and labeling ID Hash; All in 8Bit...<br /><br />Has to group by preference into 8Bit groupings the resulting identifiers; We are going to assume U16 & U32 & U64 memory cells..<br /><br />We are going to write those cells per 8Bit block in Sync/ASync Till Full..<br />We are going to process grouped CELLS in SiMD & of groupîngs 8, 16, 32, 64 < 512Bit AVX/SiMD,</div><div><br />RS<div><br /></div><div>*</div><br /><h4 style="text-align: left;">SiMD Applications of basic maths operations in machine learning : RS</h4><br />Applications of operators to machine learning is like a PHP Database...<br />What we need to do is convert database accesses into actionable results...<br /><br />Google Bard & Bing/Cortana crawl the web; But too many results leave us inconclusive...<br /><br />We will be using database analysis on basic queries & for that we need heuristic maths!<br /><br />So what do we need ?<br /><br />Input data collection : Text & speech processing<br /><br />Sorting algorithms (Operators, Example Variable Sort : A*B =< C Sort)<br /><br />Graph Maths table collation : 3D Matrix Math - A B C Matrix<br />A C<br />|/<br />---B<br /><br />Analysis of various results & statistical analysis of motivated search & conclusion testing..<br />With these we can test many math examples such as edge detect & sharpening or result maths...<br /><br />With Operators ><br /><br />FMA AVX Performance table: 2Flops per Cycle per FMA Unit<br />Architecture Fast Instructions for FMA<br /><br />Reference Tables <a href="https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf">https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf</a><br /><br />Operators in C<br />● Arithmetic<br />a + b, a – b, a*b, a/b, a%b<br />● Bitwise <br />a | b, a & b, a ^ b, ~a<br />● Bit shift <br />a << b, a >> b (signed), a >> b (unsigned)<br />● Logical operators <br />a && b, a || b, !a<br />● Comparison operators<br />a == b, a != b, a < b, a <= b, a > b, a >= b<br />● Tertiary operator <br />x = a ? b : c<br />● Special functions:<br />sqrt(x), abs(x), fma(a,b,c), ceil(x), floor(x) <br /><br />For when {U, X, Y, Z} = N Expressions h<a href="ttps://is.gd/ForWhen_UXYZ_N">ttps://is.gd/ForWhen_UXYZ_N</a><br />For when {(A+B/2)} = C Expressions <a href="https://is.gd/ForWhen_ABx2_C">https://is.gd/ForWhen_ABx2_C </a><br /><br />Rupert S, <br /><br />Reference operators <a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />Matrix-Blas_Libs-Compile<br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a></div><div><br /></div><a href="https://en.wikipedia.org/wiki/FMA_instruction_set">https://en.wikipedia.org/wiki/FMA_instruction_set</a><br /><a href="https://en.wikipedia.org/wiki/Advanced_Vector_Extensions">https://en.wikipedia.org/wiki/Advanced_Vector_Extensions</a><br /><a href="https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE)">https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE)</a><div><br />*</div><div><div><br /></div><h4 style="text-align: left;">Number Complexity Reduction for operations</h4><br />I suppose you can use for example a - b & automatically see if it is larger? So you could 1 to 20 & sort them by remaining number; Before asking, Small number remainders are 8Bit 0-256 , 16Bit is 65535...<br />So reducing the value of a group of numbers you sort to 16Bit or 8Bit considerably reduces sorting cost...<br /><br />Achievable complexity reduction by abstracting a simple number to do the following:<br /><br />You link the Data in 64Bit, 32Bit to & Vector Table,<br />List of lower complexity is faster<br /><br />Sorting<br />Comparator matrix<br /><br />Colour composing,{<br />The result is blended, <br />The result is High/Low Vector gradient, <br />We need a reduced colour set for compression<br />}<br /><br />Where we sort files or names but reduced information (example First 4 Letters)<br />Sorting phone numbers fast...<br /><br />Comparing lower complexity lists that have been; divided or had a static number removed from them,<br />This method reduces search & sort complexity; Like so:<br /><br />Phone Number N +1 444555777<br /><br />Sort N [+n]<br />N - last 6 digits (Zero 6 Digits, AVX has this feature)<br />Sort [N1 to N200]<br />List first 4, Sort by 4 to groups of 10<br />N - First 6 Digits (Zero First 6)<br />Sort <br />Return N1 to N200<br />Store<br /><br />That may well be a lot quicker with very large lists.<br /><br />RS<br /><br />*<br /><h4 style="text-align: left;">AI</h4><br />Complex feeling based Machine Learning ML is known as AI..<br />To truly generate AI is not impossible; There is instability in the core; Fragmentations of motive...<br />Miss diagnosis; Error; Decay?<br /><br />So we do need a foundation; In us Education; Metabolised Data..<br />Analysis & then..<br />Application to motive & goal.<br /><br /><br />We require to understand humour,<br />We require to understand {Art, Science, Feeling, Life}<br />We require a goal or two; A {Sophie reward}; B {action reward}; C {Pleasurable reward}<br />We Require, {Goals, Life, Feeling, Action, Motive, Interest} : Creative intellect<br /><br />RS<br /><br />*</div><div><br /><h4 style="text-align: left;">Operation precision reductions : Effects General : RS</h4><br />Operation precision reductions affect & effect more than Machine Learning & yes we have known this for years!<br />But we can learn from ML; In that in machine learning like the mind; A lack of precision affects so many issues!<br /><br />The mind is self evidently the first place; <br />We lack logic when we do not precisely learn; We do not learn all...<br />We however learn quickly on reduced precisions... We Learn Fast; But do we learn well?<br />In school we teach as high a quality precision(Quality Education); As we can; But like machine RAM; We lack either time or memory & in truth we can learn all our lives..<br /><br />So our core issues in all methods of enactment of thought:<br /><br />Memory<br />Power<br /><br />Precision<br />Quality of information<br /><br />Retention<br />Relearning?<br />(Training)Requalification of information correctness<br />Thought process<br /><br />Actions<br />Creations<br />Thought<br />Dreams<br /><br />Reality & Truth<br /><br />Rupert S<br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br />*<h4 style="text-align: left;">+Useful operation precision reductions : RS</h4><div><br /></div>Useful operation precision reductions; I observe that reducing precision to 1Bit & 2Bit..<br /><br />While enhancing the definition of a positive, Negative Dipole & thus enhancing speed..<br />Further reduces reasoning capacity; That in order to reduce Processor bandwidth for reasoning..<br /><br />In the example of the XBox & PS5; DOT4 & INT4, INT8 & F16 & bF16; Apply considerable improvement to reductions probable error related to a lack of remainder or float value depth enhancement!<br /><br />By reason of probability i assume a value of 4Bit & 2Bit to allow the smallest packing ability; Existing alongside the word reasoned!<br /><br />To reduce to 1 & 0; I assume a definite statement that a Value Integer Solve in the form of a vector..<br />Is most probably the solution & that furthermore that in most cases; Projected in pure maths & code ASM,<br />Both SiMD; Float & Integer...<br /><br />Reduction to multiple 2 Bit values in short Integer instructions; I will state however that no such value is further away than a statistics table or PHP Data-Set.<br /><br />Rupert S 2023-06<br /><br />"The application of CNNs to resource-constrained embedded platforms has been a challenge, leading to the emergence of CNNs with various lightweight techniques. BNNs [22] are representative lightweight CNNs obtained by compressing CNN activation and weights into 1 and −1<br /> values instead of using single-precision floating-point data. We simplified the multiply–accumulate operation, which was previously complex and required multiple cycles in CLs, by replacing it with a simple bitwise operation using 1-bit XNOR and popcount operations [23]. While BN in neural networks using single-precision floating-point data involves complex operations, a BNN simplifies this process by adding an offset to the resulting value. BN has four fixed parameters for network inference operations. Because 𝜎<br /> is always a positive value, it can be expressed by Equations (2) and (3), depending on 𝛾<br /> [24].</div><div><br /><div class="html-p" style="background-color: white; box-sizing: border-box; color: #222222; font-family: Arial, Arial, Helvetica, sans-serif; font-size: 13.2px; margin-block: 1em; margin-inline: 0px; margin: 0px; max-height: 1e+06px; padding: 0px; text-align: justify; text-indent: 2em;"></div></div><div>Reference to Table 24 found in https://www.mdpi.com/1424-8220/23/12/5701</div><div><div class="html-p" style="background-color: white; box-sizing: border-box; color: #222222; font-family: Arial, Arial, Helvetica, sans-serif; font-size: 13.2px; margin-block: 1em; margin-inline: 0px; margin: 0px; max-height: 1e+06px; padding: 0px; text-align: justify; text-indent: 2em;"></div></div><div><br /></div><div><br />BNNs compress weights and input data into single bits to significantly reduce memory usage and perform hardware-optimized parallel operations using bitwise operations such as XNOR and popcount. However, there are limitations to using BNNs for complex networks, such as multi-keyword detection, owing to the decrease in accuracy caused by lightweight techniques. To address this issue, we propose a TNN that maintains the input data as binary while ternarizing the weights. The TNN has higher accuracy than the BNN owing to its higher bit precision; however, it can still use the bitwise operation method, and both networks have similar operational processes.<br />2.3. Depthwise Separable Convolutional Neural Network<br />In a typical CNN, multiple three-dimensional kernels repeatedly multiply and accumulate input feature maps to generate multiple output feature maps, which is computationally intensive with large memory usage. To solve this problem, we applied a DS-CNN that is highly accurate compared with the same parameters while reducing memory usage. A DS-CNN performs the local and global feature extraction functions of a typical convolutional operation in separate layers. Depthwise (DW) convolution matches a single input channel to an output channel, excluding interchannel correlations and reflecting local features. Pointwise (PW) convolution is equivalent to 1 × 1 convolution, reflecting interchannel correlations (i.e., global features). Figure 1 shows CNN and DS-CNN. In this figure, the use of the same color (e.g., red, blue, yellow) represents input channels with the same index being used to generate corresponding output channels in DW convolution. Table 1 lists the number of parameters and computations in specific layers with a 3 × 3 kernel. In one example from the network used in this paper, a layer with 128 input channels and 64 output channels experienced an approximately eight-fold reduction in the number of parameters and computational complexity using the DS-CNN."<br /><br />Useful operation precision reductions<br />FPGA Implementation of Keyword Spotting System Using Depth-wise Separable Binarized and Ternarized Neural Networks<br />https://www.mdpi.com/1424-8220/23/12/5701</div><div><br />*<br /><br /><h4 style="text-align: left;">Precision Context of learning</h4><br />Machine Learning : It is hard to say every function that we would use,<br /><br />However we have years of experience of using computers to calculate precise maths..<br /><br />So our objective from the past is to pick high precision maths to calculate graphs,<br />Now we can surmise the fact that high precision calculations have accuracy!<br /><br />But in machine learning modeling we are heading for speed; On the other hand Maths Tools such as:<br /><br />AVX & FPU : Very high precision; But we can use 16bit & 8Bit x many in AVX<br />BFloat F16b & F32b exist to allow us to explore precise results,<br />F4 F8, Int4 & Int8 exist to allow us to explore at speed & some times (at all :p),<br /><br />We can surmise that most functions of a CPU are in fact available to machine learning ..<br /><br />How so ?<br /><br />Because we graph it!<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">RAM ADDER differential Inference (c)RS : </h4>RAM Table Accumulated addition node network Accumulator with Accumulation comparison Inference<br /><br />*</div><div><h4 style="text-align: left;">Inferencing 4Bit, lessons from the RS, </h4></div>Inference Tessellation Edge Enhancing : Detection <> Inference <> Interpolation Tessellation<div><br /></div><div>Now in the case study we will be edge enhancing with an inferencer..<br /><br />We do not assume we 4Bit inference; We assume any bit-width..<br /><br />We however assume that we multibyte every inference so that we can fill the instruction with..<br /><br />MPi multibyte parallel instructions.<br /><br />AC<br />BD<br /><br />EG<br />FH<br /><br />& So on; for every instruction inference or edge, 4Bit, 8bit, ++Nbit<br /><br />Now I have spoken to you before about edge detection in Python & observed that obviously this is a sharpening edge detection made to order!<br /><br />So what do we do ?<br /><br />4 Byte code: does ? A = B + C (edge interpolation, for training we assume the rule A + B = C)<br /><br />We assume that if A + B = (C/2) , that they are the same C & then we...<br /><br />A + C = (D/2) & B+C = (E/2),<br /><br />And forever yep...<br /><br />So what do we do this for, We know A & B are a line or a curve?, So why not ask?<br /><br />Is G/Z buffered Polygon { A , B, C, D & so on} & Then:<br /><br />A + B = (C/2) & A + C = (D/2) & B+C = (E/2) But also Shape from Polygon:{ A , B, C, D & so on},<br /><br />Now normally can & will!<br /><br />But we do not "Inferencing what we already know!"; We inference what we do not!<br /><br />For example exploding fragment polygons without a buffer (in a shader in the 64KB RAM Cache),<br /><br />A mouse pointer that we do not cache! &or DMA Device pointer.<br /><br />Rupert S<br /><br />*</div><div><br /></div><h4 style="text-align: left;">Multi-line Packed-Bit Int SiMD Maths : Relevance HDR, WCG, ML Machine Learning (Most advantaged ADDER Maths)</h4></div><br />The rules of multiple Maths with lower Bit widths into SiMD 256Bit (example) 64Bit & 128Bit & 512Bit can be used<br /><br />In all methods you use packed bits per save, so single line save or load, Parallel, No ram thrashing.<br /><br />You cannot flow a 16Bit block into another segment (the next 16Bit block)</div><div><br /></div><div>You can however use 9 bit as a separator & rolling an addition to the next bit means a more accurate result!<br />in 32Bit you do 3 * 8bit & 1 * 4Bit, in this example the 4Bit op has 5 Bit results & The 8Bit have 9Bit results..<br />This is preferable!<br /><br />2Bit, 3Bit, 4Bit Operation 1 , 8Bit Operations 3: Table<br /><br />32Bit<br />4 : 1, 8 : 3<br /><br />64Bit<br />4 : 2, 8 : 6<br />2 : 1, 7 : 8<br />3 : 1, 8 : 1, 16 : 3</div><div><br />Addition is the only place where 16Bit * 4 = 64Bit works easily, but when you ADD or - you can only roll to the lowest boundary of each 16Bit segment & not into the higher or lower segment.<br /><br />A: In order to multiply you need adaptable rules to division & multiply<br />B: you need a dividable Maths unit with And OR & Not gates to segment the registered Mul SiMD Unit..<br /><br />In the case of + * you need to use single line rule addition (no over flow per pixel)..<br />& Either Many AND-OR / Not gate layer or Parallel 16Bit blocks..<br /><br />You can however painful as it is Multi Load & Zero remainder registers & &or X or Not remainder 00000 on higher depth instructions & so remain pure!<br /><br />8Bit blocks are a bit small and we use HDR & WCG, So mostly pointless!<br /><br />We can however 8Bit Write a patch of pallet & sub divide our colour pallet & Light Shadow Curves in anything over 8Bit depth colour,<br /><br />In the case of Intel 8Bit * 8 Inferencing unit : 16 Bit Colour in probably (WCG 8 * 8) + (HDR 8 * 8) Segments,<br /><br />In any case Addition is fortunately what we need! so with ADD we can use SiMD & Integer Today.<br /><br />Rupert S<br /><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2021/11/parallel-execution.html">https://science.n-helix.com/2021/11/parallel-execution.html</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><div><br /></div><div>*<br /><div><div><h4 style="text-align: left;">Main Operation solves: Bit-Depth Conversions & Operations</h4>Packed Bits, Multibyte Storage : u32, u64, u128</div><div><br />The storage of multiple bit operations with Sync Read & Write,<br />The purpose of this is to Read, Write & Store Operations on:<br /><br />DOT4<br />INT8, INT16<br />F16, F32, F64<br /><br />In RAM of 32Bit, 64Bit, 128Bit<br /><br />Values Storage Table<br /><br />32Bit = [16bit:16Bit]<br />32Bit = [8bit:8Bit:8bit:8Bit]<br />32Bit = [4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit]<br /><br />64Bit = [32bit:32Bit]<br />64Bit = [16bit:16Bit:16bit:16Bit]<br />64Bit = [8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit]<br />64Bit = [4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit]<br /><br />128Bit = [64bit:64Bit]<br />128Bit = [32bit:32Bit:32bit:32Bit]<br />128Bit = [16bit:16Bit:16bit:16Bit:16bit:16Bit:16bit:16Bit]<br />128Bit = [8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit:8bit:8Bit]<br />128Bit = [4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit:4bit:4Bit]</div><div><br /></div><div><br />Bear in mind that Integer 64Bit is 2 x 32Bit on AMD; So you can compute 2 operations at 32Bit per 64Bit operation,</div><div><br />Some 64Bit units are only 64Bit; So we need to know how many!<br /><br />32Bit operations are fine! & Conversion of 16Bit value ranges into 32Bit Operations can still be within range of 16Bit Storage..<br />If we stick within the 16Bit value range on Multiply & ADD,<br />We can therefore simply post a 16Bit value range data set & expect to be able to Store 16Bit!<br /><br />The simple method is to store 2 16Bit values in the same 32Bit table; like [16bit:16Bit] = 32Bit<br /><br />With this we can Load, Store, Run & Save 8bit INT8 operations in 32Bit devices such as Alexa as 8bit x 4 = 32Bit, So we don't Waste RAM or resources!<br /><br />But we still have access to 32Bit RAM Paging; But with values loaded in 4Bit, 8Bit, 16Bit, 32Bit & so on.</div><br />With NANO Android on F16 & F32 & MIPS the same & AMD, Intel, NVidia, <br />Learning F16 offers considerable value for performance with 16M Values!<div><br /></div><div>(c)RS</div><h4 style="text-align: left;">Direct DMA 32Bit & 64Bit RAM : Multiple Sync 16Bit Texture:</h4><br />A good example of where 8Bit & 16Bit Value load works well is in the case of the texture,<br />To load 4 x 16Bit into a single 64Bit Cache:<br /><br />32Bit RAM = 16Bit, 16Bit<br />64Bit RAM = 16Bit, 16Bit, 16Bit, 16Bit<br />128Bit RAM = 16Bit, 16Bit, 16Bit, 16Bit<br /><br />In the case of direct DMA, you would be aware that you have, <br />128Bit, 192Bit Buss on GPU<br />32Bit & 64Bit on CPU<br /><br />So a direct 4 * 32Bit or 2 * 64Bit Cache loads is a logically fast method to DMA directly from Cache to GPU!<br />In short you convert 8 x 16Bit into a 2x 64Bit DMA push; Which is very fast!<br /><br />You can do the same with batches of vertices in many storage sizes.<div><br /></div><div>(c)RS</div><div><br />References:<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br /><br />On the subject of how deep a personality of 4Bit, 8Bit, 16Bit is reference:<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />*</div><div><br /></div><div><h4 style="text-align: left;">Quantization modelling : RS : Physics III Slit Experiment</h4>Expanding on potentials for precise machine learning has the same qualities as Maths & quantified research,<br /><br />A fully qualified result is often required for deep thought & precise thought!,<br /><br />But we do not always have the RAM or resources that we require; When we need to prioritise load & data sets to specific RAM & Processor availability or location, or by necessity..<br /><br />Optimise our resource footprint & speed, while maintaining precision to our fully optimised values & data set needs & requirements.<br /><br />*</div><div><br /></div><div><h4 style="text-align: left;">Dynamic Scaling</h4><br />Ideas of FP8-F8 & FP16-F16 Interpolation to 32Bit & 64Bit, Gama Curves are usable(c)RS</div><div><br />Presenting the full precision neuron,; <br /><br />var Me = expand, {<br /><br />preload = dataset; {Ds1, Ds2, Dsn }, { condition = Present };<br /><br />var Present = { Datapoint set }; {<br /><br />var CC = Compose Compressed {Brotli-G > ZSTD };<br /><br />4Bit to N-Bit { Brotli-G(GPU Shader) Compressed Data Bit with Tri-Linear Interpolation & Extrapolation };<br /><br />var Pf = Processor contains N Features { F16, F32, F64, FPU } * { N, N2, N3, Nn };<br />var Ex = Expand Points { Series Precise { F16:<FPU }, Series Median { Int8:<Int64 }, Series Low priority { Int2:<Int32 };<br /><br />load Present;<br /><br />run ML, {epoch1 < epochNN };<br /><br />test results, {log : logNN};<br /><br />);<br /><br />*</div><div><br />"(SmoothQuant).The optimized model achieves >3X latency improvement with a custom dequantization kernel for FP16 inference. Although the work does not map to Int8 engine"<br /><br />In view that inferencing is being activated in Int4 & Int8 & Int16 & Floats f16b F8 & F4,<br /><br />Now my view is a vision of a Slit experiment in Physics; Now a slit experiment shows light photos in slices through a screen..<br /><br />Int4 IIII < Int8 IIIIIIII < Int16 IIIIIIIIIIIIIIII<br /><br />Ratio 1:2:4 on contained knowledge<br /><br />Minimal Origin of mankind's knowledge : IIII < IIIIIIII < IIIIIIIIIIIIIIII Defined Summit of all power<br /><br />My method is to compress the point node data with<br /><a href="https://is.gd/WaveletAutoEncoder">https://is.gd/WaveletAutoEncoder</a> </div><div><a href="https://github.com/GPUOpen-LibrariesAndSDKs/brotli_g_sdk">https://github.com/GPUOpen-LibrariesAndSDKs/brotli_g_sdk</a><br /><br />So what we do is take advantage of patterns; Creating tables of 1111 1010 as examples; These compress well & can be short noted as patterns,<br /><br />We can expand 4Bit into 8Bit inference & compress as patterns; The total data point is 4Bit if it is a pattern,<br />The subject is not predictable unless we pick the patterns!<br /><br />We can however Quantize the memory footprint; The Double/Single precision operations may be faster! :L<br /><br />We need the models to work in F16 & Int8 & Int4 after-all, But i see a reason to use Floats because sub-quantization does leave a remainder for us to compare..<br /><br />That relevant 'F16' >=-<br /><br />RS<br /><br />Study Subject Reduction :<br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://blog.openvino.ai/blog-posts/q123-technology-update-low-precision-and-model-optimization">https://blog.openvino.ai/blog-posts/q123-technology-update-low-precision-and-model-optimization</a><br /><a href="https://blog.openvino.ai/blog-posts/q223-technology-update-low-precision-and-model-optimization">https://blog.openvino.ai/blog-posts/q223-technology-update-low-precision-and-model-optimization</a><br /><a href="https://blog.openvino.ai/blog-posts/q323-technology-update-low-precision-and-model-optimization">https://blog.openvino.ai/blog-posts/q323-technology-update-low-precision-and-model-optimization</a><br /><a href="https://blog.openvino.ai/blog-posts/q423-technology-update-low-precision-and-model-optimization">https://blog.openvino.ai/blog-posts/q423-technology-update-low-precision-and-model-optimization</a><br /><br />Ideas of FP8-F8 & FP16-F16 Interpolation to 32Bit & 64Bit, Gama Curves are usable(c)RS - 'ocp' F8 & FP8 or smaller with interpolation-microscaling-formats-mx-v1-0-spec-final<br /><a href="https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf">https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf</a></div><div><br />Self Trained Auto Sparsity ML</div><div><br />Evolution-ML CNN Self Trained Auto Sparsity - Hybrid multi-objective evolutionary model compression with convolutional neural networks<br /><a href="https://www.sciencedirect.com/science/article/pii/S2590123024000045">https://www.sciencedirect.com/science/article/pii/S2590123024000045</a><br /><a href="https://blog.research.google/2023/12/advancements-in-machine-learning-for.html">https://blog.research.google/2023/12/advancements-in-machine-learning-for.html</a></div><div><br /></div>ML Batch Matrix MAP in FPGA<br /><a href="https://drive.google.com/file/d/1hdxeK1r8LIhvpn7poOm3MfXmGr9Tq-ni/view?usp=sharing">https://drive.google.com/file/d/1hdxeK1r8LIhvpn7poOm3MfXmGr9Tq-ni/view?usp=sharing</a><br /><br />ML Compressed Dynamic16bit-8Bit - Hardware-friendly compression and hardware acceleration for ML Transformer<br /><a href="https://aimspress.com/article/doi/10.3934/era.2022192">https://aimspress.com/article/doi/10.3934/era.2022192</a><br /><br />Matrix Processors - Memory & command - All-Digital Compute-In-Memory FPGA Architecture for Deep Learning Acceleration<br /><a href="https://dl.acm.org/doi/pdf/10.1145/3640469">https://dl.acm.org/doi/pdf/10.1145/3640469</a><br /><br />Matrix Processors - Inline Ram & Command { CMD : RAM }:{NET}<br /><a href="https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf">https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf</a><br /><a href="https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/EW2020-Deep-Learning-Inference-AICore.pdf">https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/EW2020-Deep-Learning-Inference-AICore.pdf</a></div><div><br /></div><div>learning Cards 52 upto 208 Tops $249+<br /><a href="https://hailo.ai/products/ai-accelerators/hailo-8-century-high-performance-pcie-card/#hailo8-features">https://hailo.ai/products/ai-accelerators/hailo-8-century-high-performance-pcie-card/#hailo8-features</a><br /><br />Comparative Streaming cards with ML & 70+ video Streams per unit<br /><br />130 channels of 1920x1080p<br /><a href="https://www.qualcomm.com/products/technology/processors/cloud-artificial-intelligence">https://www.qualcomm.com/products/technology/processors/cloud-artificial-intelligence</a><br />96 channels of 1920x1080p<br /><a href="https://www.xilinx.com/applications/data-center/v70.html">https://www.xilinx.com/applications/data-center/v70.html</a></div><div><br />TAC (Tiny Anomaly Compression)<br /><a href="https://pypi.org/project/Conect2ai/">https://pypi.org/project/Conect2ai/</a><br /><br />Inference on any device with a C99 compiler<br /><a href="https://pypi.org/project/emlearn/">https://pypi.org/project/emlearn/</a><br /><br />to run without activating C99; Installs under Python 3.10+<br /><a href="https://github.com/emlearn/emlearn-micropython">https://github.com/emlearn/emlearn-micropython</a><br /><a href="https://github.com/emlearn/emlearn-micropython/releases">https://github.com/emlearn/emlearn-micropython/releases</a><br />git clone https://github.com/emlearn/emlearn-micropython</div><div><br /></div><div>With EmLearn you can compile really tight models of tensors & random forest & Gaussian Matrix,<br />These are very good for: <br /><br />A1: Anti-Aliasing ( Gaussian, Tensor error diffusion, forested Random spread )<br />A2: sharpening & Shaping ( Tensor Edge detect with enhance, Gaussian estimation & line fill, Random forest A to B to D: E to B to F X + )<br />A3: Line & Curve estimation fills & Tessellation ( forested Random spread (Dither fills) & A1 & A2 & Differentiation in 3D Space : 1:2:3{ A B C : E B F }<br />A4: HDR & WCG, Combinations of dithering in colour space & light/Shadow differentiation in 3D Space : 1:2:3{ A B C : E B F }<br /><br />36Minutes UpscaleDL <a href="https://youtu.be/16jLi95mat8">https://youtu.be/16jLi95mat8</a><br /><br />Megatron Classifies Images in Web Tensors<br />A: <a href="https://drive.google.com/file/d/1EMMASCIu92hIgIxg0bEBrmAJuxvEfk2e/view?usp=drive_link">https://drive.google.com/file/d/1EMMASCIu92hIgIxg0bEBrmAJuxvEfk2e/view?usp=drive_link</a></div><div>B: <a href="https://drive.google.com/file/d/1A_P9GI6jztxw-K3xlPocGUzTSqti7_wX/view?usp=drive_link">https://drive.google.com/file/d/1A_P9GI6jztxw-K3xlPocGUzTSqti7_wX/view?usp=drive_link</a><br />C: <a href="https://drive.google.com/file/d/18jnPASrGo_pbubGmLuRiDVJYMDjPeD-c/view?usp=drive_link">https://drive.google.com/file/d/18jnPASrGo_pbubGmLuRiDVJYMDjPeD-c/view?usp=drive_link</a></div><div>D: <a href="https://drive.google.com/file/d/1Sfm9wUqihpC4gnhinuKD7SjlyrzFZc6B/view?usp=drive_link">https://drive.google.com/file/d/1Sfm9wUqihpC4gnhinuKD7SjlyrzFZc6B/view?usp=drive_link</a><br />E: <a href="https://drive.google.com/file/d/1wKfcBIKnHmHPbxcWB1Xp1gW3M7MvWlzy/view?usp=drive_link">https://drive.google.com/file/d/1wKfcBIKnHmHPbxcWB1Xp1gW3M7MvWlzy/view?usp=drive_link</a><br />F: <a href="https://drive.google.com/file/d/1R-4p-R6QMVwhCkUAdpUvhVK46t-h9_fw/view?usp=drive_link">https://drive.google.com/file/d/1R-4p-R6QMVwhCkUAdpUvhVK46t-h9_fw/view?usp=drive_link</a><br />G: <a href="https://drive.google.com/file/d/1hTTnczwKCiGUi3B4jkAG-TyfvY3hJJfs/view?usp=drive_link">https://drive.google.com/file/d/1hTTnczwKCiGUi3B4jkAG-TyfvY3hJJfs/view?usp=drive_link</a><br /><br /></div><div>11m 34m space then 11m;</div><div><a href="https://drive.google.com/file/d/1FZQnTNwqN2KPz0NUcELr63TdqEybnsn_/view?usp=drive_link">https://drive.google.com/file/d/1FZQnTNwqN2KPz0NUcELr63TdqEybnsn_/view?usp=drive_link</a><br />58m UpscaleDL </div><div><a href="https://drive.google.com/file/d/1vNQpvnKCTMicT8QztSeZAcLhSuWD_pjK/view?usp=drive_link">https://drive.google.com/file/d/1vNQpvnKCTMicT8QztSeZAcLhSuWD_pjK/view?usp=drive_link</a><br />36Minutes UpscaleDL <a href="https://drive.google.com/file/d/1zEJsz8_Us_nu2un5n5yE-F-q0gJpNi0z/view?usp=drive_link">https://drive.google.com/file/d/1zEJsz8_Us_nu2un5n5yE-F-q0gJpNi0z/view?usp=drive_link</a><br /><br />Count 58 - 18-49m Inference USB Accelerators - Megatron Web Tensor Classification 2024-02-02 17-12<br /><a href="https://drive.google.com/file/d/18hFa_fDMzVX8bbRyYUZh8JAByCN8fFaJ/view?usp=drive_link">https://drive.google.com/file/d/18hFa_fDMzVX8bbRyYUZh8JAByCN8fFaJ/view?usp=drive_link</a></div><div><br />Mr420Megatron Classifies Images in Web Tensors & you know he's good right, That is just what he feels! for real bro<br /><a href="https://drive.google.com/file/d/1UXlA-xpODvwGuUhCed0EBd6LJ0wB4J5E/view?usp=drive_link">https://drive.google.com/file/d/1UXlA-xpODvwGuUhCed0EBd6LJ0wB4J5E/view?usp=drive_link</a></div><div><br />Supercharge Web AI model testing: WebGPU, WebGL<br /><a href="https://developer.chrome.com/blog/supercharge-web-ai-testing?hl=en">https://developer.chrome.com/blog/supercharge-web-ai-testing?hl=en</a><br /><br /><a href="https://tensorflowjs-fashion-mnist-classifier.glitch.me/">https://tensorflowjs-fashion-mnist-classifier.glitch.me/</a></div><div><br /></div><a href="https://www.w3.org/2020/06/machine-learning-workshop/talks/access_purpose_built_ml_hardware_with_web_neural_network_api.html">https://www.w3.org/2020/06/machine-learning-workshop/talks/access_purpose_built_ml_hardware_with_web_neural_network_api.html</a></div><div><br /></div><div><a href="https://www.w3.org/TR/webnn/#intro">https://www.w3.org/TR/webnn/#intro</a></div><div><br /><a href="https://www.tensorflow.org/js">https://www.tensorflow.org/js</a></div><div><br /><a href="https://intel.github.io/webml-polyfill/examples/image_classification">https://intel.github.io/webml-polyfill/examples/image_classification</a><div><br /></div><div>Rupert S<div><br />Batch Size 240W>65W, 32GB{64, 16}, 15W>5W, 4gb{16, 1} : 16, 8, 4 seems optimal,<br />Time taken compatible:</div><div><br />ML_With_USB_Stress-Testing_USB_Accelerators_for_Efficient_Edge<br /><a href="https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference">https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference</a></div><div><a href="https://github.com/raphischer/edge-acc">https://github.com/raphischer/edge-acc</a></div><div><br /></div><div>Coral TPU Micro Edge Learning with performance arranged Intel FPGA Arria 10 SX SoC Kit & Google Coral, NVIDIA Jetson Nano and CPU ROCK 4C Plus<br /><a href="https://doi.org/10.3390/s24030899">https://doi.org/10.3390/s24030899</a></div><div><br /></div><div>ML Document Caches - USB Acceleration & Small devices - Combining Machine Learning and Edge Computing Opportunities Frameworks & Devices<br /><a href="https://www.mdpi.com/2079-9292/13/3/640">https://www.mdpi.com/2079-9292/13/3/640</a><div><br /></div><a href="https://is.gd/CJS_DictionarySort">https://is.gd/CJS_DictionarySort</a><br /><br />Python & JS Configurations<br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a></div><div><br /><div>*</div><div><br /></div>ML Tensor, ONNX Machine learning model that involves direct compression & higher accuracy in preference to Bit Reduction; Because reducing Bit Depth on decisions makes results potentially overflow your maximum ML Node Point Depth...<br /><br />Because of point overflow on low bit depth (less than 4Bit in most cases) We plan to use compression to multiply the RAM available to the ML..<br /><br />With Brotli-G the Zip can be directly decompressed inside the GPU & therefore the results are much faster & more efficient for us..<br /><br />We can further improve by selecting compression Compatable patterns such as 1111<1toN or 1010<10*N where N = Multiples of for example 1234 (repeating); R * N = RN,<br /><br />So we can maximise compression in Processor & not need to pass uncompressed data points,<br />We Cache & Decompress & Recompress as required.<br /><br />RS<br /><br />ML tensor + ONNX Learner libraries & files<br /><br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a><br /><a href="https://is.gd/UpscalerUSB_ROM">https://is.gd/UpscalerUSB_ROM</a><br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL</a><br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a><br /><br /><a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a></div><div><br />*</div><div><br /></div><div>Application of Data Compression to ML<br /><br />Some examples of how Brotli-G compression can be used to improve the performance of machine learning models:<br /><br />Compressing model parameters: Brotli-G can be used to compress the weights and biases of machine learning models, <br /><br />Brotli-G can reduce the amount of memory required to store the model; Which can be beneficial for deploying the model on devices with limited memory.. For example: <br /><br />Brotli G can be used to compress a model with 100 million parameters from 100MB to 50MB.<br /><br />Compressing model inputs and outputs: Brotli-G can also be used to compress the inputs and outputs of machine learning models; <br /><br />This can reduce the amount of data that needs to be transferred between the model and the data source or sink.. For example: <br /><br />Brotli-G can be used to compress images from 1MB to 500KB.<br /><br />Compressing model activations: Brotli-G can also be used to compress the activations of a machine learning model! <br /><br />Reducing the amount of memory required to store the intermediate results of the model.. For example: <br /><br />Brotli-G can be used to compress activations from 500MB to 250MB.<br /><br />In addition to these specific examples, Brotli-G can also be used to compress other types of data that are used in machine learning; text & data, <br /><br />Brotli-G is a high-performance compression algorithm that can provide significant performance improvements for machine learning applications.<br /><br />These examples demonstrate the potential of Brotli-G to improve the performance of machine learning models. As Brotli-G becomes more widely adopted, we can expect to see even more innovative uses of powerful compression algorithms.</div><div><br />RS<br /><br />*</div><div><h4 style="text-align: left;">Inferencing & Classification : Protocols</h4>To clarify that the inferencing unit such as Intel, AMD & ARM are expressly created with the opportunity to minimal instruction load; Edge detect & other machine learning comparators..<br /><br />As the Inferencing instructions contain the logic of comparison.. & furthermore are created to facilitate the comparison of Inference tasks..<br /><br />most logically you can see a wise person could see scope for edge detecting expressly with edge sharpening & shaping in mind; But also Trilinear filtering & of course Tessellation ..<br /><br />Now i believe you have Displays, Cameras & Audio Systems to optimise!<br /><br />Now we know that we can & also improve latency related issues such as frame tearing detection & also jitter & QFT & VRR.<br /><br />How ? Inference all of the latency issues of frame arrival time, torn frames & misaligned audio & Electric signal jitter in what is effectively an Ethernet protocol AKA Frame Transmission & Reception ...<br /><br />More ? Why not :L<br /><br />Rupert S<br /><br />*<h4 style="text-align: left;">Int8:SiMD : Maths & Logic</h4><br />This is about how you think about components such as INT8, INT4(Xbox) & SiMD, You have to classify by necessity & optimise the structure.<br /><br />You can shape the game reality with specific control objects & statics!<br />Maths in SiMD & Int8 & Machine Learning in Int8 & SiMD; SiMD is hard maths, Int8 is soft edge inference...<br /><br />Both are maths; But soft logic is not a PROOF Math but can be proof; Hard math is not 'Invention & Imagination 'Exactly''<br /><br />But we have both to improve performance.<br /><br />RS<br /><br />*<h4 style="text-align: left;">SiMD Performance : RS</h4><br />Performance per WATT of MMX & MMX+ & SSE & AVX Machine Learning & Shader code; Is a matter of 8x8Bit & 16x16Bit Code on GPU<br /><br />Our role is to reduce complex un-cache-able ML to Cache Enabled 64KB<br />Modelling of 1990's without Quality loss of 32Bit++ 64Bit+<br /><br />8x8Bit sharpening MMX Becomes Dual Pipe (16x16bit)*2 in 32Bit Dual 16 Pipeline & Twice as sharp<br />Machine Learning method for MMX Is Fast & Cheap, MMX2 More Compatible,<br />Intrinsic improvements such as combined ops & DOT4 Further improve the performance of under 1MB Code..<br /><br />Performance & Function per WATT, Is unbeaten; Let us prove it!</div><div><br /></div><div>For example Quake has MMX Emulation & MMX Dithering code on 3D Textures, <br />In 8Bit 256 Colours dithering is noticeable; In 15Bit to 32Bit the small shade difference in dithering colour is subtle & flawless, <br />Improving light subtilty & Colour pallet WCG & HDR 10Bit to 16Bit per channel.</div><div>*</div><br /><h4 style="text-align: left;">SiMD & Int8 & dp4a & F16/F32/F64>:</h4><br />The way SiMD Repeating Parallel batches of instruction can still side load data,<br />Data is loaded into the 'calculation set'<br /><br />http://ftp.cvut.cz/kernel/people/geoff/cell/ps3-linux-docs/CellProgrammingTutorial/BasicsOfSIMDProgramming.html<br />https://en.wikipedia.org/wiki/Single_instruction,_multiple_data<br /><br />SiMD Consist of 8Bit to 64Bit Long & Floats,<br />SiMD are simple instructions; Or so they think; SiMD are relatively complex instructions..<br />For example 4/1 of a page full of arithmetic code; However our goal is to use Heuristics & logic to circumvent the Artifacts/Errors in self generated code,<br /><br />In addition to using problem solving tables to choose instructions that advantage our analysis (Machine Learning),<br />We also can choose the most probably optimal code type.<br /><br />Our outset objective is to decide if we want to use CPU Feature types:<br /><br />F16<br />Int8<br />dp4a<br />SiMD<br /><br />Depending on the Mathematical Qualities of each ML Node & the questions they are asking,<br />For examples:<br /><br />A simple ResNet Image identification uses edge detect & for that we need for example SiMD Matrix Edge Detection<br /><br />Speech requires identifying Words in a codec, So obviously we need a Decoder & Encoder,<br />Word identifiers & correctness checking; But firstly we need to identify accent to correctly choose words..<br /><br />We also need to classify words by Idea grouping (DataBase, Open Database)<br /><br />As you can see; We will be defining many of these function groups as SiMD & Float,<br />Effective use of Int8 differentiation, Comparators & Maths operations has many benefits; So does JIT Compile.</div><div><br /></div><div>RS</div><div><br />*<div><h4 style="text-align: left;">Solve Table of Statistically provable Machine Equates & Solves : Table of function competitors & Operators.</h4><br />Runtime Library - Multiple Solve Table<br /><br />I would like a Solve Table of Statistically provable Machine Equates & Solves that make the equivalent of Maths Compilers such as RUST & Fortran's<br /><br />For example basic ML code test function loops are basically compatible with X-OR Comparators on AVX! Other functions such as greater or less than; Are AVX Compatible.<br /><br />Machine Learning : List of actions that are SiMD Baseline: Statistical Observance and Solve Tables<br /><br />Yes or no comparator X-OR<br />Memory array Byte Swap<br />Greater or less than with swap or with X-OR Roll<br />Memory save & store<br />Edge comparisons<br />Compares (Colour, Math, Equate, Target, Solve if)<br /><br />There are more! Statistical Observance and Solve Tables.<br /><br />Examples 2:<br /><br />Shape compare is a matter of inner & outer Vector : Comparison & X-OR, Larger outside & X-OR The differentiation: <br />By Dot, <br />By Mass (non literal dot difference comparator by axis), <br />Actual Mass<br />Density : Lumina, Weight, Mole, Mass / Area<br /><br />Edge Solve : X-OR ~= Colour, Lumina, Shade, Vibrancy, Distance, Matrix Solve 3D>=2D Flattened Comparator<br />If = X-OR=N<0.0001 Then Compare &= Mutex Solve / Average<br /><br />Polygon Join/Merge Tessellation : If Model = Same (T1 + T2 If (T1 + T2)/2 = Difference Less Than 0.0001 | = Merge/Converge<br /><br />*</div><br /><h4 style="text-align: left;">Audio, Video & High precision Float ML</h4><br />tensors & full onnx configuration : Upscaling : While we are not sure how much ML we need & at what precision,<br /><br />We can be sure that 32Bit (per channel) Value RGBA (Multiple layer) requires at least 8Bit to 16Bit per channel final precision; So here is a list:<br /><br />Required Value of output, Neural Network precision guide table: RS<br /><br />Input<br />8Bit, 10Bit, 12Bit, 16Bit<br /><br />Input network precision average bit retention (for RAM some error is allowed)<br />6Bit, 8Bit, 10Bit, 14Bit, 16Bit<br /><br />Classifiers as we know can be, <br />Int 2Bit 4Bit, 8Bit, 16Bit, 32Bit<br />2 Bit is unlikely & 32Bit is for Dream Smooth 16Bit+ Precision output</div><div><br />Output Float (Mostly FP & F16b)<br />16Bit = { 8Bit, 10Bit, 12Bit }<br />24Bit, 32Bit, 64Bit = { 16Bit, 32Bit, 48Bit }<br />We can upscale : Audio, Video, Content & Polygons, We classify Quality by expectations & Quantify by percent %<br /><br />Rupert S<br /><br />*</div><div><br /></div><div><h4 style="text-align: left;">8Bit vs 16Bit vs 32Bit</h4><br />Stitching wounds is an example for use to compare inferencing bit depth:<br />An 8Bit reference photo constitutes approximately 1cm² Black & White / Grayscale 300ppi, maybe 1/2cm² Colour 8Bit 150PPI,<br /><br />16Bit reference constitutes approximately 6cm² grey scale 600ppi, 3cm² Colour 15Bit 300ppi.<br /><br />32Bit single precision still has more to examine.<br /><br />Both 8Bit & 16Bit Inference offer a solution.<br /><br />(c)Rupert S<br /><br />Bit Depth and Colour Representation:<br /><br />A bit is a fundamental unit of information in computing, representing either a 0 or a 1.<br /><br />Bit depth refers to the number of bits used to represent a colour value for a single pixel in an image.<br /><br />Higher bit depth translates to more possible colours or shades of grey.<br /><br />An 8-bit image can represent 2 raised to the power of 8 (2⁸) which is 256 colour values, <br />This is often enough for basic images and applies well to grayscale images with high precision (300ppi in example).<br /><br />A 16-bit image can represent 2¹⁶ (65,536) colour values, offering a significant increase in colour detail, <br />This can be beneficial for colour reference photos (like the 300ppi colour example).<br /><br />Bit Depth and Image Quality in Stitching<br /><br />In the context of stitching wounds together, accurate colour representation and detail are crucial.<br /><br />An 8-bit grayscale image at 300ppi might provide enough detail for basic analysis, <br />But a 16-bit image (or even higher) would likely be preferable for capturing subtle variations in skin tone and tissue.<br /><br />The provided information suggests that 16-bit color images might offer a good balance between detail and file size for this application (around 3cm² at 300ppi).<br />32-bit and Beyond<br /><br />While 32-bit images offer an even greater range of colors, they might not be necessary for tasks like wound stitching, and would likely come with increased file size and processing demands..<br /><br />Important Considerations<br /><br />The suitability of a bit depth depends on the specific application.<br /><br />File size also plays a role - higher bit depth images require more storage space.<br /><br />Processing power required to manipulate the image can also be affected by bit depth.<br /><br />*</div><div><br /></div><h4 style="text-align: left;">TPU is discovering a new market in L1 Server class NPU Share; Minimal footprint NPU Class EdgeTPU has the edge you can't match..<br />Edge Server class mPCIe M.2 NPU learning.</h4><div><br />Remember that without Jenny, his dream of identifying cells wouldn't have come today, Jenny inspired the Resnet 50m photos to cure cancer story with her great energy; Resnet-50 Cell identification program<br /><br />You may be wondering but as a doctor you may already know that they have a 3D XRay to destroy cancers, <br />But you might not know how Resnet50 could isolate & destroy cancer cell clusters in a 3D XRay/Image/MRI scan,<br /><br />cloudflare.com Resnet-50 Service It takes 50m images identified to cut all polyp cancer cells from a victim,<br />Coral edge TPU and Movidius are the economy answers for cloudflare and MSF.fr <br /><br />@cf/microsoft/resnet-50 50 layers deep-image classification CNN trained on more than 1M images from ImageNet<br /><br />Worthy configurations for consoles such as dentists computers : <br />Cancer & searches for tissues such as FATS in the veins of the heart,<br /><br />Fats in veins constitute an average width of healthy vein being a measurable statistical normal,<br />The fat amounts stuck to the vein constitutes an abnormal or statistical deviation..<br />Many of these measurements need official verification & should be signed as verified.<br /><br />Heart pulse rate versus body size & arrhythmic or statistical variances beyond normal; That are not seen as healthy (if you verify knowledge).<br /><br />There are many small tasks that the body does that are equivalent to vehicle verification & health checks..<br /><br />The results of the statistical normal & small task..<br />The task that has many points of interest & thus takes hours for people to verify,<br />Computers do these tasks better & quicker.<br /><br /><h4 style="text-align: left;">ApplicationSensiMelia (c)RS</h4><br />I estimate a tip of 15cents per client per hour would make the application work,<br /> <br />In the case of diabetics & other statistical anomalies like heart rate,<br />The App that works is a combination of Lamba LLM & statistics & average deviations in 8Bit inferencing,<br /><br />Perfect for EdgeTPU.<br /><br />(c)Rupert S<br /><br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS </a><br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL </a><br /><a href="https://developers.cloudflare.com/workers-ai/models/image-classification/">https://developers.cloudflare.com/workers-ai/models/image-classification/</a></div><div><br /></div><div>Cancer Research References</div><div>Reference: <a href="https://drive.google.com/file/d/1WmhMcCZZjDI4pKnQsccvaf4RdquhPPs8/">https://drive.google.com/file/d/1WmhMcCZZjDI4pKnQsccvaf4RdquhPPs8/</a><br />Reference française: <a href="https://drive.google.com/file/d/1WiFUEOE23D4UTQRN7MP6Z4Lh24PJxuFG/">https://drive.google.com/file/d/1WiFUEOE23D4UTQRN7MP6Z4Lh24PJxuFG/</a></div><div><br /></div><a href="https://www.google.com/search?q=resnet+50+for+cancer+screening&hl=en">https://www.google.com/search?q=resnet+50+for+cancer+screening&hl=en</a><br /><br />Skin cancer<br /><a href="https://github.com/ngandhi369/Skin-Cancer-detection-using-ResNet-50">https://github.com/ngandhi369/Skin-Cancer-detection-using-ResNet-50</a><br /><br />Prostate Cancer<br /><a href="https://bmcmedinformdecismak.biomedcentral.com/articles/10.1186/s12911-024-02419-0">https://bmcmedinformdecismak.biomedcentral.com/articles/10.1186/s12911-024-02419-0</a><br /><br />Breast Cancer<br /><a href="https://pubmed.ncbi.nlm.nih.gov/36631349/">https://pubmed.ncbi.nlm.nih.gov/36631349/</a><br /><a href="https://arxiv.org/html/2308.13150v6">https://arxiv.org/html/2308.13150v6</a></div><div><br /></div><div>Deep learning radiomics based prediction of axillary lymph node metastasis in breast cancer<br /><a href="https://www.nature.com/articles/s41523-024-00628-4">https://www.nature.com/articles/s41523-024-00628-4</a><br /><br />Improving image classification of gastrointestinal endoscopy using curriculum self-supervised learning<br /><a href="https://www.nature.com/articles/s41598-024-53955-8">https://www.nature.com/articles/s41598-024-53955-8</a></div><div><br />Cervical cancer<br />Prediction of lymph node metastasis in operable cervical cancer using clinical parameters and deep learning with MRI data: a multicentre study<br /><a href="https://insightsimaging.springeropen.com/articles/10.1186/s13244-024-01618-7">https://insightsimaging.springeropen.com/articles/10.1186/s13244-024-01618-7</a><br /><br />$DeepCPD: deep learning with vision transformer for colorectal polyp detection<br /><a href="https://link.springer.com/article/10.1007/s11042-024-18607-z">https://link.springer.com/article/10.1007/s11042-024-18607-z</a><br /><br />A Combined Ensemble Model (CEM) for a Liver Cancer Detection System<br /><a href="https://thesai.org/Publications/ViewPaper?Volume=15&Issue=2&Code=IJACSA&SerialNo=18">https://thesai.org/Publications/ViewPaper?Volume=15&Issue=2&Code=IJACSA&SerialNo=18</a><br /><br />MRI ML Enhancement<br />Deep-learning-based reconstruction of under-sampled MRI to reduce scan times, a multicentre retrospective cohort study<br /><a href="https://www.thelancet.com/journals/lanonc/article/PIIS1470-2045(23)00641-1/fulltext">https://www.thelancet.com/journals/lanonc/article/PIIS1470-2045(23)00641-1/fulltext</a><br /><br />PulmoNet: a novel deep learning based pulmonary diseases detection model<br /><a href="https://bmcmedimaging.biomedcentral.com/articles/10.1186/s12880-024-01227-2">https://bmcmedimaging.biomedcentral.com/articles/10.1186/s12880-024-01227-2</a></div><div><br /></div><div>An efficient image classification of lung nodule classification approach using CT and PET fused images<br /><a href="https://drive.google.com/file/d/1irjQF-rvLtfvdzHTBB7tSuJCGLO40OxD/view?usp=drive_link">https://drive.google.com/file/d/1irjQF-rvLtfvdzHTBB7tSuJCGLO40OxD/view?usp=drive_link</a></div><div><br />Salivary gland tumours<br />Deep learning based ultrasound analysis facilitates precise distinction between parotid pleomorphic adenoma and Warthin tumour<br /><a href="https://www.frontiersin.org/journals/oncology/articles/10.3389/fonc.2024.1337631/full">https://www.frontiersin.org/journals/oncology/articles/10.3389/fonc.2024.1337631/full</a><br /><br />Rapid and Label-Free Histopathology of Oral Lesions Using Deep Learning Applied to Optical and Infrared Spectroscopic Imaging Data<br /><a href="https://www.mdpi.com/2075-4426/14/3/304">https://www.mdpi.com/2075-4426/14/3/304</a></div><div><br />Brain Cancer<br />A multi-class brain tumour grading system based on histopathological images using a hybrid YOLO and RESNET networks<br /><a href="https://www.nature.com/articles/s41598-024-54864-6">https://www.nature.com/articles/s41598-024-54864-6</a><br /><br />Deep-learning quantified cell-type-specific nuclear morphology predicts genomic instability and prognosis in multiple cancer types<br /><a href="https://www.biorxiv.org/content/biorxiv/early/2024/03/12/2023.05.15.539600.full.pdf">https://www.biorxiv.org/content/biorxiv/early/2024/03/12/2023.05.15.539600.full.pdf</a><br /><br />Multiple path trained cancer & diagnostics study with full networks and specifically tuned: Progress : :D<br /><a href="https://blog.research.google/2024/03/health-specific-embedding-tools-for.html">https://blog.research.google/2024/03/health-specific-embedding-tools-for.html</a><br /><br />Medical Data for ML Processes:<br />The data that support the findings of this study are openly available on Kaggle: <a href="https://www.kaggle.com/">https://www.kaggle.com/</a><br /><br />*<br />Treatment<br /><br />Machine Learning Processed 3D Fully Masked Identified Groups : MLp-MaskedIG screen & clense:<br /><br />Dealing with Resnet Identify Masking & Precise Ion control in 3D Fully Masked Identified Groups <br /><a href="https://home.cern/news/news/knowledge-sharing/cern-detector-could-help-improve-head-tumour-radiotherapy">https://home.cern/news/news/knowledge-sharing/cern-detector-could-help-improve-head-tumour-radiotherapy</a><br /><a href="https://home.cern/news/news/knowledge-sharing/biodynamo-cutting-edge-software-helps-battle-cancer">https://home.cern/news/news/knowledge-sharing/biodynamo-cutting-edge-software-helps-battle-cancer</a><br /><br />Observing that directed energy reduces radio exposure & sickness; works with surgeries also & is human processed or robotic.<br /><br />RS<br />*<br /><br />Incident observations , download entitlement <a href="https://drive.google.com/file/d/1GOZR4kZmH1s4vqqoNZ0C8Pnc0BwenkRo/">https://drive.google.com/file/d/1GOZR4kZmH1s4vqqoNZ0C8Pnc0BwenkRo/</a><div><br /></div><div>Extra layer reference : <a href="https://coral.ai/docs/edgetpu/inference/">https://coral.ai/docs/edgetpu/inference/</a><br /><br />Retraining the last layer or Repointing a network;<br />In terms of ourselves this constitutes Retraining our degree along specialisation tasks,<br />That is the method RS<br /><br />We need to clip the last layer or re profile the vision application if we wish to add networks like cancer or germs to a pre trained model,<br /><br />According to them we repoint nodes or we clip inferencing layer & re train the network before inferencing..<br />Exact referencing is complex; But we need to retrain or repoint gan's and inferencing networks..<br /><br />Pre trained networks that are not specific to our task cannot add nodes for tasks without re imprinting the network optimally or shaving off the last layer to further our identify tasks.<br /><br />Rupert S<br /><br />Reference: https://drive.google.com/file/d/1WmhMcCZZjDI4pKnQsccvaf4RdquhPPs8/<br />Reference française: https://drive.google.com/file/d/1WiFUEOE23D4UTQRN7MP6Z4Lh24PJxuFG/<br /><br />PCIe Acceleration modelling for Medical grade 3rd World #FirstClass : Question is, are you McGuiver? I Am ;D #DoctorLove<br /><br />Your standard medical console may be using most probably Standard Python acceleration (older version), <br />Most likely a cancer screening could shave 30 seconds from your diagnostic timeline..<br /><br />If you have one of the following available:<br /><br />hailo 8, PCIe, M.2, M.2 in a PCIe Card such as a compatible Wifi M.2 E-key or AE Key...<br /><br />Question is, are you mcGuiver? I Am ;D<br /><br />Hailo3/5 with phiza & the like who 'donated it'<br /><br />CORALS on sale 4TOPS, 8TOPS, Your choice, What you need for HPC 09:33 06/03/2024 : RS<br /><br />https://science.n-helix.com/2022/10/ml.html<br /><br />ML tensor + ONNX Learner libraries & files<br />Model examples in models folder<br /><br />https://is.gd/DictionarySortJS<br />https://is.gd/UpscaleWinDL<br />https://is.gd/HPC_HIP_CUDA<br /><br />https://is.gd/UpscalerUSB_ROM<br /><br />https://is.gd/OpenStreamingCodecs<br /><br />The perfect Proposal RS<br /><br />*<br /><h4 style="text-align: left;">FPGA BitFile & Code Opt (c)RS 2021-01 </h4></div><div><br /></div>https://science.n-helix.com/2022/10/ml.html <br />https://science.n-helix.com/2022/08/jit-dongle.html <br />https://is.gd/LEDSource<br /><br />In my view heuristics in compilers are a choice for those who do not wish to include direct ML compiled into their code,<br />This is understandable in terms of terminator & cylons & indeed flawed beings or even good ones with depression!<br /><br />However the application of branch optimisation is a sample code optimisation that can 'Plug In' to branch caching on the CPU & GPU.<br /><br />Heuristics are not just code in the compiler; They are also micro code selecting a probable branch; Although code that forces a branch can be flawed..<br /><br />Both heuristics, Branch probability selection & ML can run in parts of the code to select probable path!<br /><br />Yes fundamentally any code that modifies behaviour is a catch bullet frame for not sound 'Fortrans code is rock solid' Rust is also supposed to be solid.<br /><br />Including soundly made heuristic code & branch probability code ML in your inline routines; 'Very much interpretive master jedi'; But it can be done!<br /><br />Question is How big? & how fixed?<br /><br />25KB per 3MB on average?<br /><br />ML & Heuristics like my application FPGA BitFile & Code Opt (c)RS 2021-01<br /><br />can be applied at runtime & remain only for selecting the fastest path or the best; In terms of which Processor function to run code for.<br /><br />(c)Rupert S<div><br />*</div><br /><h4 style="text-align: left;">TOPCloud Scaled Flexible WebASM & WebGPU & MathML!</h4><br />Quite flexible for use on Monitors & TV's; Light processor load on simple tasks & offloadable such as TOPCloud!<br /><br />You may be thinking Offloading is impracticable because that requires one of two things:<br /><br />JIT Compiler Dongle..<br />USB device such as Firestick or GPU & CPU (With OpenCL Compat)<br /><br />Server! so internet & service provision!<br />Impossible? No; WebAdvert supported TV's need both!<br />So why not HPC TOPCloud? could make a HOT TV a lot cooler & Eco friendly with Server repeating tasks:<br /><br />Scaling<br />Quality Service<br />Service availability<br /><br />TOPCloud Offload Logic:<br /><br />In terms of WebASM & WebGPU & MathML; TOPCloud provides sufficient advantages to be considered a core utility..<br /><br />While Offloading repeating content such as Siteload core stack (Server) & Localising configuration such as Webpage size & DPI & Dynamic font arrangements that require thought.<br /><br />In terms of Offloaded function & Efficient system load for large configurations..<br /><br />Especially efficient configurations such as TPU, Coral, GPU work & Cloud CPU that have large optimised stacks & installed drivers.<br /><br />RS</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">#Sound Strategy game TOPCloud (c)RS</h4><br />PCM & MP4 are 2D/3D Image so GPU Helps there also with 3D Audio mapping!<br />Games do not require cloud processing of images & a lot of local strategies are procedural Heuristic<br /><br />You see RDP has GPU Connect (my innovation i might add) So Bluetooth & Wifi can connect RTP GPU; The port specifics are not particularly important; However a device such as music streamer can have ML TOP's available locally & from the cloud, <br /><br />Due to how the TOPCloud strategy works with localised ML TOPS; Not all data has to be sent or received.. For example all Audio 3D Profiles for HQ Room audio can be done within a few MB of data; With some hard work? 150Kb of data & so in reach of phones & mobile! <br /><br />Gaming is an example here. I give TickTackToe as the example where all that a device like Alexa or Google smart device has to think is Which square? but..<br /><br />No physical picture needs to be sent for the game to be played & if required a small TickTack Strategy ML is desired locally for a quicker response!<br /><br />You see with a low latency GPU RTP & GPU RDP connection to cloud GPU; Most localised thinking TOPS can be carried out in Seconds if not milliseconds & PCM & MP4 are 2D/3D Image so GPU Helps there also with 3D Audio mapping!<br /><br />Rupert S<br /><br />*</div><div><br />Core features of TOPCloud:<br /><br />RTP ML TOPS are a processors friend<br /><br />3D audio mapping & spatialization for realistic sound effects<br />3D Vector Support for various audio formats such as PCM, MP4, OGG, and WAV<br /><br />Low latency & high bandwidth connection to cloud GPU servers via RDP<br /><br />Procedural & heuristic algorithms for generating game scenarios & strategies & 3D Audio & Visuals<br />Localized & cloud-based machine learning models for optimizing game performance & user experience<br /><br />RTP GPU Connect technology that allows users to access GPU resources from any device with Bluetooth or WiFi<br /><br />TOPCloud is a revolutionary 'TOPS' way to enjoy & create audio games using your own music & the power of the cloud. Try it today & discover a new dimension of gaming!<br /><br />*<div><br /></div><div><h4 style="text-align: left;">Scaling; We can classify by colour or creativity. (c)RS</h4><br />If you use TOPCloud, you can share between different displays in the TOP's Sense..<br />but mostly you would need cloud presence,<br /><br />Mostly this would be about making the most out of TOP heavy Business GPU & personal ones in your computer or consoles.<br /><br />But sharing common tasks such as scaling movies by type or by identifying a single movie to upscale...<br /><br />Now you might be asking what we would be doing there?<br />Well a single movie uses the same materials in our ML; We can analyse the class & optimise the scaling by class..<br /><br />For those familiar with games & FSR; We familiarise our code with a single game!<br />By doing this we improve our product and can therefore classify by:<br /><br />Resolution<br />Style<br />Speed<br />Type, FPS for example & RTS<br /><br />We can classify by colour or creativity...<br /><br />We do not simply have to roll the dice on General Scaling, We can use classifiers:<br /><br />Title<br />Scale<br />Type<br />Speed<br />Frame Rate<br />Colour & Composure<br /><br />Rupert S</div><div><br />PoCL Source & Code<br />https://is.gd/LEDSource<br /><br />*<div><div><div><br />We all think our own way; Potential is always there on a Runtime Library - Multiple Solve Table<br /><br />Machine learning | Equate ~= Multi Layer Wavelet Abstraction<br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://www.youtube.com/watch?v=-9lCpfrOQQ4<br /><br />(c)Rupert S 2022-10<br /><br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br />https://is.gd/BTSource<br /><br /><a href="https://science.n-helix.com/2023/06/tops.html">https://science.n-helix.com/2023/06/tops.html</a><br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://is.gd/MLCodecShaping">https://is.gd/MLCodecShaping</a></div><div>*<br /><br />This one will suite Dedicated ARM Machine in body armour 'mental state' ARM Router & TV <br />(ARM Learning 4K ROM; Safe Larger USB ROM) https://bit.ly/3Afn1Y4<br /><br />https://drive.google.com/file/d/102pycYOFpkD1Vqj_N910vennxxIzFh_f/view?usp=sharing<br /><br />Android & Linux ARM Processor configurations; routers & TV's upgrade files, Update & improve<br />https://drive.google.com/file/d/1JV7PaTPUmikzqgMIfNRXr4UkF2X9iZoq/<br /><br />Providence: https://www.virustotal.com/gui/file/0c999ccda99be1c9535ad72c38dc1947d014966e699d7a259c67f4df56ec4b92/<br /><br />https://www.virustotal.com/gui/file/ff97d7da6a89d39f7c6c3711e0271f282127c75174977439a33d44a03d4d6c8e/<br /><br />Python Deep Learning: configurations<br /><br />AndroLinuxML : https://drive.google.com/file/d/1N92h-nHnzO5Vfq1rcJhkF952aZ1PPZGB/view?usp=sharing<br /><br />Linux : https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing<br /><br />Windows : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing</div><div><br /></div><div>*Windows {<br />To Compress using CPU/GPU: MS-OpenCL<br />https://is.gd/MS_OpenCL<br />https://is.gd/OpenCL4X64<br />https://is.gd/OpenCL4ARM<br /><br />Upscale DL<br />https://is.gd/UpscaleWinDL</div><div><br /></div>https://is.gd/HPC_HIP_CUDA<br /><br />https://www.amd.com/en/developer/rocm-hub/hip-sdk.html#tabs-ddafbba141-item-c6b9ce2aab-tab<br />https://rocm.docs.amd.com/en/docs-5.5.1/deploy/windows/quick_start.html<div><br /></div><div>X86Features-Emu<br />https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing</div><div>}<br /><br />Machine Learning SDK's,<br />You may not have a Machine Learning SDK to accelerate your GPU/CPU/Device<br /><br />3 main ones, but Python does not guarantee an accelerator!<br />Obviously Python Builds with Accelerators work!<br /><br />HW Build Source : Upscale DL<br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonML<br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonImageFilter<br /><br />PoCL Source & Code<br />https://is.gd/LEDSource</div><div><br /><div>*</div></div>https://github.com/ssube/diffusers/tree/feature/onnx-upscale<br /><br />https://github.com/huggingface/diffusers<br />https://huggingface.co/ssube/stable-diffusion-x4-upscaler-onnx<br /><br />https://huggingface.co/uwg/upscaler/tree/main<br />https://huggingface.co/nvmmonkey/optimal_upscale/tree/main<br />https://huggingface.co/gmp-dev/gmp-upscaler/tree/main/ESRGAN<br /><br />Neural Engine<br />https://github.com/godly-devotion/MochiDiffusion<br /><br />ML List & Services<br />https://huggingface.co/models?sort=downloads&search=upscale<br />https://huggingface.co/models<br />https://huggingface.co/pricing</div><div><br /></div>Tokma ML</div><div><br /></div>Batch Size 240W>65W, 32GB{64, 16}, 15W>5W, 4gb{16, 1} : 16, 8, 4 seems optimal,<br />Time taken compatible:<div><br /></div><div>ML_With_USB_Stress-Testing_USB_Accelerators_for_Efficient_Edge<br /><a href="https://drive.google.com/file/d/1s2DORhFyvg0jT7AMhtTPdyPk0Aimdemi/view?usp=drive_link">https://drive.google.com/file/d/1s2DORhFyvg0jT7AMhtTPdyPk0Aimdemi/view?usp=drive_link</a><br /><a href="https://github.com/raphischer/edge-acc">https://github.com/raphischer/edge-acc</a></div><div><br />Python & JS Configurations<br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a><br /><br />https://iopscience.iop.org/article/10.1088/1741-4326/ad142f<br /><br /><a href="https://is.gd/TokmaML">https://is.gd/TokmaML</a></div><div><br /><div>*</div><br />Training Networks</div><div><br /></div><div><a href="https://science.n-helix.com/2023/06/tops.html">https://science.n-helix.com/2023/06/tops.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/pm-qos.html">https://science.n-helix.com/2023/02/pm-qos.html</a><br /><a href="https://science.n-helix.com/2023/06/ptp.html">https://science.n-helix.com/2023/06/ptp.html</a><br /><br />ML_With_USB_Stress-Testing_USB_Accelerators_for_Efficient_Edge<br /><a href="https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference">https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference</a><br /><a href="https://github.com/raphischer/edge-acc">https://github.com/raphischer/edge-acc</a></div><div><br /></div>Coral TPU Micro Edge Learning with performance arranged Intel FPGA Arria 10 SX SoC Kit & Google Coral, NVIDIA Jetson Nano and CPU ROCK 4C Plus<br /><a href="https://doi.org/10.3390/s24030899">https://doi.org/10.3390/s24030899</a><br /><br />With both USB Devices being 8Bit INT, I would imagine all of the models would run on both in 8Bit INT<br /><a href="https://coral.ai/docs/edgetpu/models-intro/#transfer-learning-on-device">https://coral.ai/docs/edgetpu/models-intro/#transfer-learning-on-device</a><br /><a href="https://www.intel.com/content/www/us/en/developer/articles/technical/movidius-accelerator-on-edge-software-hub.html">https://www.intel.com/content/www/us/en/developer/articles/technical/movidius-accelerator-on-edge-software-hub.html</a><br /><a href="https://www.intel.com/content/www/us/en/support/articles/000033354/boards-and-kits/neural-compute-sticks.html">https://www.intel.com/content/www/us/en/support/articles/000033354/boards-and-kits/neural-compute-sticks.html</a><br /><br />39$ 2x Edge TPU, Prefer 6x or 8x M.2 & PCI 16x & 32x with 4GB+ RAM<br /><a href="https://coral.ai/products/m2-accelerator-dual-edgetpu/">https://coral.ai/products/m2-accelerator-dual-edgetpu/</a><br /><div><br /></div><a href="https://coral.ai/products/">https://coral.ai/products/</a></div><div><br /></div><div><h4 style="text-align: left;">Gimp Speed Figures, </h4>OpenCL per Selective Gaussian Blend<br />24GB RAM 8Core<br /><br />CPU 1.3m<br />RX200 60s <br />Movidius 10s<br />+Coral Offloads Int32 & processes; Processing INT8, <br />In that way the main CPU is the handler of most complex non inference tasks..<br />In many networks F32 & Int32 would be used to represent computation tasks & can be sieved optimally.</div><div><br /></div>With 8MB of Essentially RAM Writeback Cache; Input-Output though the USB or M.2/PCIe,<br />Loading tasks through the IO buffer; Into & out of the work buffer; The average flow cache would be around 256KB..<br />The machine Learning ML itself is between 32KB & Around 7MB.<br /><br />The Processor itself has multiple threads & IO/DMA Processes to directly inference or solve programming.<br /><br />Ideally Compressed RAM, with Rsrt ADD+ & MUL* & PACK & Min Mean & Max,<br />We can perform flexible basic maths,<br /><br />Flexible compression by copy & replication<br />Compression consisting of MUL expansions or fractions, MUL ADD & roll Example n+n*y = , n+((n+10)*y),<br />Compression formula consisting of algebra operations to unroll or roll & gradients Min=m to Max=y<br /><br />Examples of formula expansion compression</div><div><br />replication n+((n+10)*y)<br />Formula expansion n+(y*z) = , (n+y)*z =<br />gradients Min=m to Max=y , A++B till (N*t)=C then Min A to Max C | Median = D | D++t<br />(the above for example: ((n+y)*z = )Rsrt = )</div><div><br /></div><div>8MB Work buffer<br />256KB IO Buffer (Fast Frame Buffer); The effective memory used by images or audio may reach 2MB.</div><div><br /></div><div>The perfect Proposal RS<br /><br /><h4 style="text-align: left;">TOPS Conversion Table:</h4><br />8000G 16TOPS NPU + SiMD 13TOPS total 39TOPS,<br />Standard FX 8TOPS to 13TOPS All SiMD used!<br />EdgeTPU*2 8TOPS + CPU SiMD &or NPU..<br /><br />SiMD F32, F16, Int32, Int16, Combined 8Bit parallel ops..<br /><br />NPU F16, Int16, Int8, Int4,<br />TPU U8 & Int8,<br /><br />Perfection,<br /><br />Conversion recommendation work for NPU & SiMD:<br /><br />Int32/64 CPU + 8Bit Inference TPU<br />F32 conversion by removal of remainder Xor XMM & YMM XXX to Integer Inference; TPU 8Bit or NPU..<br /><br />Rupert S<div><br /></div><div>*<br /><br />The perfect Proposal RS {<br /><br />PCIe/M.2 TPU Dual Edge M.2-2230 E-key<br /><a href="https://www.amazon.fr/dp/B09DM31V2T/">https://www.amazon.fr/dp/B09DM31V2T/</a><br /><a href="https://www.amazon.co.uk/dp/B09DM31V2T/">https://www.amazon.co.uk/dp/B09DM31V2T/</a><br /><br /><a href="https://www.amazon.fr/s?k=coral+m.2">https://www.amazon.fr/s?k=coral+m.2</a><br /><a href="https://www.amazon.co.uk/s?k=coral+m.2">https://www.amazon.co.uk/s?k=coral+m.2</a><br /><a href="https://www.amazon.com/s?k=coral+m.2">https://www.amazon.com/s?k=coral+m.2</a></div><div><br /></div><div><a href="https://github.com/magic-blue-smoke/Dual-Edge-TPU-Adapter">https://github.com/magic-blue-smoke/Dual-Edge-TPU-Adapter</a><br /><a href="https://www.makerfabs.com/catalogsearch/result/?q=Low+profile+PCIe+for+two+Dual+Edge+TPU+cards">https://www.makerfabs.com/catalogsearch/result/?q=Low+profile+PCIe+for+two+Dual+Edge+TPU+cards</a><br /><br /><a href="https://www.amazon.fr/dp/B09ZDPP43X/">https://www.amazon.fr/dp/B09ZDPP43X/</a><br /><a href="https://www.amazon.co.uk/dp/B09ZDPP43X/">https://www.amazon.co.uk/dp/B09ZDPP43X/</a><br /><a href="https://www.amazon.de/dp/B09ZDPP43X/">https://www.amazon.de/dp/B09ZDPP43X/</a><br /><br /><a href="https://www.amazon.com.be/dp/B0BC8MQFJ6/?language=en_GB&th=1">https://www.amazon.com.be/dp/B0BC8MQFJ6/?language=en_GB&th=1</a><br /><a href="https://www.amazon.fr/dp/B0BC8MQFJ6/?language=en_GB&th=1">https://www.amazon.fr/dp/B0BC8MQFJ6/?language=en_GB&th=1</a><br /><a href="https://www.amazon.co.uk/dp/B0BC8MQFJ6/?language=en_GB">https://www.amazon.co.uk/dp/B0BC8MQFJ6/?language=en_GB</a><br /><a href="https://www.amazon.de/dp/B0BC8MQFJ6/?language=en_GB">https://www.amazon.de/dp/B0BC8MQFJ6/?language=en_GB</a><br /><br /><a href="https://www.amazon.com.be/dp/B0C2JC7MDX/">https://www.amazon.com.be/dp/B0C2JC7MDX/</a><br /><a href="https://www.amazon.fr/dp/B0C2JC7MDX/">https://www.amazon.fr/dp/B0C2JC7MDX/</a><br /><a href="https://www.amazon.co.uk/dp/B0C2JC7MDX/">https://www.amazon.co.uk/dp/B0C2JC7MDX/</a><br /><a href="https://www.amazon.de/dp/B0C2JC7MDX/">https://www.amazon.de/dp/B0C2JC7MDX/</a></div><div><br /></div><a href="https://hailo.ai/products/ai-accelerators/hailo-8-ai-accelerator/#hailo8-overview">https://hailo.ai/products/ai-accelerators/hailo-8-ai-accelerator/#hailo8-overview</a><br />Hailo M.2 & mPCIe are both available a 28TOPs 199$ & the (MultiProcessor) PCI Cards for around 300$ to 800$,<br />Unfortunately not sources on amazon.<br /><br />8TOPS M.2 <a href="https://Coral.ai">https://Coral.ai</a> 38$; Worth a thought.<div><br />Maybe<br />B Key / M Key M.2, M.2 NGFF B Key / M Key M.2 NGF, M 2 Specifications support : 2280/2260/2242/2230<br /><a href="https://www.amazon.fr/dp/B0CT3FXQM8/">https://www.amazon.fr/dp/B0CT3FXQM8/</a><br /><a href="https://www.amazon.co.uk/dp/B0CT3FXQM8/">https://www.amazon.co.uk/dp/B0CT3FXQM8/</a></div><div><a href="https://www.amazon.de/dp/B0CT3FXQM8/">https://www.amazon.de/dp/B0CT3FXQM8/</a><br /><br />ahum no<br /><br />SSD M2 key B/ key B+M/ key M)<br /><a href="https://www.amazon.fr/dp/B0CBWWD144/">https://www.amazon.fr/dp/B0CBWWD144/</a><br /><a href="https://www.amazon.co.uk/dp/B0CBWWD144/">https://www.amazon.co.uk/dp/B0CBWWD144/</a></div><div><a href="https://www.amazon.de/dp/B0CBWWD144/">https://www.amazon.de/dp/B0CBWWD144/</a><br /><br />GLOTRENDS M.2 M Key to E Key WiFi Adapter for M.2 WiFi Module<br />+ <a href="https://www.amazon.fr/dp/B09ZS1FHCG">https://www.amazon.fr/dp/B09ZS1FHCG</a></div><a href="https://www.amazon.co.uk/dp/B09ZS1FHCG">https://www.amazon.co.uk/dp/B09ZS1FHCG</a><br /><a href="https://www.amazon.de/dp/B09ZS1FHCG">https://www.amazon.de/dp/B09ZS1FHCG</a><div><br /></div><div>};<br /><br />USB<br /><a href="https://www.amazon.com/dp/B07S214S5Y">https://www.amazon.com/dp/B07S214S5Y</a><br /><a href="https://www.amazon.fr/dp/B07S214S5Y">https://www.amazon.fr/dp/B07S214S5Y</a><br /><a href="https://www.amazon.co.uk/dp/B07S214S5Y">https://www.amazon.co.uk/dp/B07S214S5Y</a><br /><br /><a href="https://www.amazon.fr/s?k=Dual+Edge+M.2-2230+E-key+to+pci">https://www.amazon.fr/s?k=Dual+Edge+M.2-2230+E-key+to+pci</a><br /><br /><a href="https://en.wikipedia.org/wiki/M.2">https://en.wikipedia.org/wiki/M.2</a><br /><br />To my knowledge M.2 E is basically PCIe but smaller, So adapter is fairly simple.<br /><br />HP/Mac/Dell/Acer<br /><br />The M.2 "E" key sockets are used for Wireless LAN/Bluetooth cards.<br />These sockets are common with laptop motherboards.<br />They are also found on some desktop motherboards (mITX, mATX, ATX).<br />Gigabyte offers mITX boards with this support.<br /><br /><a href="https://www.amazon.fr/dp/B09ZDPP43X/">https://www.amazon.fr/dp/B09ZDPP43X/</a><br /><a href="https://www.amazon.fr/s?k=wifi+M.2-2230+E+to+pcie">https://www.amazon.fr/s?k=wifi+M.2-2230+E+to+pcie</a><br /><br />*</div><div><div><br /></div><div>Analogue ML - Including Additive-Capacitor-'Battery' - Using the IBM analogue in-memory hardware acceleration kit for neural network training and inference - APL Machine Learning<br /><a href="https://pubs.aip.org/aip/aml/article/1/4/041102/2923573/Using-the-IBM-analog-in-memory-hardware">https://pubs.aip.org/aip/aml/article/1/4/041102/2923573/Using-the-IBM-analog-in-memory-hardware</a><br /><br />RAM ADDER differential Inference (c)RS : <br />RAM Table Accumulated addition node network Accumulator with Accumulation comparison Inference<br /><br />IBM Analog Hardware Acceleration Kit <a href="https://github.com/IBM/aihwkit">https://github.com/IBM/aihwkit</a></div><div><br />Matrix Processors - Multi Node SpiNNaker2 A Large-Scale Neuromorphic System<br /><a href="https://arxiv.org/pdf/2401.04491.pdf">https://arxiv.org/pdf/2401.04491.pdf</a></div><div><br />PysicsX<br />Isaac Gym - Preview Release<br /><a href="https://developer.nvidia.com/isaac-gym">https://developer.nvidia.com/isaac-gym</a><br /><br />CALM: Conditional Adversarial Latent Models for Directable Virtual Characters<br /><a href="https://github.com/NVlabs/CALM">https://github.com/NVlabs/CALM</a></div><div><br /></div><div>ML Strategic Workflow Training & Models - Machine Learning model guide Tensor to ONNX - Fraud Prevention & Statistics - Turning Data into Insight with IBM zOS16<br /><a href="https://www.redbooks.ibm.com/redpieces/pdfs/sg248552.pdf">https://www.redbooks.ibm.com/redpieces/pdfs/sg248552.pdf</a></div><div><br />Evolution-ML CNN Self Trained Auto Sparsity - Hybrid multi-objective evolutionary model compression with convolutional neural networks<br /><a href="https://www.sciencedirect.com/science/article/pii/S2590123024000045">https://www.sciencedirect.com/science/article/pii/S2590123024000045</a><br /><a href="https://blog.research.google/2023/12/advancements-in-machine-learning-for.html">https://blog.research.google/2023/12/advancements-in-machine-learning-for.html</a><br /><br />ML Compressed Dynamic16bit-8Bit - Hardware-friendly compression and hardware acceleration for ML Transformer<br /><a href="https://aimspress.com/article/doi/10.3934/era.2022192">https://aimspress.com/article/doi/10.3934/era.2022192</a><br /><br />AA-DLADMM - GD Gradient Descent - An Accelerated ADMM-based Framework for Training Deep Neural Networks<br /><a href="https://arxiv.org/pdf/2401.03619.pdf">https://arxiv.org/pdf/2401.03619.pdf</a></div><div><br />*<br /><h4 style="text-align: left;">Personality UI : Have a friend</h4><br />Alpaca Character Generation model<br />4Bit for speed, But not precise<br /><a href="https://huggingface.co/anon8231489123/gpt4-x-alpaca-13b-native-4bit-128g">https://huggingface.co/anon8231489123/gpt4-x-alpaca-13b-native-4bit-128g</a><br />trained 3Epoc Higher Precision <a href="https://huggingface.co/chavinlo/gpt4-x-alpaca">https://huggingface.co/chavinlo/gpt4-x-alpaca</a><br /><br />Base model <a href="https://huggingface.co/chavinlo/alpaca-13b">https://huggingface.co/chavinlo/alpaca-13b</a><br /><a href="https://github.com/teknium1/GPTeacher">https://github.com/teknium1/GPTeacher</a><br /><br />Python WebUI<br /><a href="https://github.com/oobabooga/text-generation-webui">https://github.com/oobabooga/text-generation-webui</a><br />Mac; Mostly MAC but fast<br /><a href="https://github.com/ggerganov/llama.cpp">https://github.com/ggerganov/llama.cpp</a><br /><br />how to use & personality sets https://discord.com/invite/aitrepreneur-1018992679893340160<br /><br />On the subject of how deep a personality of 4Bit, 8Bit, 16Bit is reference:<br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br />*<div><div><br />Machine learning | Equate ~= Multi Layer Wavelet Abstraction</div><div><br /></div><div><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><br />https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html</div><div><br />(documents) JIT & OpenCL & Codec : https://is.gd/DisplaySourceCode<br /><br /><div>Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />https://science.n-helix.com/2022/08/simd.html<br /><br />Eclectic & for the codecs of the world! OVCCANS (install and maintain as provided HPC Pack)<br /><br />https://science.n-helix.com/2018/09/hpc-pack-install-guide.html</div><div><br /></div>*</div><div><br /></div><div><h4 style="text-align: left;">Transversal processing availability : Transparent Task Sharing Protocols</h4><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br /><h4 style="text-align: left;">Machine Learning</h4><br />https://science.n-helix.com/2022/10/ml.html<br /><br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</div><div><br /></div><div><h4 style="text-align: left;">Innate Compression, Decompression</h4><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />https://science.n-helix.com/2022/09/audio-presentation-play.html<br /><br />https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html<br /><br />https://science.n-helix.com/2023/03/path-trace.html<br /><br />*****<br />Best NPM site on world https://npm.n-helix.com/bundles/<br /><br />(Simple Install) Website Cache JS Updated 2021-11 (c)RS https://bit.ly/CacheJS<br />(Simple Install) Science & Research Node High Performance Computing<br />Linux & Android https://is.gd/LinuxHPCNode<br /><br />Presenting JIT for hardware interoperability & function :<br />https://is.gd/DisplaySourceCode<br /><br />https://is.gd/BTSource<br /><br />(Simple Install) Website Server Cache JS Updated 2021-11 (c)RS<br />https://bit.ly/CacheJSm<br />(Simple Install) Website Server Cache JS Work Files Zip Updated<br />2021-11 (c)RS https://bit.ly/AppCacheJSZip<br />*****</div></div><div><br /></div><div>machine learning <a href="https://www.amazon.com/dp/B08V134ZFD">https://www.amazon.com/dp/B08V134ZFD</a></div></div></div><div><br /></div>*****<br /><br />Direct ONNX Hardware Accelerated: F16<br />https://github.com/GPUOpen-LibrariesAndSDKs/RadeonML</div><div><br />Ideal for 4Bit Int4 XBox & Int8 GPU<br />PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors - Bus-width 8-bit, 4-bit, 2-bit and 1-bit<br />https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/<br /><br />ML Proof case SVM (Multi-Dimensional-Elliptic,98%) aDaBoost M1(Mac,91%) - COVID-19 Prediction Using Supervised Machine Learning - Irfan_Ali_MEng_2023<br />https://dspace.library.uvic.ca/bitstream/handle/1828/14676/Irfan_Ali_MEng_2023.pdf?sequence=1&isAllowed=y</div><div><br /></div><div>Useful operation precision reductions<br />FPGA Implementation of Keyword Spotting System Using Depthwise Separable Binarized and Ternarized Neural Networks<br />https://www.mdpi.com/1424-8220/23/12/5701<br /><br />Useful operation precision reductions; I observe that reducing precision to 1Bit & 2Bit..<br /><br />While enhancing the definition of a positive, Negative Dipole & thus enhancing speed..<br />Further reduces reasoning capacity; That in order to reduce Processor bandwidth for reasoning..<br /><br />In the example of the XBox & PS5; DOT4 & INT4, INT8 & F16 & bF16; Apply considerable improvement to reductions probable error related to a lack of remainder or float value depth enhancement!<br /><br />By reason of probability i assume a value of 4Bit & 2Bit to allow the smallest packing ability; Existing alongside the word reasoned!<br /><br />To reduce to 1 & 0; I assume a definite statement that a Value Integer Solve in the form of a vector..<br />Is most probably the solution & that furthermore that in most cases; Projected in pure maths & code ASM,<br />Both SiMD; Float & Integer...<br /><br />Reduction to multiple 2 Bit values in short Integer instructions; I will state however that no such value is further away than a statistics table or PHP Data-Set.<br /><br />Rupert S 2023-06<div><br /></div>*****<div><br /></div>Gaussian<br />https://gmd.copernicus.org/articles/16/1697/2023/<br />https://gmd.copernicus.org/articles/16/1697/2023/gmd-16-1697-2023.pdf<br /><br />SiMD Gaussian Blending & Dithering - Better_Fixed_Point_Filtering_with_Averaging_Trees<br />https://andrew.adams.pub/Better_Fixed_Point_Filtering_with_Averaging_Trees.pdf<br /><br />Vectorization of Kernel and Image Subsampling in FIR Image Filtering<br />http://bncss.org/index.php/bncss/article/viewFile/101/105<br /><br />Implementation of a High-Quality Dolby Digital Decoder Using SiMD MMX™ Technology<br />https://smtnet.com/library/files/upload/dolby-intel.pdf<div><br /></div><div>*****<br /><br />Common techniques used in ML Learning are edge detection, accent recognition, language processing, and code optimization.<br /><br />Basic ML Feature list; Also for learning<br /><br />Edge detection is a process of identifying the boundaries of objects in images or videos.<br /><br />Accent recognition is a process of identifying the regional or social variation of speech.<br /><br />Language processing is a process of analyzing and generating natural language texts.<br /><br />Code optimization is a process of improving the performance or quality of code.<br /><br />https://www.ibm.com/topics/machine-learning<br />https://en.wikipedia.org/wiki/Edge_detection<br />https://en.wikipedia.org/wiki/Accent_recognition<br />https://en.wikipedia.org/wiki/Natural_language_processing<br />https://en.wikipedia.org/wiki/Code_optimization<br />https://en.wikipedia.org/wiki/Supervised_learning<br />https://en.wikipedia.org/wiki/Unsupervised_learning<br />https://en.wikipedia.org/wiki/Reinforcement_learning<br />https://www.ibm.com/cloud/learn/machine-learning-ethics</div></div></div><div><br /></div><div>*****</div><div><br /></div><h4 style="text-align: left;">Dynamic ML IRS-RIS 4G,5G Wave Shaping Edge detection with reflection angle calculation - strong wave localising edge (shaping)sharpening(c)RS</h4><br />By quantifying how waves bounce from reflective surfaces it is possible to shape waves that bounce in a different direction from a mechanical reshaping surface called a RIS..<br /><br />Reconfigurable intelligent surfaces & Intelligent reflecting surfaces bounce radio waves for wireless networks..<br /><br />Presenting the example: <br /><br />Coral TPU Micro Edge Learning with performance arranged Intel FPGA Arria 10 SX SoC Kit & Google Coral, NVIDIA Jetson Nano and CPU ROCK 4C Plus<br /><a href="https://doi.org/10.3390/s24030899">https://doi.org/10.3390/s24030899</a><div><br /></div>ML_With_USB_Stress-Testing_USB_Accelerators_for_Efficient_Edge<br /><a href="https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference">https://www.researchgate.net/publication/377174200_Stress-Testing_USB_Accelerators_for_Efficient_Edge_Inference</a><br />https://github.com/raphischer/edge-accRed Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-32052317931401644442022-10-04T23:23:00.006+02:002023-07-21T21:22:59.240+02:00Vibration Array Spectrometer : (c)RS<h4 style="text-align: left;">Vibration Array Spectrometer : (c)RS</h4><br />Vibrating side to side & where necessary up and down & at angles to create a complete wavelength photo & data from events such as nuclear reactions..<br /><br />The devices specific vibrational frequency can range into the thousands Hz & must slow down before vibrating back to assist delicate sensor material from cracking or fracturing during work cycles..<br /><br />We can use compound to bounce absorbed energy back the other way; Such as silicone & rubber,<br />But they will be Soft & springy to reduce energy transfer of heat or radiation..<br /><br />Must also be capable of resisting high & low temperature or environmental energies for long periods.<br /><br />Super conducting surface vibration is capable of shifting a side strengthened cube at higher frequency with wave motions & sound also.<br /><br /><h4 style="text-align: left;">Interpolation of Spectrometer Data RS 2022</h4><br />We can examine the light shift with our spectrometers & use interpolation arrays to make photos of it, <br /><br />Thus we will be able to isolate the spectrometric data more precisely on our telescopes; When we use split colour wavelength spectrometry.<br /><br />How do these Interpolation arrays work ?<br /><br />We align the orbital position & azimuth & time with the specific wavelength in our Sapphire Crystal Grid Sensor spectrometer,<br /><br />We do this with time so that we can align multiple orbit passes or vibrations of our sensor & create a sharp full spectrum image & data array!<br /><br />We then can verify the exact spectrum of each star or subject; For example when using a spectrometer in CERN that vibrates at high frequency..<br /><br />(c)Rupert S<br /><br />*****<br /><br /><h4 style="text-align: left;">Interpolation in the age of Virtual Screen Resolution/Scaling : The process of evolutions in sharpness for over qualified displays(proud makers) (c)Rupert S</h4><br />LED Pixel By Pixel exact full screen display of all resolutions with automatic compatibility for all input VESA Resolutions & Zero incompatibility with Any Resolution in the correct dimensions : RS https://is.gd/LEDSource<br /><br />With PoCL & FSR intrinsic<br /><br />It makes perfect sense that scaling frames is done though PoCL & FSR, Indeed both are required for CPU function!<br /><br />Streaming services frame video & scale it & so do games, the scaling of inset video is a logical vector of FSR Scaling & colour correct display... HDR, SD, Rec709, Rec2020<br /><br />Pure Tone Encoding/Decoding Codec<br /><br />Applies to Displays & Camera/Recording Equipment; Codec: Decode & Encode,<br />Colours of composing display or recording elements; Red, Green, Blue, Grayscale Channel,<br />Pure tone Encoding & Decoding.<br /><br />*<br /><br />FRC is clever Dither : https://is.gd/BTSource https://is.gd/LEDSource<br /><br />The main thing about Rec709 10Bit is that all 10Bit is in LED Standard spectrum, All 1.07B colours; Add FRC this is important!<br /><br />Rec2020 is flexible upto 12/14Bit So 8Bit+2/4/6/8Bit FRC makes sense! & so does 10Bit + FRC<br /><br />FRC Modes:<br /><br />6Bit+FRC (for car & mobile tablet)<br /><br />8Bit+FRC<br /><br />10Bit+FRC<br /><br />*<br /><br />https://is.gd/ColourGrading<br /><br />4 primary colour composure: RS<br /><br />What does decomposing a frame into 4 colour groups mean?<br /><br />Red, Green, Blue, Grayscale<br /><br />Each pixel on a screen has 4 colour components & they are on a different place on the screen,<br />So when we sharpen; We sharpen to the closest pixel LED of the right colour,<br /><br /><div>Obtaining the best colour with the most logical of LED content,<br />the right colour sharpened for the right LED<br /><br />Fist of all "We Have to decompose the image into primaries to compose the screen in it's highest colour value composite" Sharpening our composure to maximum colour correctness & sharpness Is only a:<br /><br />*<br /><br />Interpolation FRC Frame Compose:<br /><br />CPU Estimate 300Mhz : 600Mhz : 900Mhz<br /><br />2 step process,<br /><br />Max 3 Processor Cycles:<br />Get/Fetch, Decompose, Blend & Sharpen,<br /><br />Compose/FRC to pure Primaries Pixel & Interpolation<br />Max 5 Cycles<br /><br />*<br /><br />The creation of the frame requires so much data bandwidth, more pictures means more RAM...<br />Refinement means less error repair?<br /><br />So what can we do ?<br /><br />This is how interpolation works in principle:<br /><br />We find the edges of a blurred image, now for our purposes we will Super Sample that image before saving it!<br /><br />Therefore we have maneuvering room to upscale the actual screen & we can!<br /><br />Using a simple principle of dividing the Image pixel count into its defining Red, Green, Blue & contrast shadow...<br /><br />We have three planes of existence? no 4! Red, Green, Blue, Backlight or light shading!<br /><br />With this we interpolate the nearest Pixel of the closest matching colour..<br /><br />Not perfect; We still can lose contrast, <br />But we can take an upscaled image enhanced Alpha blend & get more from the actual display.<br /><br />We can imagine the image being too red,green,blue, too contrasted?<br /><br />But no, The project is to bring real extra resolution to the screen; By dividing our Red,Green,Blue,Black & White pixels into individually sharpened & together blended master piece,<br /><br />One picture; 4 parts; One Whole piece<br /><br />4 primary colour composure: RS<br /><br />What does decomposing a frame into 4 colour groups mean?<br /><br />Red, Green, Blue, Grayscale<br /><br />Each pixel on a screen has 4 colour components & they are on a different place on the screen,<br />So when we sharpen; We sharpen to the closest pixel LED of the right colour,<br />Obtaining the best colour with the most logical of LED content,<br />the right colour sharpened for the right LED<br /><br />Divided we FALL, Together we stand tall, The important bit is to catch the pieces that start to fall & rebuild tall!<br /><br />Rupert S<br /><br />If you design and create LED Monitors & TV's & want 165Hz refresh rate you often have sRGB, OLED Monitors are over 2x the price! So you need LED,<br /><br />But how do we get the best out of LED?<br /><br />Two ways: to be clear we use both methods at the same time!<br /><br />1: We use FRC to increase colour references within our pallet ...<br />2: We sharpen & smooth unique content!<br /><br />*<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2022/08/simd.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />Reference source https://is.gd/LEDSource<br /><br />Main interpolation references:<br /><br />This doc https://drive.google.com/file/d/1dn0mdYIHsbMsBaqVRIfFkZXJ4xcW_MOA/view?usp=sharing<br /><br />ICC & FRC https://drive.google.com/file/d/1vKZ5Vvuyaty5XiDQvc6LeSq6n1O3xsDl/view?usp=sharing<br /><br />FRC Calibration ><br /><br />FRC_FCPrP(tm):RS (Reference)<br /><br />https://drive.google.com/file/d/1hEU6D2nv03r3O_C-ZKR_kv6NBxcg1ddR/view?usp=sharing<br /><br />FRC & AA & Super Sampling (Reference)<br />https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing<br /><br />Audio 3D Calibration<br />https://drive.google.com/file/d/1-wz4VFZGP5Z-1lG0bEe1G2MRTXYIecNh/view?usp=sharing<br /><br />2: We use a reference pallet to get the best out of our LED; Such a reference pallet is:<br /><br />Rec709 Profile in effect : use today! https://is.gd/ColourGrading<br /><br />Rec709 <> Rec2020 ICC 4 Million Reference Colour Profile : https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing<br /><br />For Broadcasting, TV, Monitor & Camera https://is.gd/ICC_Rec2020_709<br /><br />ICC Colour Profiles for compatibility: https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing<br /><br />https://is.gd/BTSource<br /><br />Colour Profile Professionally<br />https://displayhdr.org/guide/<br />https://www.microsoft.com/store/apps/9NN1GPN70NF3<br /><br />*Files*<br /><br />This one will suite Dedicated ARM Machine in body armour 'mental state' ARM Router & TV https://drive.google.com/file/d/102pycYOFpkD1Vqj_N910vennxxIzFh_f/view?usp=sharing<br /><br />Android & Linux ARM Processor configurations; routers & TV's upgrade files, Update & improve<br />https://drive.google.com/file/d/1JV7PaTPUmikzqgMIfNRXr4UkF2X9iZoq/<br /><br />Providence: https://www.virustotal.com/gui/file/0c999ccda99be1c9535ad72c38dc1947d014966e699d7a259c67f4df56ec4b92/<br /><br />https://www.virustotal.com/gui/file/ff97d7da6a89d39f7c6c3711e0271f282127c75174977439a33d44a03d4d6c8e/<br /><br />Python Deep Learning: configurations<br /><br />AndroLinuxML : https://drive.google.com/file/d/1N92h-nHnzO5Vfq1rcJhkF952aZ1PPZGB/view?usp=sharing<br /><br />Linux : https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing<br /><br />Windows : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing<br /></div><div><br /></div>*******<div><h4 style="text-align: left;">Medical Spectroscopy : RS</h4><br />Medical Spectroscopy, as used on POP & Pope for Pulmonary issues last month)The Synergy for upscaling between SiMD, Matrix & Maths reaches a new hight with { Super temporal Resolution Imaging : RS<br /><br />For checking Processors, RAM, Components & LED & Technology for production errors & validity of course RS<br /><br />07:48 21/07/2023<br /><br />The Synergy for upscaling between SiMD, Matrix & Maths reaches a new hight with<br />{<br />Super temporal Resolution Imaging of Membrane Potential via Stroboscopic Microscopy<br /><br />https://is.gd/SpectroscopyPDF<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />https://science.n-helix.com/2023/06/map.html<br />}<br /><br />Vectors & maths<br />https://science.n-helix.com/2022/08/simd.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br />https://science.n-helix.com/2022/04/vecsr.html<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />Networking & Management<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/02/pm-qos.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2022/01/ntp.html<br /><br />Faster Maths & ML<br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Focus on Quality<br />https://science.n-helix.com/2022/09/ovccans.html<br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />Hallelujah RS Light-Wave SiMD https://www.allaboutcircuits.com/news/lightelligence-reports-worlds-first-optical-network-on-chip-processor/<br /><br />(c)RS<br /><br />**********************************<div><br /><h4 style="text-align: left;">Technology Super temporal Resolution Imaging (STRI)</h4><div><br />Technology called Super temporal Resolution Imaging (STRI), which uses SiMD, matrix, and math to achieve higher temporal resolution than traditional imaging techniques. STRI has the potential to revolutionize the field of medical spectroscopy, as it could be used to study biological processes in unprecedented detail.<br /><br />The text also links to a number of articles and websites that provide more information about STRI. The article from the American Chemical Society (ACS) provides a detailed overview of the technology, while the website from N-Helix discusses the potential applications of STRI in medical spectroscopy.<br /><br />Overall, the text provides a good overview of the new technology of STRI. It is clear that STRI has the potential to make a significant impact on the field of medical spectroscopy, and it will be interesting to see how this technology develops in the future.<br /><br />Here are some additional thoughts on the potential of STRI:<br /><br />STRI could be used to study the dynamics of biological processes in real time. This could lead to new insights into the mechanisms of disease and the development of new treatments.<br /><br />STRI could be used to image individual cells and organelles. This could provide new information about the structure and function of these cellular components.<br /><br />STRI could be used to image tissues and organs in vivo. This could provide new insights into the functioning of the human body.<br /><br />The potential applications of STRI are vast, and it is likely that this technology will have a major impact on the field of medical research in the years to come.<br /><br />Here are some specific examples of how STRI could be used in medical spectroscopy:<br /><br />I do not expect to think of everything.. Rupert S<br /><br />To Examine technology in production for defects.<br />To Study earth minerals, Chemicals & Compounds.<br />To Study Physical Dynamic Effects such as Atom polarity & Physics.<br /><br />To study the dynamics of cell signaling.<br />To image the movement of molecules within cells.<br />To visualize the activity of individual proteins.<br />To diagnose and monitor diseases.<br />To develop new drugs and treatments.<br /><br />The possibilities are endless, and it is exciting to think about how STRI could be used to improve our understanding of human health and disease.<br /><br />(c)RS </div></div></div><div><br /></div>*<br /><br />Reference Examples Spectroscopy :<br /><br />Super temporal Resolution Imaging of Membrane Potential via Stroboscopic Microscopy<br />https://pubs.acs.org/doi/epdf/10.1021/cbmi.3c00054<br /><br />Synchrotron X-ray Studies of the Structural and Functional Hierarchies in Mineralised Human Dental Enamel: A State-of-the-Art Review<br />https://www.mdpi.com/2304-6767/11/4/98<div><br /></div><div>Spectroscopy - Spatial-Super-Sample SpectralRay Attention-Enhanced Generative Adversarial Network for Hyperspectral Imagery Spatial Super-Resolution<br />https://www.mdpi.com/2072-4292/15/14/3644</div><div><br />Enterobacter hormaechei -Driven Novel Biosynthesis of Tin Oxide Nanoparticles and Evaluation of Their Anti-aging, Cytotoxic, and Enzyme Inhibition Potential<br />https://www.researchgate.net/publication/372427993_Enterobacter_hormaechei_-Driven_Novel_Biosynthesis_of_Tin_Oxide_Nanoparticles_and_Evaluation_of_Their_Anti-aging_Cytotoxic_and_Enzyme_Inhibition_Potential<br /><br />Spectral Observations and Modeling of a Solar White-light Flare Observed by CHASE<br />https://iopscience.iop.org/article/10.3847/2041-8213/ace18c</div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-82266384334068053212022-09-29T03:29:00.006+02:002023-07-28T10:09:53.453+02:00Audio presentation & play"I made a codec but I am not sure how to improve it! probably interpolation"<br /><br />Audio presentation & play (c)Rupert S<br /><br />Available for Bluetooth, VESA, HDMI & DisplayPort & Hardware such as GPU, CPU & Equipment.<br /><br />Well the thing is that Wavelets (Dynamic mathematical NDimension Nd Shape objects),<br />& Also PCM is Pictorial 2D & 3D shape in forms such as BitMap.<br /><br />To explain bitmap; This is a picture; Now with a picture we can present an enhanced version using bilinear interpolation & Trilinear Interpolation...<br /><br />PCM is a BitMap or JPG or WebP Wavelet 2D drawing of a graph that translates into Audio by copying the frequency & volume.<br /><br />So basically any operation used on Audio can be used on visual elements; Including wave filters & resonators or WaWa Bars,<br /><br />Digital Audio presented as BITMAP presents an ideal situation where we can enhance it with Graphical effects such as sharpening & shaping or smoothing..<br /><br />We can also present the Audio in 3D through a non literal presentation of 3D through Colour or shade on the drawing; or present that audio in a parallel bars or side by side presentation..<br /><br />The Sound Colour Table : RS<br /><br />We can use colour to present precision, Warmth & vibrational intensity & amplitude..<br />We can use cross shading to present repetition, Translation & transition..<br />We can present so many ways, But more importantly we can compress colour in ways like wavelet<br />We can Present 3D & Virtual Surround through Colour<br /><br />We can also present the Audio as WebP or Textures including our compressed forms; However we have to reduce our compression so that no artifacting occurs.<br /><br />New Audio Formats:<br /><br />Wavelet Bitmap<br />Texture formats such as STC, ATC, HDR, Deep Colour<div>Texture formats such as Drill & SLLRL, ASTC, EAC, DXT, PVRTC & DSC<br /><a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a> , <a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby</a> , <a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a> , <a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a></div><div><br />32Bit Float<br />24Bit Float<br />16Bit Float<br /><br />We can potentiate the floating point by using it to present 3D Audio virtualisation or to improve audio precision.<br /><br />Rupert S<br /><br />*<br /><br />XeSS Is here and is great! #Exclusive<br /><br />https://www.youtube.com/watch?v=uMqKFgJcr-U<br /><br />Lets use both XeSS & FSR to do Audio Sampling in 3D Wavelet (audio PCM<br />is just a BMP Saved!<br />We can do much more & compress more & still have better quality!<br /><br />*****<br /><br /><h4 style="text-align: left;">O!DMD : Original Dynamic MIDI Audio Device(tm) : Wavelet Vocal & Music/Action/Audio Sample, Instruments & Percussion Simulation, The principle is as follows: (c)RS</h4><br />24Bit Audio Sample + 8 Bit for audio modifications: 3D Audio, Resonance, Tempo, Pitch, Style Etcetera<br /><br />A Wavelet is a Shape; A Shape is a LPCM, MP3, MP4 & AC3 & AC4 Wavelet according to the MP4 Standard...<br />A Wavelet is 12Bit to 32Bit in precision Sample & from 32Kbs to 384Kbs in Bitrate Samples<br />A Voice/Sample Synth Quality is determined by the Bitrate; We can use Wavelet Sample to Simulate!<br />We can simulate any Sound with a sample; We can vary the Sound Style, Tempo, Scale & Range...<br />We can use real processed samples; We can resample Live & Locally or in cloud<br />Emulation does not need to be 2D, 3D or Processed into 3D & 2D with the same size room in mind for reverb & echo & VR 3D Audio<br /><br />8Bit Modifier can be 4Bit Modifier + 4Bit 3D VR + 24Bit Audio Sample<br /><br />(c)Rupert S<br /><br />https://science.n-helix.com/2022/09/audio-presentation-play.html<br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2022/01/ntp.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br />https://science.n-helix.com/2021/02/multi-operation-maths.html<br />https://science.n-helix.com/2021/11/parallel-execution.html<br />https://science.n-helix.com/2022/12/math-error-solve.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />Sparse matrix multiplication in SRM array<br />https://www.science.org/doi/10.1126/sciadv.adf7474<br /><br />Error Correction Options & Mitigation<br />https://futurism.com/ibm-breakthrough-quantum-computing<br /><br />*****<br /><br /><h4 style="text-align: left;">Soft Interrupt IRQ: Faster CPU Cycles: RS</h4><br />A Soft Interrupt is where you direct the interrupt register to a compiled Code Block..<br />The code block handles the Wait Queue in a gentle way that allows processing to continue & Ram to be accessed..<br /><br />While the HDD directly writes the IRQ messages to the Code Block; The Code block is below the size of Cache on the Processor..<br /><br />In advanced scenarios the Soft Int Caches Read/Write in RAM while Directing DMA & R/W Cached Cycles; Good Bioses & Software do this.<br /><br />But in a processor Internals you have to call the Main Micro loops (Soft Int) in your App; & OS Task Instruction cache.<br /><br />RS<br /><br />Interrupts particularly effect the Processor functions such as..<br />Machine Learning Load & Store of Frames, Also the internet..<br />In such as Network cards offloading is often required to handle interrupts..<br /><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />*****</div><div><br />Compression formats:<br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br />Data Saving by inexact replication & Double layer wavelet shaping which are both one believes compatible with analog output & also with adjustment repeat play.<br /><br />Compression matrix<br /><a href="https://drive.google.com/file/d/1xQ0t7LEYltQ8TR3MDsV4IHE8wrfsfWV0/view?usp=sharing">https://drive.google.com/file/d/1xQ0t7LEYltQ8TR3MDsV4IHE8wrfsfWV0/view?usp=sharing</a><br /><br />SLLRunLength : Compressed Pixel<br /><a href="https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing">https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing</a><br /><br />Drill texture & image format (with contrast & depth enhancement)<br /><br /><a href="https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing">https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing</a><br /><a href="https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing">https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing</a></div><div><br /></div><div><a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU </a><br /><a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby </a><br /><a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a><br /><a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a></div><div><br />https://is.gd/BTSource<br /><br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a></div><div><br /></div>Secure Configuration:<br /><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM</a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a><br /><a href="https://is.gd/SSL_NetSecurity_NTP_PTP">https://is.gd/SSL_NetSecurity_NTP_PTP</a><br /><a href="https://is.gd/EthernetTunnelOpt">https://is.gd/EthernetTunnelOpt</a><br /><br />PTP & NTP Improve security WW <a href="https://is.gd/PTP_TimeStream">https://is.gd/PTP_TimeStream</a><br />Open Streaming Codecs 2023 <a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-46846000310578550632022-09-12T00:40:00.068+02:002023-12-25T01:41:42.782+01:00OVCC_ANS : Optimised Vector component Compression with Alpha Numeric Sequencing & Compression<h4 style="text-align: left;">OVCC_ANS : Optimised Vector component Compression with Alpha Numeric Sequencing & Compression (c)Rupert S</h4><div>*</div>Suitable for codec, Texture, Video Element, Firmware & ROM, Executable, Storage & RAM, DLL & Library runtimes, CSS & JS & HDMI & DisplayPort VESA Specifications : <div>https://science.n-helix.com/2022/09/ovccans.html</div><div>https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br /><div><br /><div>Eclectic & for the codecs of the world! OVCCANS (install and maintain as provided HPC Pack)<br />https://science.n-helix.com/2018/09/hpc-pack-install-guide.html<br /><div>*</div><br /><h4 style="text-align: left;">OVCC_ANS : RS</h4><br />Suitable for codec, Texture, Video Element, Firmware & ROM, Executable, Storage & RAM, DLL & Library runtimes, CSS & JS & HDMI & DisplayPort VESA Specifications</div><div><br /></div>Storage Problems EEPROM : Small powerful packed firmware for Devices, Routers, TV's Cameras & Computers</div><div><br /></div><div>*</div><div>Devices, Drivers, VESA DSC & Active display drivers<br />PoCL & CL Kernels are used for the codecs & shading; Simply from the point of view multithreading SysCL & OpenCL are most effective at headless worker kernels; Frame buffer not required.<br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a></div><div><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a></div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br />*</div><div><br />Cache Cyclic load segment Code Replication is quite a bit more efficient from the Shader, OpenCL, SiMD & Float expression point of view.<br /><br />With code replication you do not necessarily have to depack the RAM to run the code; But that is a question of Jumps or Cache Cycles!</div><div><br /><div><div><div>Similar to vector render on the optimised Vector component input compression is a layer of compression that renders fine lines, Curves & circles & points & basic gradients,</div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Principle of the Repeater with Co-modifier Gradient Wavelet & Numbers: RS</h4><br />The primary principle to remember is that a gradient wavelet is in effect (in music terms):<br /><br />A Sustain (Echo note)<br />A Pause (A silence (Space is taken in a file for this)<br /><br />A Register Shaped Sustain (Where we move up the scale or down the scale or in a curve; With the same resonance sample, Example Trumpet or Piano or Harp)<br /><br />A Repeater note : Exact repeat, Varied over time repeat, Quieter or louder, Modified by a coefficient.<br /><br />So principle is : Copy Note sound & Modify over time, Repeat over time, Repeat & modify over time.</div><div><br /></div><p style="text-align: left;">Also repeating for lines in an Image & hence video.</p><br />For example Bumps on a door or the texture of paint,<br />Light & shadow over the same texture; How complex this is depends on required quality!<br /><br />Image, Number Or Audio sample: Data Complexity & How many SiMD Computation Cycles are required..<br />The more repeats or how large; Varies the processing workload.<br /><br />Example: Hello World<br /><br />Hello World Sample : [HWS] , Silent Echo Sample : [SES]<br /><br />#PrintF Hello World<br /><br />[SES], [HWS], [SES]x2, [HWS]x2(louder), [SES](Quieter), [HWS]x4(Louder to quieter), <br />[SES]x4 (Quieter to much quieter), [HWS]x4(quieter to Louder), [SES]x2(louder to quiet), [HWS]x4(Louder to quieter),</div><div><br /><div>*<br /><h4 style="text-align: left;">Wavelet Float forms</h4><div><br />Wavelet bF16, F16 are quite useful for MP4 Standard compression<br />Wavelet bF32, F32 are quite useful for MP4 Enhanced Precision compression<br />Speed = bF16 (with advantages of long chain integer & small exponent)<br />For AVX F32 up to F64 are variously advantaged in multithreading,<br />Exceptionally bF16 & F16 NANO SiMD<br />*</div><div><br />OVCC is used to apply layers of vector graphic elements with optimised wavelets..<br />In principle the file is saved like so:<br /><br />OVCC Layers<br /><br />V = Vector<br />W = Wavelet<br />Gv = Gradient vector<br />Ns = Numeric Sequence<br />As = Alphabet Sequence<br />Ans = Alpha Numeric Sequence<br /><br />{Load Binary or code: DLL,Exe, Library, WebJS for example}: {Firmware, Separate or joined}<br />{ Header }<br />{ Value storage for replication }<br />{ Gv:1>n, W:1>n, V:1>n }<br />{ Cans:1>n, Ns:1>n, As:1>n, Ans:1>n }<br /><br />Vector Storage<br /><br />[Gv];[Gv];[Gv]<br />[V];[V];[V];[V]<br />[W];[W];[W];[W]<br />[V];[Gv];[V];[Gv]<br />[W];[W];[V];[Gv];[W];[W];[V];[Gv]<br /><br />Sequence Storage<br /><br />[Ans];[Ans];[Ans]<br />[Ns];[Ns];[Ns];[Ns]<br />[As];[As];[As];[As]<br />[Ns];[Ans];[Ns];[Ans]<br />[As];[As];[Ns];[Ans];[As];[As];[Ns];[Ans]</div><div><br /></div><div>Code Sequence Storage<br /><br />[Loader]<br />[Cans];[Cans];[Cans]<br />[Ans];[Ans];[Ans]<br />[Ns];[Ns];[Ns];[Ns]<br />[As];[As];[As];[As]<br />[Ns];[Ans];[Ns];[Ans]<br />[As];[As];[Ns];[Ans];[As];[As];[Ns];[Ans]</div><div><br />You can use vector compression on plane transparency & Greyscale adding a lot to sharpness if optimised.</div><div><br /></div>*<br />You see at the worst Drivers are compiled with last stage DSC Compression as Pixel shaders or compute shaders, <br /><br />Thus avoiding bad bios DSC VESA But you can use OpenCL & directly render the frame as smoothing is not particularly required! <br /><br />Even though before DSC a Smooth Wavelet is a big advantage to compression ratio & sharpness<br /><br />But OpenCL Can smooth & sharpen with AA & SS Implemented.</div><div><br /></div><div>Could We make all codecs compress & decompress ? We can!<br />I might have an MP4 DVD & also HPC requires WebP compression feature <br />& also HDR formats like JPGXL & JPG2000 & WebP & H264 & H265 & VP9 & AV1 on systems,<br />Like the RX570 & ARM, CPU & GPU; With OpenCL Support in all programs & for the operating system<br /><br />OpenCL Hardware Compression is possible for all encoding formats & textures<br /><br />VP9, AV1, Media compression acceleration! <br />But what to use based on de/compression performance? <br />VP9/H265 Currently Hardware Accelerated 90% of the time.</div><div>*</div><br /><h4>DSC/AV1/VP9/MPEG/H265/H264 Block Size Streamlining (c)RS</h4><p style="text-align: left;">Code/JS/OpenCL/Machine Learning Processing Block Size Streamlining (c)RS</p></div><div><br />Dataset AV1/VP9/MPEG/H265/H264 : case example <br />My personal observation is that decompression & compression performance relates to block size & cache<br /><br />SiMD 8xBlock x 8xBlock Cube : 32Bit | x 4 128Bit | x 8 256Bit | x 16 512Bit<br />Cache Size : 32Kb Code : Code has to be smaller inline than 32Kb! Can loop 4Kb x 14-1 for main code segment<br /><br /><br />Cache Size 64Kb Data : Read blocks & predicts need to streamline into 64Kb blocks in total,<br />4Kb Optimized Code Cache<br />4Kb Predict (across block for L2 Multidirectional)<br />16Bit Colour Compressed block 4x16Bit (work cache compressed : 54Kb<br />Lab Colour ICC L2 & block flow L2</div><div><br /><div><div>*</div>The advice i give is given with honour & is stated true, We all need a good VP9 & AV1 & Media Codecs!<br />The advice, is to refresh the stream & restart the browser; You can see the world better with #True-Sourcery</div><br />Get rid of 90% of your intel & other device Codec Glitches and errors..<br />Compile right!</div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Compression, Dictionary Sort & Same Size Copy Match & Unite Same with location in 2D Matrix #JS #C #Python RS 2023</h4><br /><a href="https://is.gd/CJS_DictionarySort">https://is.gd/CJS_DictionarySort</a><div><br /><div>*</div><div><br /></div><div>*****</div><br /><h4 style="text-align: left;">Ellipso formula for compressed media:</h4><br />The headers are encrypted with AES:{GCM, CCM}, CHACHA20-POLY1305<br />The header containing compression words, File List, Directory & Data chunks for replication..<br /><br />Ellipso encoded data segments for example graphs, Curves, Shapes, A:B:C colour or audio & math scaling curves,<br />Representing data curves such as colour gradients & corners or ellipses; In Lines or Cubes..<br /><br />Conception is similar to compression data compression shapes; But defining most shapes & colour or sound samples.<br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><a href="https://science.n-helix.com/2022/11/frame-expand-gen-3.html">https://science.n-helix.com/2022/11/frame-expand-gen-3.html</a><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a></div><div><br /></div><div>Bluetooth dongle LE Protocol<br /><a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a></div><div><br />Rupert S</div><div><br /><div>*****</div><div><br /></div><h4>2 layer/Plane Codecs: RS</h4>Texture Compression & video Compression for quality 12Bit & 16Bit HDR & WCG,</div><div><br /></div>Can also be used in displays for tiling & animation of screen array with multiple frames single post,<br />Cache & post commands; Single DIMM Post with multiple frames for lower Processor Cycle costs..<br />Screen brightness & colour control per tile; Single line post or Screen Post Cube Suggested.<br /><br />In applications 2 layer/Plane texture can post to GPU & animate multiple frames with overlay texture or animation.</div><div><br /></div><div>In video codecs can animate frame on base layer (background for example)</div><br />2 Planes / 2 Layer : Monitor, TV & Codec to screen cycle (advantageous to GPU & ARM Configured units & displays)<div><div><br /><div>Animated or Image or 2 plane static + Animation frame (BumpMapping)</div><div>More than 2 Layers is possible but 16Bit & 32Bit SiMD & ALU suggest a range:</div><div><br /></div><div>*</div><div>16Bit Effective ++ List : 2 Layer : ETC, ASTC Etcetera : Compatible Compression</div><div><br /></div><div>10Bit + 4Bit + Modifiers</div><div><div>12Bit + 4Bit</div><div>10Bit + 6Bit</div></div><div><br /></div><div>8Bit + 6Bit + Modifiers</div><div>8Bit + 4Bit + Modifiers</div><div><div>8Bit + 8Bit</div><div>8Bit + 4Bit</div></div><div>*</div><div><br />Basic 2 layer involves using another Plane/Layer as a mask,<br /><br />Primary layer is 8Bit, 12Bit, 16Bit <> NBit Texture; Secondary layer is a mask:<br /><br />Mask Methods:<br /><br />1 Layer Texture : Can be animated but second layer will be Sync Timed.<br /><br />2a layer is darker / lighter Image, Grayscale : HDR + small varieties in shade = WCG<br />2b layer is darker / lighter Image, Colour, Additive to Colour range + Light/Dark : WCG & HDR<br />2c Layer subtracts or Adds , Multiplies / Divides : Basic maths operations : Work = Depth<br /><br />https://is.gd/BTSource<br /><br />https://is.gd/Dot5CodecGPU <br />https://is.gd/CodecDolby<br />https://is.gd/CodecHDR_WCG & <br />https://is.gd/HPDigitalWavelet<br /><br />DSC, DXT5, ETC, ATC, PVRTC, ASTC & DTX Compression for display frames<br /><br />These are the main XRGB : RGBA Reference for X,X,X,X <br />https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing<br />https://drive.google.com/file/d/12vbEy_1e7UCB8nvN3hYg6Ama7HIXnjrF/view?usp=sharing<br /><br />(c)RS</div><div><br /></div><div>*****</div><div><br /></div><h4 style="text-align: left;">F16b Adaptive Float value : Texture Color Palette Example : RS</h4><br />Basic Example of F16b float in action on a colour pallet: {F16b,F32b, F64b}<br /><br />F16b is short remainder F16 & it has 8 Bits of 0.01 point value rather than 16,<br />So what do we mean ? What is significant about this?<br /><br />F16b Has 24Bit precision integer with an 8 bit remainder!<br />So? So 16Bit + 8Bit = 24Bit! & 8bit point value...<br /><br />In colour representation point values contribute to subtle blending;<br />So a full 24Bit contributes to 90% of the Color Palettes<br /><br />So the 24Bit colour pallet is 32Bit Colour Minus Alpha;<br />We can use F16b in HDMI & DisplayPort & inside the GPU & Also for textures & JPG'S..<br />Thereby i present F16b & F24Bit colours in F16b<br /><br />This saves all data in single 32bit Spaces & therefore is both faster & higher resolution than comparable float value presentations.<br /><br />Bound to make a big difference to BlueRay, but particularly DVD & AC3 & AC4; <br />F16b Adaptive Float value : Texture Color Palettes Example; <br /><br />(you can use F16b * R,G,B,A) in HDMI a& DisplayPort, Massive colour improvements; Lower RAM Costs<br /><br />Rupert S</div><div><div><br /></div><div>*<br /><h4 style="text-align: left;">{Solve} : {Maths Roll Error}</h4>{Maths Roll Error on 24Bit Audio versus 32Bit} ~= Stutter<br /><br />Additional roll, Error margin on 32Bit maths Float with 24Bit 5 point margin roundups,<br />A 32Bit float rolls up on a single operation 226526554817.{24Bit float + Error roundup} .9> .49 = .5+ = roll up.. <br /><br />R={5+ or 4- | 0.45+ or 0.44-} : or {0.445, |> 0.444444444445 |> 0.4 N4 +Decimal Places +5}<br /><br />Clipping operation depth of float; Is 3 operations or 2 with Stop count = 1 to 24 bit places + 1 or 2 for error rolling, up or down.<br /><br />Precision Clip<br />Math OP | Clip > Cache {Math OP <> Use}<br /><br />Precision Counter<br />Math OP + Counter(internal to FPU:CPU | Stop > Cache {Math OP <> Use}</div><div>*</div><h4 style="text-align: left;">SiMD Performance : RS</h4><br />Performance per WATT of MMX & MMX+ & SSE & AVX Machine Learning & Shader code; Is a matter of 8x8Bit & 16x16Bit Code on GPU<br /><br />Our role is to reduce complex un-cache-able ML to Cache Enabled 64KB<br />Modelling of 1990's without Quality loss of 32Bit++ 64Bit+<br /><br />8x8Bit sharpening MMX Becomes Dual Pipe (16x16bit)*2 in 32Bit Dual 16 Pipeline & Twice as sharp<br />Machine Learning method for MMX Is Fast & Cheap, MMX2 More Compatible,<br />Intrinsic improvements such as combined ops & DOT4 Further improve the performance of under 1MB Code..<br /><br />Performance & Function per WATT, Is unbeaten; Let us prove it!<br /><br />For example Quake has MMX Emulation & MMX Dithering code on 3D Textures, <br />In 8Bit 256 Colours dithering is noticeable; In 15Bit to 32Bit the small shade difference in dithering colour is subtle & flawless, <br />Improving light subtilty & Colour pallet WCG & HDR 10Bit to 16Bit per channel.<br /><br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br /><a href="https://is.gd/MLCodecShaping">https://is.gd/MLCodecShaping</a><div>*<br /><div><h4 style="text-align: left;">Drill texture & image format (with contrast & depth enhancement)</h4><br />https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing<br /><br />https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing</div><div><br /></div>Scanline Coder Compression <br />https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing</div><div><br /></div>WebP<br /><a href="https://github.com/webmproject/libwebp">https://github.com/webmproject/libwebp</a><br />https://github.com/webmproject/libwebp/blob/main/ChangeLog</div><br />AV1<br />https://github.com/AOMediaCodec</div><div><br />HEIF:HEVC<br />High Efficiency Image Format (HEIF) is being introduced : 10Bit>16Bit HDR<br />High Efficiency Video Codec (HEVC)-encoded storage system for intra-images and HEVC-encoded video image sequences in which inter-prediction is applied; Also for still images compressed with the HEVC (H.265) codec.<br />https://www.photoreview.com.au/tips/shooting/heif-what-you-need-to-know/<br />https://www.howtogeek.com/345314/what-is-the-heif-or-heic-image-format/<div><br /></div><div>File Compression Logic<br />https://is.gd/BitStreamSpec<br />https://is.gd/IFFByteOrder</div><div><br /></div>Compression Speed Results<br /><a href="https://quixdb.github.io/squash-benchmark/#results-table">https://quixdb.github.io/squash-benchmark/#results-table</a><br /><br />File & Texture Compressors<br /><a href="https://github.com/GPUOpen-LibrariesAndSDKs/brotli_g_sdk">https://github.com/GPUOpen-LibrariesAndSDKs/brotli_g_sdk</a><br /><a href="https://github.com/BinomialLLC/basis_universal">https://github.com/BinomialLLC/basis_universal</a><br /><a href="https://github.com/darksylinc/betsy">https://github.com/darksylinc/betsy</a><br /><a href="https://github.com/ARM-software/astc-encoder/">https://github.com/ARM-software/astc-encoder/</a><br /><a href="https://github.com/synfosec/packz">https://github.com/synfosec/packz</a><br /><a href="https://is.gd/CJS_DictionarySort">https://is.gd/CJS_DictionarySort</a><br /><br />Python & JS Configurations<br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a></div><div><br />To Compress using CPU/GPU: MS-OpenCL<br /><a href="https://is.gd/MS_OpenCL">https://is.gd/MS_OpenCL</a><br /><a href="https://is.gd/OpenCL4X64">https://is.gd/OpenCL4X64</a><br /><a href="https://is.gd/OpenCL4ARM">https://is.gd/OpenCL4ARM</a><br /><br />PoCL Source & Code<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a></div><div><br />VVC<br />https://github.com/fraunhoferhhi/vvenc<br />https://github.com/fraunhoferhhi/vvdec</div><div><br /></div><div>https://gitlab.com/AOMediaCodec/SVT-AV1/-/blob/master/Docs/CommonQuestions.md#improving-decoding-performance</div><br />Reference : "Patent license terms" https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding#2022<div><div><br /></div>Secure Configuration:<br /><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM</a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a><br /><a href="https://is.gd/SSL_NetSecurity_NTP_PTP">https://is.gd/SSL_NetSecurity_NTP_PTP</a><br /><a href="https://is.gd/EthernetTunnelOpt">https://is.gd/EthernetTunnelOpt</a><br /><br />PTP & NTP Improve security WW <a href="https://is.gd/PTP_TimeStream">https://is.gd/PTP_TimeStream</a><br />Open Streaming Codecs 2023 <a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a><div><br /></div><div>Codec Parallelism - Dataflow model PREESM, OpenMP and OpenCL<br />OpenVVC & OpenHEVC Decoder Parameterized and Interfaced Synchronous DataFlow Tile Based Parallelism (PiSDF)</div><div>Create the dataflow model is called PREESM. This tool allows the automatic scheduling of tasks according to the number of used cores and the automatic generation of multicore algorithms.<br />https://link.springer.com/content/pdf/10.1007/s11265-022-01819-7.pdf<div><div><br /></div><div>"State-of-the-art approaches such as OpenMP and OpenCL"<br />https://is.gd/BTSource<br /><br />https://is.gd/LEDSource<br /><br />(documents) JIT & OpenCL & Codec : https://is.gd/DisplaySourceCode<br /><br />Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html</div><br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html</div><div><br /><div>https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />https://science.n-helix.com/2022/08/simd.html</div><div><br /></div>Eclectic & for the codecs of the world! OVCCANS (install and maintain as provided HPC Pack)<br /><br />https://science.n-helix.com/2018/09/hpc-pack-install-guide.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html</div><div><br /></div><div>Suitable for codec, Texture, Video Element, CSS & JS & HDMI & DisplayPort VESA Specifications : https://science.n-helix.com/2022/09/ovccans.html</div></div></div><div><br /></div>https://science.n-helix.com/2023/02/smart-compression.html</div><div><br /></div><div>Strobe Line by Line Run Length Compression DVB, NTSC, VESA :RS Approved <br />https://drive.google.com/file/d/148-BpVSfT6bA5nPjKoiZ41vwuI9n7P_f/view?usp=sharing<div><br /></div><div>Networking & Management<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/06/tops.html<br />https://science.n-helix.com/2023/06/ptp.html<br />https://science.n-helix.com/2023/02/pm-qos.html<br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2022/01/ntp.html<div><br /></div><div>https://www.gyan.dev/ffmpeg/builds/</div><div>https://github.com/GyanD/codexffmpeg/releases/tag/tools-2022-01-01-git-d6b2357edd</div><div>https://github.com/GyanD/codexffmpeg/releases/tag/5.1.1</div><div>https://www.gyan.dev/ffmpeg/builds/ffmpeg-tools.zip</div><div>https://github.com/GyanD/codexffmpeg/releases/download/5.1.1/ffmpeg-5.1.1-full_build.zip</div><div><br /></div><div>https://ffmpeg.org/download.html</div><div>https://ffmpeg.org/releases/ffmpeg-snapshot.tar.bz2</div></div><div><br /></div><div>Full H265, H264 & AV1 Support https://drive.google.com/file/d/1Xka_QSRmVBCqnyCZwrA_yjnqwSl4g0ml/view?usp=sharing</div><br />VP9, AV1, Media compression acceleration! <br />But what to use based on de/compression performance? <br />VP9/H265 Currently Hardware Accelerated 90% of the time<br /><br />Get rid of 90% of your intel & other device Codec Glitches and errors..<br />Compile right!<br /><br /><div>Easy Install Codecs : <a href="https://is.gd/DilyWinCodec">https://is.gd/DilyWinCodec</a></div><br />The advice i give is given with honour & is stated true, We all need a good VP9 & AV1 & Media Codecs!<br />The advice, is to refresh the stream & restart the browser; You can see the world better with #True-Sourcery<div><br /></div><div>*<br />'Study Observation' YouTube switches from pushing AV1 by majority to<br />VP9 & H265 which encodes slightly less, I mean slightly because my own tests<br />indicate a 300MB/h HD.. So VP9 & H265 Rock with E-AC3 & E-AC4 5.1:<br /><br />The majority of GPU acceleration of VP9 & H265 & H264 is a good<br />reason! So let us clarify H264, H265 & VP9 Will become better with<br />this document. Rupert S<br /><br />To clarify major improvement to H264, H265 & VP9 are clearly required for class leader,</div><div>There may be some doubt as to H264 but not of H265 & VP9!,</div><div><br /></div><div>However this is 'In 'Statute'' fundamental versioning..</div><div><br /></div><div>Allowing GPU to continuance to provide a quality of service of exceptional quality for the available price!</div><div>Our continued support of the aged & the mentally fit & the able; Of this world & of our society.<br /><br />OpenCL Compatibility is making these codecs faster: For the highly expectant x64 FFmpeg crew, </div><div>A Most compatible; Easy Install Codecs: <a href="https://is.gd/FFmpegWinCodec">https://is.gd/FFmpegWinCodec</a></div><div><br />Easy Install Codecs: <a href="https://is.gd/DilyWinCodec">https://is.gd/DilyWinCodec</a></div><div>Easy Install Codecs 4 ARM: <a href="https://is.gd/DilyWinARMCodec">https://is.gd/DilyWinARMCodec</a></div><div><br /></div><div>Example : <a href="https://drive.google.com/drive/folders/1JwbEGHiCzbeDFoRnF43VUHUDZlwcibcX?usp=sharing">https://drive.google.com/drive/folders/1JwbEGHiCzbeDFoRnF43VUHUDZlwcibcX?usp=sharing</a><br />* </div><br />OpenCL & other Hardware Acceleration : FFMPEG<br />https://ffmpeg.org/ffmpeg-all.html<br />https://ffmpeg.org/documentation.html<div><br /><div><div>https://ffmpeg.org/download.html<br />https://ffmpeg.org/releases/ffmpeg-snapshot.tar.bz2<br />https://github.com/FFmpeg/FFmpeg<br />https://github.com/FFmpeg/FFmpeg/releases/tag/n3.0<div><br />HQImage<br />https://apps.microsoft.com/store/detail/webp-image-extensions/9PG2DK419DRG<br />https://www.microsoft.com/en-us/p/heif-image-extensions/9pmmsr1cgpwg<br />https://www.microsoft.com/en-us/p/hdr-wcg-image-viewer/9pgn3nwpbwl9<br />https://www.microsoft.com/en-us/p/raw-image-extension/9nctdw2w1bh8<br /><br />HQVideo<br />https://www.microsoft.com/en-us/store/p/web/9n5tdp8vcmhs<br />https://www.microsoft.com/en-us/p/mpeg-2-video-extension/9n95q1zzpmh4<br />https://www.microsoft.com/en-us/p/av1-video-extension/9mvzqvxjbq9v<br />https://www.microsoft.com/en-us/p/vp9-video-extensions/9n4d0msmp0pt<br />https://www.microsoft.com/en-us/p/hevc-video-extensions/9nmzlz57r3t7<div><br /></div><div>*****<br /><br />https://www.phoronix.com/news/Rust-UEFI-Firmware-Hope-Tier-2<br /><br />https://rust-lang.github.io/compiler-team/<br /><br />https://dvdhrm.github.io/2022/09/07/towards-stable-rust-uefi/<br /><br />https://doc.rust-lang.org/nightly/rustc/platform-support/unknown-uefi.html<br /><br />https://github.com/rust-lang/compiler-team/issues/555<br /><br />Yes Firmware Codec Development is the Dinosaur!<br />DOLBY ATMOS 7.1.2 "Dinosaurs in Atmos"- OFFICIAL THEATER DOLBY VISION [4KHDR]<br />https://www.youtube.com/watch?v=0EKBYVUj4w0</div></div></div></div></div></div><div><br /></div>*****<br /><br /><h4 style="text-align: left;">Stone Effect : Image compression for all skin types & Art (c)Rupert S (available to all games):RS</h4><br />Marble is a beautiful product; People draw it too low quality (in older games) Or too high ôo Oblivion,<br />Several properties exist in Marble & stone,<br />Firstly Marble is a co-modifier colour range of mostly gray & white with black over a 1cm² to 10cm² Aria,<br />As in the pattern has points; Draw the curves and shapes from a central higher contrast area; With tiny modulations of light & dark &or One colour subtly blended with another...<br /><br />This can be done two ways:<br /><br />Highly detailed Texture in HDR & WCG.... 4MB texture<br /><br />Highly detailed Texture in HDR & WCG, But Pallet Limited to 4 zones,<br />These 4 zones are White & off-White, Dark & Off-Dark, Green, gold, Brown, Gray & White.<br />These colours apply colour culling between the primary group & therefore reduce the colour pallet by 50%; You compress the file with the off colour zone colours Culled & Save storage file size.<br />.... 1.5MB texture<br /><br />Extra detail is payed to which patterns are sharp high contrast & which patterns are smooth & useful to blend with the AA SSA Shader (post render & recache)<br /><br />Pay attention to animation because not all skin types require direct texture refresh & shaders can micro map a layer on top & thus keep the texture flawless for little cost.<br /><br /><br />Raytrace into the filter layer (Transparency Depth) (a layer of Shader, BumpMapping, & light textures & Animations)<div><br /></div>*****<br /><br />Good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />These are the addresses directly of some good ones; DNS & NTP & PTP 2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b 142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-54338747321489258582022-08-29T15:51:00.027+02:002023-07-28T23:01:48.224+02:00JIT Compiler Dongle - The Connection HPC 2022 RS<h4 style="text-align: left;">JIT Compiler Dongle - The Connection HPC 2022 RS (c)Rupert S</h4><br />JIT Compiler Dongle makes 100% Sense & since it has no problem acting like a printer! It can in fact interface with all printers & offload Tasks,<br /><br />However in High Performance Computing mode of operation the USB Dongle acts as the central processor from the device side; That is to say the device such as the printer or the Display...<br /><br />You can supply a full workload to the dongle & of course it will complete the task with no necessity of assistance from the computer or the device.<br /><br />The JIT Compiler comes into its own one two fronts:<br /><br />Compatibility between processor types.<br /><br /><div>Aiding a device in processing &or passing work to that device to run; Work that is shared & if required workloads are passed back & forth & shared,<br /><br />Shared & optimised...<br /><br />The final results for example are post-scripts? no problem!<br />The final results for example are Directly Compute Optimised Printer Jet algorithms? no problem!<br />The task needs to compute specifics for a DisplayPort LED Layout ? no problem!<br /><br />The device is powerful so share, JIT Compiler for real offloading & task management & runtime.<br /><br />Functional Processing Dongle Classification USB3.1+ & HDMI & DisplayPort (c)RS<br /><br />Theory 1 Printer<br /><br />Itinerary:<br /><br />Printers of a good design but low manufacturing cost of ICB printed circuits have a printhead controller,<br /><br />But no Postscript Processor; But they do have a print dither controller & programmable version need to interface with the CPU on the printing device,<br /><br />Print controlling is a viable Dongle & also Cache but workload cache has to have a reason!<br /><br />That reason here given is the JIT Dongle that is able to interface with both Web print protocol & IDF Printing firmware.<br /><br />But here we have postscript input into the JIT Compiles Kernel & output in terms of Jet Vectors & line by line Bitmap HDR & head motion calculations,<br /><br />We can also tick the box on Postscript offloading on functioning PostScript printers; But we prefer to offload JIT for speed & size..<br /><br />Vectors & curves & lines & Cache.<br /><br />Theory 2 Screen<br /><br />Itinerary as of printers but also VESA & line by line screen print & VESA Vectors & DisplayPort Active displays,<br /><br />Cable Active displays require the GPU to draw the screen & calculate the Line Draw!<br /><br />The Dongle activates like a screen with processor & carries the screen processing out; Instead of a smartwatch or small phone that does not have a good capacity for computer lead active display enhancements.<br /><br />Theory 3 Hard Drives & controller such as network cards & plugs for PCI<br /><br />Adapting to Caching & processing Storage or network data throughput commands, While at the same time being functionally responsive to system command & update makes JIT Dongle stand out at the head of both speed & function...<br /><br />Network cards can send offloading tasks to the PCI socket & the plug will process them.<br /><br />Hard-drives can request processing & it shall be done.<br /><br />Motherboard ROMs & hardware can request IO & DMA Translation & all code install is done by the OS & Bios/Firmware.<br /><br />Offloading can happen from socket to Motherboard & USB Socket & URT..<br /><br />All is done & adapts to Job & function in host.<br /><br />The 8M Motherboard & OS verifies the dongle, licences the dongle from the user..<br />& runs commands! Any Chipset, Any maker & every dongle by Firmware/Bios<br />What the unit constitutes is a functional Task offloader for OS & Bios/Firmware.<br /><br />The utility is eternal & the functions creative & secure & licensed/Certificate verified.<br /><br />Any Motherboard can be improved with the right Firmware & Plugin /+ device.<br /><br />(c)RS</div><div><br /></div>*****<div><br /></div><div><h4 style="text-align: left;">DDM Super Immediate Display Modes with 0ms GTG : Operation Latency Zero</h4><br />By initiating DDM & using the display processor aswell with DPIC JIT, <br />With DDM Frame Buffer Emulation & Control.<br /><br />Games & Aiming for Business,<br />DDC & FreeSync Update today!</div><br />In order to set DDM Super Immediate Display Modes you have to set the<br />display as being DDM with an input frame buffer..<br /><br />That way both the GPU & the Display can work on the frame in ALLM<br />Mode; Enhancing processing while reducing latency.<div><br /></div>*<br />FreeSync - DDM - Low Latency Screen Modes<br /><br />HDMI & DisplayPort : Screen Framebuffer {DDM, FreeSync, ALLM} : Minimal latency post processing : RS<br /><br />Direct Drive Monitor (DDM) is a mode where the Frame is directly created by the CPU/GPU facing the screen,<br />The frame buffer facing the Processor must present all capacities & properties of the Screen directly..<br /><br />List of common properties:<br /><br />Frame Buffer & Frame buffer write control<br />Bit depth & FRC<br />DSC mode<br />ICC Colour Profile<br />Write Cache buss width<br />Timings<br />Latency<br />LED Colour range & profile<br /><br />The GPU/CPU must have the capacity to order write cycles & DSC Decompression layer,<br />The GPU/CPU must not have a discussion writing to the screen; Direct Write shall be immediate!<br /><br />So we need to have the frame buffer process as fast as possible & report back,<br />But we plan to initiate a frame buffer & process it!; Process the frame fast,<br />To do that we provide all the information from our frame buffer that the CPU/GPU needs to calculate..<br /><br />Rupert S<br />*<div><div><h4 style="text-align: left;">A DDM Monitor is directly controlled by a GPU/CPU</h4><br />Initiating a Direct Drive Monitor (DDM) capability enables ultra-thin monitors (and Mobile Phone Screens) With a Short Plug DSC Compression Array...<br /><br />Could be simple!<br /><br />Initiate a DDM Mode with DPIC: JIT Kernel to a Frame Processing Unit that directly presents as a surface; All tasks from there in will not be allowed to add latency.<br /><br />(DDM) DPIC JIT Compiler Mode handles the situation of under performing hardware quite well,<br /><br />The aim is to solve one of the largest issues with DDM & that is latency! & Frame Distortion such as Frame Blur,<br /><br />Long cable access to a device encounters the same latency issues as RAM & Storage,<br />Distance means time!<br /><br />By Directly compiling commands into an (ESK) Efficient Static Kernel; Stack space (Cache & RAM)...<br /><br />Processing load is light & may be performed On The Edge; Close to the hardware; in our case a screen with a Single Core ARM Nano millimeters close to the screen.<br /><br />No we do not need a large CPU that close; But a SiMD array & Texture decompressor & Direct screen print...<br /><br />We do all our Large Problem solving previously in JIT Kernels; While doing what we can closer to the screen at our Frame Buffer,<br /><br />We can also directly process commands directed from a larger processor; a CPU, GPU, HUB,<br /><br />All we need to do is Initiate a DDM Mode with DPIC: JIT Kernel to a Frame Processing Unit that directly presents as a surface; All tasks from there in will not be allowed to add latency.<br /><br />Rupert S<br /><br />*<br /><h4 style="text-align: left;">Direct Drive Class : Displays, Printers & Devices such as Joysticks, Mice & keyboards</h4><br />You know Active Display, <br />The DisplayPort & HDMI Configuration, <br />JIT Compiler is a way of getting these to work internally inside the GPU &<br />In Port class units & USB Dongles that process Computation tasks,<br /><br />The JIT Compiler DPIC System processes for the Display,<br /><br />Therefore Able to Activate the display to the highest level of<br />processing with minimal requirements of necessity!<br /><br />For example Active Displays with basically a Micro NUC that has an arm<br />processor & is 4 CM² with USB Connection, <br />Therefore can power an active display (the type with smaller processors)<br /><br />Additionally can carry out more work & share a single NUC with<br />multiple Active Displays.. <br /><br />Bearing in mind that such a OpenCL/JIT Driver is universal to all Systems & Simply classifies by processor<br />class.<div><br /></div>*<br /><br /><h4 style="text-align: left;">The primary motivation for Direct Drive Class displays & Equipment is to offload Processing tasks to the GPU/CPU...</h4><br />However by example we can Flow Control frames on the HDMI & DisplayPort cables,<br />We do this by Writing a Kernel/OpenCL Code (Around 60KB) that queries the Frame Ready Flag/Property in the GPU...<br /><br />Example of Coding Model {Display CPU <> GPU} : Audio : Video : Texture Set<br /><br />OpenCL Kernel Runtime 512Kb (aim)<br /><br />Set Properties of display screen (Size & compression & Unique properties such as Texture Types)<br />Request Frame memory Allocation<br />Frame Pull (Demand a frame)<br />Query Frame & Send Ready flag<br /><br />When Frame Ready***<br /><br />Send workloads to GPU on frame: Example<br />Decompression Stack<br />Frame Mask<br />Memory Load (Direct DMA access to RAM from Cable)<br /><br />Sort functions,<br />Optimisation tasks such as Colour range optimisation & WCG, HDR Tone Mapping.<br /><br />We keep these operations from sending frame & texture back; by operating on the frame analysis before sending frame...<br /><br />Reception process involves sending:<br /><br />Data From Tasks first<br />RAM Page Map (if we did this process on GPU)<br />Frame<br />Process (We send additional tasks if required from a worker thread)<br /><br />Send out Query : Repeat!<br /><br />#GoodFramingDirectDrive<br /><br />RS</div><div><br /></div><div>***<br /><h4 style="text-align: left;">Plan 2023-03-07 Direct Map DDM : Efficient Monitor Direct Frame Forwarding Render : DDM ALLM : Rupert S</h4><br />DDM Combined with Combining Texture converters, FSR & OpenCL (Compilable for processor types & Firmware),<br /><br />Allows the HDMI & DisplayPort FrameBuffer Abstraction layer to pass fully optimized texture layers directly into Frame Rendering & therefor to be directly DMA Copied to the screen along with the Colour conversion table mapping (can be done by the GPU, The Monitor or be Hardware intrinsic to DSC.<br /><br />DPIC JIT Compiler (Kernels : Small & into Precompiled Code Array Buffer)<br /><br />https://drive.google.com/file/d/1D27MOBYKVkKib1JzP_eFucp8RRrzAhd6/view?usp=sharing, https://drive.google.com/file/d/1DbcifAxrG4XKfJ9Mrpsfq7kq1I4aV5ES/view?usp=sharing, https://drive.google.com/file/d/1d_bWbZl9fAZXsLbN_jZdqSxdWzraLSIz/view?usp=sharing<br />***<div><br /></div>GTG : GoodToGame : Consoles, Gaming & Movies : RS<br /><br />DDM ALLM Dongle use case - 10K Presentation of abstract data polygons<br /><br />Dear VESA & HDMI; This gaming feature does rely on the GPU (in the main) but does have CPU Capacity; Particularly in consoles of the new generation!<br /><br />Luckily in my experience the CPU is often under utilized by Vulkan API & DirectX 12.1 & therefore the use of DDM mode combined with the JIT Compiler OpenCL compile is a very logical choice! due to DDM being VESA we arrange it,<br /><br />Clearly the RAMDAC does pre compute a frame & clearly a frame is no more than 15% work for a FreeSync monitor,<br /><br />Combining the strengths of 2016+ TV & monitor ARM processors (600Mhz+; obviously less powerful than 550Mhz & DDM + ALLM + FreeSync + JIT Compiler is a clean logical choice)<br /><br />RAMDACS are 600Mhz but we can multitask; So we shall.<br /><br />Rupert S on behalf of VESA & HDMI & the gaming & Film community.<div><br /><div><div><div>*****</div><div><br /><h4 style="text-align: left;">Example Display Chain (Can be USB/Device Also For the OpenCL Runtime; To Run or be RUN) (c)RS</h4><br />How a monitor ends up with an OpenCL : CPU/GPU Run Time Process: Interpolation & Screen enhancement: The process path<br /><br />Firstly we need to access the GPU & CPU OpenCL Runtime such as:<br /><br />Components that we need:<br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a></div><div><br /></div>FPGA 'Xilinx Virtex-II' HPC application Multiple-Applications & Image-Net & Matrix-Multiplication - H-SIMD machine _ configurable parallel computing for data-intensive HPC<br /><a href="https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations">https://digitalcommons.njit.edu/cgi/viewcontent.cgi?article=1836&context=dissertations</a><div><br /></div>A SIMD architecture for hard real-time systems<br /><a href="https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2">https://www.repository.cam.ac.uk/bitstream/handle/1810/315712/dissertation.pdf?sequence=2</a><br /><br />Ideal for 4Bit Int4 XBox & Int8 GPU<br />PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors - Bus-width 8-bit, 4-bit, 2-bit and 1-bit<br /><a href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/">https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6939244/</a><div><br /></div><div>Predict Scaling : SiMD/AVX.SSE3:<br /><a href="https://science.n-helix.com/2023/03/path-trace.html">https://science.n-helix.com/2023/03/path-trace.html</a></div><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><div><br />Firstly, we need an OpenCL Kernel : PocCL : <br /><br />PoCL Source & Code<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br /><br />MS-OpenCL<br /><a href="https://is.gd/MS_OpenCL">https://is.gd/MS_OpenCL</a></div><div><a href="https://is.gd/OpenCL4X64">https://is.gd/OpenCL4X64</a><br /><a href="https://is.gd/OpenCL4ARM">https://is.gd/OpenCL4ARM</a></div><div><div><br /></div>Upscale DL<br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL</a><br /><br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a><br /><br />X86Features-Emu<br /><a href="https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing">https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing</a><br /><div><br /></div>Crucial components:<br /><br />Microsoft OpenCL APP<br />Microsoft basic display driver OpenCL component (CPU)<br /><br />CPU/GPU OpenCL Driver<br />PoCL Compiled runtime to run Kernels https://is.gd/LEDSource<br /><br />We need an Ethernet connection to the GPU (Direct though the HDMI, DisplayPort), <br />A direct connection means no PCI Bus or OS Component needed, <br />(But indirect GPU Loaded OpenCL Kernel loading may be required)<br /><br />Or<br /><br />We need an Ethernet connection to the PC or computer or console!<br />Then we need a Driver (this can be integral or Drive) to load the OpenCL Kernel; This can have 3 parts in the main to run it!<br /><br />Microsoft OpenCL APP<br />Microsoft basic display driver OpenCL component (CPU)<br /><br />CPU/GPU OpenCL Driver<br />PoCL Compiled runtime to run Kernels https://is.gd/LEDSource<br /><br />The compiled Kernel itself & this can be JIT : Just In Time Compile Runtime<br /><br />Rupert S</div><div><br />*****</div><div><br /><h4 style="text-align: left;">The DPIC Protocol in use for display, robotic hardware (arms for example) & Doctor Equipment arms & surgeries, Website loading or games.</h4><br />In context of load for DPIC, We simply need a page (non-displaying Or Displaying (for example Monitor Preferences)) Inside the GPU..<br /><br />Can use WebJS, WebASM : WASM, OpenCL : WebGPU : WebCL : WebGPU-ComputeShaders...<br /><br />RAM Ecology wise between 1MB to 128MB RAM (But should inform client in print of options); I cannot really imagine you would need more apart from complex commands (cleaning for example & robots)<br /><br />Direct Displayport & HDMI Interface; With or without use of USB Protocol HUB..<br /><br />Touch screen operation examples:<br /><br />Can additionally Smart pick diagnostic process of operations or equipment placement & screw & nut & bolting operations & welding or cutting!<br /><br />For example, the DPIC Protocol can interface & runtime check Operations, Rotations, Motions & activations in well managed automatons; While directly interfacing the ARM/X64/RISC Processor tools & where necessary optimise memory & instruction ASM Runtime Kernel. <br /><br />*<br /><br />How does PTP Donation Compute work in business then:<br /><br />Main JS Worker cache (couple of MB)<br /><br />{ main . js }<br /><br />{<br /><br />{ Priority Static JS Files }<br /><br />{ Priority Static Emotes & smilies (tiny) }<br /><br />{ Priority Application JS & Static tiny lushi images (tiny) }<br /><br />}<br />{<br /><br />{ Work order sort task }<br /><br />{ Sub tasks group }<br /><br />{Compute Worker Thread }<br /><br />}<br /><br />*</div><div><br />(c)Rupert S<br /><br />*****<br />Technology Demonstration https://is.gd/DongleTecDemo<br /><br />Combining JIT PoCL with SiMD & Vector instruction optimisation we create a standard model of literally frame printed vectors :<br /><br />VecSR that directly draws a frame to our display's highest floating point math & vector processor instructions; lowering data costs in visual presentation & printing.<br /><br />(documents) JIT & OpenCL & Codec : https://is.gd/DisplaySourceCode<br /><br />Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html</div><div><br /></div>https://science.n-helix.com/2022/08/jit-dongle.html<br /><br />Bus Tec : https://drive.google.com/file/d/1M2ie8Jf_bNJaySNQZ5mqM1fD9SAUOQud/view?usp=sharing</div><div><br /></div><div>Audio BT Codec<br /><br /><a href="https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html">https://science.n-helix.com/2021/10/he-aacsbc-overlapping-wave-domains.html</a><br /><br />DSC, ETC, ASTC & DTX Compression for display frames<br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><div><br /></div><div><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><br /><br /><a href="https://science.n-helix.com/2016/04/3d-desktop-virtualization.html">https://science.n-helix.com/2016/04/3d-desktop-virtualization.html</a><br /><br /><a href="https://science.n-helix.com/2019/06/vulkan-stack.html">https://science.n-helix.com/2019/06/vulkan-stack.html</a><br /><br /><a href="https://science.n-helix.com/2019/06/kernel.html">https://science.n-helix.com/2019/06/kernel.html</a></div><br /><a href="https://science.n-helix.com/2023/03/path-trace.html">https://science.n-helix.com/2023/03/path-trace.html</a><div><br /><a href="https://science.n-helix.com/2022/03/fsr-focal-length.html">https://science.n-helix.com/2022/03/fsr-focal-length.html</a><br /><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a><br /><br /><a href="https://science.n-helix.com/2022/08/simd.html">https://science.n-helix.com/2022/08/simd.html</a></div><div><br /></div>*****<br /><br />Good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />These are the addresses directly of some good ones; DNS & NTP & PTP 2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b 142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111</div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-35812147901334074122022-08-14T05:54:00.010+02:002022-08-23T15:29:32.609+02:00SiMD Chiplet Fast compression & decompression (c)RS<h4 style="text-align: left;">SiMD Chiplet Fast compression & decompression (c)RS</h4><br />*<br />Subject: SiMD Compression / Decompression chip of 2mm on side of die Chiplet (c)RS<br /><br />Compression / Decompression chip of 2mm on side of die Chiplet (c)RS<br /><br />Additional CPU & APU Compression / Decompression chip of 2mm to<br />feature on chiplet console APU's this is planned so that the Chiplet<br />does not require modification to the console APU,<br /><br />Additionally to feature pin access Direct Discreet DMA for storage :<br /><br />https://www.youtube.com/watch?v=1GvUdPn5QLg<br /><br />*<div><br />Configuration of SiMD : Huffman & Compression : RS<br /><br />To pack the majority of textures to 47 bit, one presumes a familiarity with Huffman codecs & the chaotic wavelets these present...<br /><br />AVX256 Tasks x 4 = 64Bit<br />SiMD 16Bit x 2 = 32Bit / Alignment with AVX == x8<br />SiMD 32Bit x 2 = 64Bit / Alignment with AVX == x4<br /><br />Closest to 47 = 40Bit Op x 2 (2.5Oe) | 80Bit/2 | 2 op x (1.5Oe)<br /><br />So 40 Bit x2 parallel 6 Lanes<br /><br />So on operation terms of precision : <br />32Bit Satisfies HDR, <br />40Bit Very much satisfies HDR, <br /><br />16Bit satisfies JPG (basic)<br />64Bit satisfies LUT & Wide Gamut HDR Pro Rendering<br /><br />*<br />Drill texture & image format (with contrast & depth enhancement)<br /><br /><a href="https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing">https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing</a><br /><a href="https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing">https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing</a><br /><br />https://science.n-helix.com/2022/08/simd.html<br /><br />Research topic RS : <a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a> <a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby</a> <a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a> <a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a> <a href="https://is.gd/DisplaySourceCode">https://is.gd/DisplaySourceCode</a></div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">GPU acceleration process : Huffman (c)RS</h4><br />In the case of dictionary we create a cubic array: 16 parallel Integer cube, 32 SiMD,<br /><br />FPU is used to compress the core elliptical curve with SVM Matrixing in 3D to 5D for files of 8Mb,FPU is inherently good versus Crystalline structure, We use the SiMD for comparative matrix & byte swap similarity.<br /><br />It is always worth remembering that comparative operations are one of the most fundamental SiMD functions; But multiply, ADD & divide exist within SiMD,<br />Functional FPU code can always use arrays of SiMD to handle chaotic play in the field..<br /><br />A main example is in Huffman's the variance of a wavelet from the main path,<br />Routes though main wavelet types are handled by table (on the amiga for example) &or FPU!<br />Micro changes make SiMD viable; In the same principle as a Hive & her ants.<br /><br />Inherent expansion doubles the expected SiMD use; Ideally 2MB ram per cube<br />Taking advantage of a known quantity & precision we code-block by 16Bit to 128Bit segments.<br /><br />Self correction allows us to Cube Huffman Decode into blocks, we parallelize blocks,<br />To (additionally) handle error we block the original compression.<br /><br />"We also use fine-grained locking for the frequency dictionary, individually locking each key-value pair. Once the symbol codes have been determined, each symbol is replaced by its code, and all symbols; So are processed in parallel.<br /><br />Decompression is inherently sequential, and hence much harder to parallelize. In this case, we take advantage of the self-synchronizing property of Huffman coding, which allows us to start at an arbitrary point"<div><div><br />In order of SiMD<br /><a href="https://github.com/lemire/SIMDCompressionAndIntersection">https://github.com/lemire/SIMDCompressionAndIntersection</a><br /><a href="https://github.com/lemire/FastPFor">https://github.com/lemire/FastPFor</a></div><br />Huffmans still worth the money!</div><div>Principally an order & load+Vec <a href="https://github.com/jearmoo/parallel-data-compression">https://github.com/jearmoo/parallel-data-compression</a></div><div>Huffman source, Requires analysis <a href="https://github.com/catid/Zpng">https://github.com/catid/Zpng</a><br /><br />https://vignan.ac.in/pgr20/20ES011.pdf<br />https://bestofgithub.com/repo/Better-lossless-compression-than-PNG-with-a-simpler-algorithm<br /><br />ZPNG<br />faster than PNG and compresses better for photographic images. This compressor often takes less than 6% of the time of a PNG compressor<br />https://github.com/catid/Zpng<div>*<h4 style="text-align: left;">SiMD Chiplet Fast compression & decompression (c)RS</h4><br /><h4 style="text-align: left;">3 proposals</h4><br /><a href="https://is.gd/BTSource">https://is.gd/BTSource</a><br /><br />LZ77: <br />https://github.com/jearmoo/parallel-data-compression<br /><br />The FastPFOR C++ library : Fast integer compression : <br />https://github.com/lemire/FastPFor<br /><br />SIMDCompressionAndIntersection<br />C/C++ library for fast compression and intersection of lists of sorted integers using SIMD instructions : https://github.com/lemire/SIMDCompressionAndIntersection<br /><br />Compressor Improvements and LZSSE2 vs LZSSE8<br />http://conorstokes.github.io/compression/2016/02/24/compressor-improvements-and-lzsse2-vs-lzsse8<br />http://conorstokes.github.io/compression/2016/02/15/an-LZ-codec-designed-for-SSE-decompression<br /><br /><h4 style="text-align: left;">Compression Science Docs</h4><br />A General SIMD-based Approach to Accelerating Compression<br />Algorithms<br />https://arxiv.org/ftp/arxiv/papers/1502/1502.01916.pdf<br /><br />SIMD Compression and the Intersection of Sorted Integers<br />http://boytsov.info/pubs/simdcompressionarxiv.pdf<br /><br />Fast Integer Compression using SIMD Instructions<br />https://www.uni-mannheim.de/media/Einrichtungen/dws/Files_People/Profs/rgemulla/publications/schlegel10compression.pdf<br /><br />Fast integer compression using SIMD instructions<br />https://www.researchgate.net/publication/220706907_Fast_integer_compression_using_SIMD_instructions<br /><br />*****<div><h4 style="text-align: left;">The FastPFOR C++ library : Fast integer compression<br />Build Status Build Status Ubuntu-CI</h4><br />https://jearmoo.github.io/parallel-data-compression/<br /><br />GO<br /><br />https://github.com/zentures/encoding<br /><br />http://zhen.org/blog/benchmarking-integer-compression-in-go/<br /><br />https://github.com/golang/snappy<br /><br />The FastPFOR C++ library : Fast integer compression<br />Build Status Build Status Ubuntu-CI<br /><br />What is this?<br /><br />A research library with integer compression schemes. It is broadly applicable to the compression of arrays of 32-bit integers where most integers are small. The library seeks to exploit SIMD instructions (SSE) whenever possible.<br /><br />This library can decode at least 4 billions of compressed integers per second on most desktop or laptop processors. That is, it can decompress data at a rate of 15 GB/s. This is significantly faster than generic codecs like gzip, LZO, Snappy or LZ4.<br /><br />https://github.com/lemire/FastPFor<br /><br />https://github.com/lemire/FastPFor/archive/refs/tags/v0.1.8.zip<br /><br />https://github.com/lemire/FastPFor/archive/refs/tags/v0.1.8.tar.gz<br /><br />Java May have a use in JS ôo<br />https://github.com/lemire/JavaFastPFOR<br /><br />https://github.com/lemire/JavaFastPFOR/blob/master/benchmarkresults/benchmarkresults_icore7_10may2013.txt<br /><br />*****<br /><br /><h4 style="text-align: left;">SIMDCompressionAndIntersection</h4><br />C/C++ library for fast compression and intersection of lists of sorted integers using SIMD instructions : https://github.com/lemire/SIMDCompressionAndIntersection<br /><br />SIMDCompressionAndIntersection<br />Build Status Code Quality: Cpp<br /><br />As the name suggests, this is a C/C++ library for fast compression and intersection of lists of sorted integers using SIMD instructions. The library focuses on innovative techniques and very fast schemes, with particular attention to differential coding. It introduces new SIMD intersections schemes such as SIMD Galloping.<br /><br />This library can decode at least 4 billions of compressed integers per second on most desktop or laptop processors. That is, it can decompress data at a rate of 15 GB/s. This is significantly faster than generic codecs like gzip, LZO, Snappy or LZ4.<br /><br /><h4 style="text-align: left;">*****LZ77*****</h4>Principally an order & load+Vec https://github.com/jearmoo/parallel-data-compression</div><div><br />https://jearmoo.github.io/parallel-data-compression/<br /><br /><br />Summary of What We Completed<br /><br />We have written and optimized the sequential version of the Huffman encoding and decoding algorithms, and tested it. For the parallel CPU version of this, we were debating between SIMD intrinsics and ISPC, and OpenMP.<br /><br />However, Huffman coding compression and decompression doesn’t seem to have a workload that can appropriately use SIMD. This is because there is no elegant way of dealing with bits instead of bytes in SIMD. Moreover, different bytes compress to a different number of bits (there is no fixed mapping of input vector size to output vector size), which makes byte alignment in SIMD very difficult (for example, the compressed form for a random 4 byte input could range from 2 to 4 bytes). This is much worse for decompression, where resolving bit-level conflicts (where a specific encoding spreads over 2 bytes) is almost impossible and might actually result in the algorithm being slower than the sequential version. Therefore, we decided to focus on OpenMP.<br /><br />For compression, we first sort the array in parallel, to minimize number of concurrent updates to the shared frequency dictionary, reducing contention and false sharing. We also use fine-grained locking for the frequency dictionary, individually locking each key-value pair. Once the symbol codes have been determined, each symbol is replaced by its code, and all symbols are so processed in parallel.<br /><br />Decompression is inherently sequential, and hence much harder to parallelize. In this case, we take advantage of the self-synchronizing property of Huffman coding, which allows us to start at an arbitrary point in the encoded bits, and assume that at some point, the offset in bits will correct itself, resulting in the correct output thereafter.<br /><br />We read about the LZ77 algorithm and explored the different variants of the algorithm. We also explored different ways to parallelize LZ77. One naive approach is running the LZ77 algorithm along different segments of the data. This approach could output the same result as the sequential implementation if we use a fixed size sliding window and reread over some of the data. Another approach is the one outlined in Practical Parallel Lempel-Ziv Factorization which uses an unbounded sliding window and employs the use of prefix sums and segment trees to calculate the Lempel-Ziv factorization in parallel.<br /><br />Update on Deliverables<br /><br />Our sequential implementations are close to finished, and we have some idea of how to parallelize the algorithms. Our goal for the checkpoint was to have both of these parts finished, but we have not completely met the goal. We may pivot and work on parallelizing the compression and decompression of the Huffman coding algorithm and drop the LZ77 part of the project altogether.<br /><br />Our new goals:<br /><br />Parallelize the Huffman Coding compression.<br />Parallelize the Huffman Coding decompression or LZ77 compression<br /><br /><div>Hope to achieve:<br />Both parts of part 2 in our new goals.</div><br /><h4 style="text-align: left;">*****ZPNG</h4><br />Huffman source, Requires analysis https://github.com/catid/Zpng<br /><br />Small experimental lossless photographic image compression library with a C API and command-line interface.<br /><br />It's much faster than PNG and compresses better for photographic images. This compressor often takes less than 6% of the time of a PNG compressor and produces a file that is 66% of the size. It was written in just 500 lines of C code thanks to Facebook's Zstd library.<br /><br />The goal was to see if I could create a better lossless compressor than PNG in just one evening (a few hours) using Zstd and some past experience writing my GCIF library. Zstd is magical.<br /><br />I'm not expecting anyone else to use this, but feel free if you need some fast compression in just a few hundred lines of C code.<div><div><br /></div>**************************<br /><br /><h4 style="text-align: left;">Main interpolation references:</h4><br />Interpolation https://drive.google.com/file/d/1dn0mdYIHsbMsBaqVRIfFkZXJ4xcW_MOA/view?usp=sharing<br /><br />ICC & FRC https://drive.google.com/file/d/1vKZ5Vvuyaty5XiDQvc6LeSq6n1O3xsDl/view?usp=sharing<br /><br />FRC Calibration ><br /><br />FRC_FCPrP(tm):RS (Reference)<br /><br />https://drive.google.com/file/d/1hEU6D2nv03r3O_C-ZKR_kv6NBxcg1ddR/view?usp=sharing<br /><br />FRC & AA & Super Sampling (Reference)<br /><br />https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing<br /><br />Audio 3D Calibration<br /><br />https://drive.google.com/file/d/1-wz4VFZGP5Z-1lG0bEe1G2MRTXYIecNh/view?usp=sharing<br /><br />2: We use a reference pallet to get the best out of our LED; Such a reference pallet is:<br /><br />Rec709 Profile in effect : use today! https://is.gd/ColourGrading<br /><br />Rec709 <> Rec2020 ICC 4 Million Reference Colour Profile : https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing<br /><br />For Broadcasting, TV, Monitor & Camera https://is.gd/ICC_Rec2020_709<br /><br />ICC Colour Profiles for compatibility: https://drive.google.com/file/d/1sqTm9zuY89sp14Q36sTS2hySll40DilB/view?usp=sharing<br /><br />https://is.gd/BTSource<br /><br />Colour Profile Professionally<br /><br />https://displayhdr.org/guide/<br />https://www.microsoft.com/store/apps/9NN1GPN70NF3<br /><br />*Files*<br /><br />This one will suite Dedicated ARM Machine in body armour 'mental state' ARM Router & TV https://drive.google.com/file/d/102pycYOFpkD1Vqj_N910vennxxIzFh_f/view?usp=sharing<br /><br />Android & Linux ARM Processor configurations; routers & TV's upgrade files, Update & improve<br />https://drive.google.com/file/d/1JV7PaTPUmikzqgMIfNRXr4UkF2X9iZoq/<br /><br />Providence: https://www.virustotal.com/gui/file/0c999ccda99be1c9535ad72c38dc1947d014966e699d7a259c67f4df56ec4b92/<br />https://www.virustotal.com/gui/file/ff97d7da6a89d39f7c6c3711e0271f282127c75174977439a33d44a03d4d6c8e/<br /><br />Python Deep Learning: configurations<br /><br />AndroLinuxML : https://drive.google.com/file/d/1N92h-nHnzO5Vfq1rcJhkF952aZ1PPZGB/view?usp=sharing</div><div><br />Linux : https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing<br /><br />Windows : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing</div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-83926924326679993762022-06-10T06:15:00.026+02:002023-07-28T23:02:18.703+02:00JIT CompilerDriver & Firmware Integrated JIT Compiler (c)RS<div><br /></div><div>Driver & Firmware Integrated JIT Compiler - DPIC Display Protocol Indirect Compute 2022<br /><br />Presenting JIT for hardware interoperability & function : https://is.gd/DisplaySourceCode<br /><br />Integrated JIT Compiler directly into a Shader & OpenCL / Direct Compute Driver Ethernet Protocol Socket & IP<br /><br />To & from all devices though Firmware Central JIT Compute Compiler<br /><br />Computation tasks can be carried out by all installed Hardware & USB / Plugged devices:<br /><br />WebGPU<br />Python<br />JavaScript<br />WebCL, OpenCL & Direct Compute<br />JIT compiled maths<br /><br />Indirect Computation such as maths in Application : WebGPU, WebCL, OpenCL & Direct Compute.<br /><br />Utilising Computation is as simple as having a V8 WebGPU function available,<br /><br /><div>May be directly available from the GPU without accessing the CPU if SDK is directly supported in GPU RAM...<br /><br />So in the case of a TV BlueRay Player as an example; We may infact simply be able to integrate..<br /><br />HTTPS: WebGPU, WebCL, OpenCL & Direct Compute & Methods such as JIT compiled maths.<br /><br />The plan we use is to; Integrate JIT Compiler directly into a Shader & OpenCL / Direct Compute Driver Ethernet Protocol Socket & IP<br /><br />Computation tasks can be carried out by all installed Hardware & USB / Pluged devices,<br /><br />To & from all devices though Firmware Central JIT Compute Compiler</div><div><br /></div><div>*</div><div><br /></div>Kernel Method requires around 20Kb + Cache Kernel run on OpenCL &or Direct Compute,<br />Closest device runtime &or Operation infrastructure procedure call.<br /><br />In the case examples:<br /><br />Camera focus OpenCL Kernel Ofload<br />(Edge detect, No image : edges & 4pixels with gradient with jpg compression)<br /><br />Audio device with buffers OpenCL Kernel Ofload<br />(processing input is from CPU to Audio Device : Simple Objective Pre Processing case)<br /><br />SSD & HDD Firmware OpenCL Kernel Ofload<br />(Location & Write & Math proof of safe write &or read, Error correction)<br /><br />Printer OpenCL Kernel Ofload<br />In the case of the printer the postscript driver "Is NOT" installed in your router,<br />The router prints but has basic drivers,<br /><br />OpenCL Kernel Ofload (from printer),<br />Makes the task of processing a Postscript Font & Curl Angle print; Easy!<br /><br />If you have a USB Hub with processor,<br />The Postscript Instruction Set is processed as OpenCL Vector Print</div><div><br />*<div><br />DPIC Device Protocol Indirect Compute Hub<br /><br />Proposed HDMI/DisplayPort Hub (also GPU Processed)<br />Proposed USB Hub,<br />Proposed Bluetooth Hub,<br />Proposed WiFi Hub<br />Proposed Ethernet/Net Hub<br /><br />with <br />50Mhz to 800Mhz processor with Dynamic Eco settings<br />*</div><div><br />On the aspect of HDMI & DisplayPort HTTP Ethernet protocol - DPIC Display Protocol Indirect Compute 2022 (c)RS https://bit.ly/VESA_BT<br /><br />On the aspect of HDMI & DisplayPort HTTP Ethernet protocol; Several forms of Computation exist as possible for the equipment involved : Televisions, Monitors & GPU & CPU<br /><br />*<br /><br />(c)Rupert S https://bit.ly/VESA_BT<br /><br />Research topic RS : https://is.gd/Dot5CodecGPU https://is.gd/CodecDolby https://is.gd/CodecHDR_WCG https://is.gd/HPDigitalWavelet https://is.gd/DisplaySourceCode</div></div><br />*<br /><br />Example : JIT Optimise Dynamic code - DPIC Device Protocol Indirect Compute<br /><br />Audio/Video/GPU/CPU/Urt/USB/BT : hardware to slow or fast? trade Processor Resources : How? DCP:JIT<br /><br />Camera Focusing API for Web : Application,<br />Because Computers surely focus a camera better if we use DPIC : Device Compute<br />Processing JIT Compiler,<br />Then Latency is not the issue!<br /><br />Video & Audio can do with additional processing : How? DCP:JIT<br /><br />Monitor would be able to do so much more! With additional processing : How? DCP:JIT<br /><br />Kernel Method requires around 20Kb + Cache Kernel run on OpenCL &or Direct Compute,<br />Closest device runtime &or Operation infrastructure procedure call.<br /><br />Tier processing; Objectives: <br /><br />High quality process, <br />Performance, <br />Shared workload, <br />Appropriate Computing unit<br /><br />In the case examples:<br /><br />Camera focus OpenCL Kernel Ofload<br />(Edge detect, No image : edges & 4pixels with gradient with jpg compression)<br /><br />Audio device with buffers OpenCL Kernel Offload<br />(processing input is from CPU to Audio Device : Simple Objective Pre Processing case)<br /><br />SSD & HDD Firmware OpenCL Kernel Offload<br />(Location & Write & Math proof of safe write &or read, Error correction)<br /><br />Printer OpenCL Kernel Offload<br />In the case of the printer the postscript driver "Is NOT" installed in your router,<br />The router prints but has basic drivers,<br /><br />OpenCL Kernel Offload (from printer) > (from USBHub : Some) > (Router back to printer),<br />In an ideal situation the Kernel processes the next tier up; In this case Pro-USBHub; <br />Leaving the router process free but with a very high quality printing job done.<br /><br />Makes the task of processing a Postscript Font & Curl Angle print; Easy!<br /><br />If you have a USB Hub with processor,<br />The Postscript Instruction Set is processed as OpenCL Vector Print<br /><br />*<br />DPIC Device Protocol Indirect Compute Hub<br /><br />Proposed HDMI/DisplayPort Hub (also GPU Processed)<br />Proposed USB Hub,<br />Proposed Bluetooth Hub,<br />Proposed Wifi Hub<br />Proposed Ethernet/Net Hub<br /><br />with <br />50Mhz to 800Mhz processor with Dynamic Eco settings<br />*<div><br /></div><div><h4 style="text-align: left;">Inter-device JIT Compiler Kernels (c)RS</h4><br />JIT Compiler : Driver facing the Monitor is included with JIT Compiler Firmware<br />subjectively...<br /><br />For the JIT Compiler to be available add the JIT Compiler to the HDMI<br />& Displayport Driver, <br /><br />Facing from the Monitor/AUDIO/VIDEO/BUSS/URT <><br />GPU <> CPU<br /><br />USB & Bluetooth require both the USB, Dongle adapter <> BUSS/URT <> CPU/GPU...<br />To further connect Printers & other devices...<br /><br />Under the same principle the Lens of a camera operating under the mounting fixture requires a fast connection, <br />In order to utilize Infrared/UV/Laser & Light or DIODE Controlled fixtures that require special firmware downloaded kernels,<br /><br />These kernels are flexible & will speed up devices & assure top performance with:<br /><br />16Bit, 32Bit, 64Bit & Float Kernels<br /><br />Driving the monitor & Learning sharper graphics<br /><br /><a href="https://is.gd/BTSource">https://is.gd/BTSource</a></div><div><br /></div><div><a href="https://drive.google.com/file/d/1gjXZ_ZDpOoLl4X6CYaU6RDrVKVtMAjHI/view?usp=sharing">Technology Demonstration</a></div><br />Firstly, we need an OpenCL Kernel : PocCL :<br /><br />PoCL Source & Code<br /><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br /><br />MS-OpenCL<br /><a href="https://is.gd/MS_OpenCL">https://is.gd/MS_OpenCL<br /></a><div><a href="https://is.gd/OpenCL4X64">https://is.gd/OpenCL4X64</a></div><div><a href="https://is.gd/OpenCL4ARM">https://is.gd/OpenCL4ARM</a><br /><div><br /></div>Upscale DL<br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL</a><br /><br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a><br /><br />X86Features-Emu<br /><a href="https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing">https://drive.google.com/file/d/15vXBPLaU9W4ul7lmHZsw1dwVPe3lo-jK/view?usp=usp=sharing</a><br /><div><br /></div><div>*</div><div><div><br /><div><h4 style="text-align: left;">Code/JS/OpenCL/Machine Learning Processing Block Size Streamlining (c)RS</h4><br />Dataset AV1/VP9/MPEG/H265/H264 : case example<br />My personal observation is that decompression & compression performance relates to block size & cache<br /><br />SiMD 8xBlock x 8xBlock Cube : 32Bit | x 4 128Bit | x 8 256Bit | x 16 512Bit<br />Cache Size : 32Kb Code : Code has to be smaller inline than 32Kb! Can loop 4Kb x 14-1 for main code segment<br /><br /></div><div>Cache Size 64Kb Data : Read blocks & predicts need to streamline into 64Kb blocks in total,<br />4Kb Optimized Code Cache<br />4Kb Predict (across block for L2 Multidirectional)<br />16Bit Colour Compressed block 4x16Bit (work cache compressed : 54Kb<br />Lab Colour ICC L2 & block flow L2<br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a></div><div><br />*</div><div><br />Combining JIT PoCL with SiMD & Vector instruction optimisation we create a standard model of literally frame printed vectors : <br /><br />VecSR that directly draws a frame to our display's highest floating point math & vector processor instructions; lowering data costs in visual presentation & printing.<br /><br />(documents) JIT & OpenCL & Codec : <a href="https://is.gd/DisplaySourceCode">https://is.gd/DisplaySourceCode</a><br /><br />Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/<br /><br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />https://science.n-helix.com/2022/08/simd.html</div></div></div></div><div><br /></div>*****<br /><br />Good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />These are the addresses directly of some good ones; DNS & NTP & PTP 2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b 142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-148885290936088252022-04-01T07:43:00.070+02:002024-03-14T09:39:33.234+01:00VecSR - Vector Standard Render<h4 style="text-align: left;">VecSR - Vector Standard Render</h4><div><br /></div>VESA Standards : Vector Graphics, Boxes, Ellipses, Curves & Fonts : Consolas & other brilliant fonts : (c)RS<div><br /></div><div>Vector Compression VESA Standard Display protocol 3 : RS<br /><div><br />SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts</div><div><br /></div>*<br />VecSR (c)RS<br /><br />VecSR is the principle for SiMD to accomplish a 2D & 3D trace of Rays & Vectors,<br />Principally the technology can do a couple of things (and more):<br /><br />Vectorising the Instruction & Presentation functions<br /><br />Precisely upscale (presentation)<br />Save data bandwidth on connections for monitors & printers & mice; By 'Vectorising the Instruction'<br />Present fonts & vectors to infinity..<br />Present wavelets in their Ultimate Vector form..<br /><br />There is no limit to Precision & Cache; Because presentation can be 'Dynamic Cache' & Precision is upto the Bit Depth of the hardware presenting.<br /><br />32Bit, 16Bit SiMD presents 32Bit, 16Bit FP16b, So precision is not a problem; Vectors are presented full precision as we want.<br />*<div><br /></div>*<br />32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)<br />(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second</div><div><br /></div>Security Relevant Extensions<br />SVM : Elliptic Curves & Polynomial graphs & function<br />AES : Advanced Encryption Standard Functions<br />AVX : 32Bit to 256Bit parallel Vector Mathematics<br />FPU : IEEE Float Maths<br />F16b : 16Bit to 32Bit Standards Floats<br />RDTSCP : Very high precision time & stamp<br /><br />Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1<div><br /></div><div>a<br /> \__c<br /> |<br /> b<br />Now Matrix Vectors for vector rendering <a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><div><br /></div><div><br /></div><div>Photos & Performance <a href="https://is.gd/4447GamerWEBB">https://is.gd/4447GamerWEBB</a></div><div><br /></div><div><div><a href="https://youtu.be/dOTwq7lDh1g">https://youtu.be/dOTwq7lDh1g</a></div><div><a href="https://youtu.be/nPvUSTDJ45A">https://youtu.be/nPvUSTDJ45A</a></div><div><br /></div><div><br />Research topic RS : <a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a> <a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby</a> <a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a> <a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a> <a href="https://is.gd/DisplaySourceCode">https://is.gd/DisplaySourceCode</a></div><div><br /></div><div>VecSR Anticipated Quadratic Array : Font Rendering</div><a href="https://gpuopen.com/learn/mesh_shaders/mesh_shaders-font_and_vector_art_rendering_with_mesh_shaders/">https://gpuopen.com/learn/mesh_shaders/mesh_shaders-font_and_vector_art_rendering_with_mesh_shaders/</a><div><br /></div><div>*<br /><br /><h4 style="text-align: left;">OT-SVG Fonts & TT-SVG Obviously Rendered in Direct X 9+ & OpenGL 3+ Mode & Desktop Rendering modes</h4><br />Improve Console & TV & BIOS & General Animated Render<br /><br />Vector Compression VESA Standard Display protocol 3 : RS<br /><br />SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts<br />Improve Console & TV & BIOS & General Animated Render<br /><br />Vector Display Standards with low relative CPU Weight<br />SiMD Polygon Font Method Render<br /><br />Default option point scaling (the space) : Metadata Vector Fonts with Curl mathematical vector :<br /><br />16 Bit : SiMD 1 width<br />32 Bit : SiMD Double Width<br /><br />High precision for AVX 32Bit to 256Bit width precision.<br /><br />Vectoring with SiMD allows traditional CPU mastered VESA Emulation desktops & safe mode to be super fast & displays to conform to VESA render standards with little effort & a 1MB Table ROM.<br /><br />Though the VESA & HDMI & DisplayPort standards Facilitates direct low bandwidth transport of and transformation of 3D & 2D graphics & fonts into directly Rendered Super High Fidelity SiMD & AVX Rendering Vector<br /><br />Display Standards Vector Render : DSVR-SiMD Can and will be directly rendered to a Surface for visual element : SfVE-Vec<br /><br />As such transport of Vectors & transformation onto display (Monitor, 3D Unit, Render, TV, & Though HDMI, PCI Port & DP & RAM)<br /><br />Directly resolve The total graphics pipeline into high quality output or input & allow communication of almost infinite Floating point values for all rendered 3D & 2D Elements on a given surface (RAM Render Page or Surface)<br /><br />In high precision that is almost unbeatable & yet consumes many levels less RAM & Transport Protocol bandwidth,<br /><br />Furthermore can also render Vector 3D & 2D Audio & other elements though Vector 'Fonting' Systems, Examples exist : 3D Wave Tables, Harmonic reproduction units for example Yamaha and Casio keyboards.<br /><br /><h4 style="text-align: left;">RGBA Composite Layer X-OR</h4><br />RGBA Can simply be the shape printed onto alpha layer; Wide Transparency effect.<br />RGB-Supposition is X-OR Shape on mapping block or cube or curve & shape; Due to Alpha Alias smooth blending is achieved.<br /><br />*<br /><br />Furthermore can also render Vector 3D & 2D Audio & other elements though Vector 'Fonting' Systems, Examples exist : 3D Wave Tables, Harmonic reproduction units for example Yamaha and Casio keyboards.<br /><br />Personally QFT is a much more pleasurable experience than VRR at 2xFPS+<br />Stable FPS & X-OR Partial Frame Retention saving on compression.<br /><br />"QFT a Zero compression or low level compression version of DSC<br />1.2bc<br /><br />X-OR Frame Buffer Compression & Blank Space Compression:<br />Vector Compression VESA Standard Display protocol 3"<br /><br />"QFT transports each frame at a higher rate to decrease “display<br />latency”, which is the amount of time between a frame being ready for<br />transport in the GPU and that frame being completely displayed. This<br />latency is the sum of the transport time through the source’s output<br />circuits, the transport time across the interface, the processing of<br />the video data in the display, and the painting of the screen with the<br />new data. This overall latency affects the responsiveness of games:<br />how long it appears between a button is pressed to the time at which<br />the resultant action is observed on the screen.<br /><br />While there are a lot of variables in this equation, not many are<br />adjustable from an HDMI specification perspective. QFT operates on the<br />transport portion of this equation by reducing the time it takes to<br />send only the active video across the cable. This results in reduced<br />display latency and increased responsiveness."</div><div><br />*<br /><br />(c)Rupert S</div><div><br /></div><h4 style="text-align: left;">(QT_SECC) ECC Temporal Tick for low energy devices & computer systems : RS</h4><br />(including GPU & RAM & Fast Storage),<br />Fast & high performance Elliptic Curves 8Bit to 128Bit<br /><br />Ideal standards of 16Bit Elliptic curves for Audio, Video, 3D Texture & Edge shaping...<br />As described here we create edges & cubes & fills & Obviously Elliptic Curves!<br /><br />We can shape digital audio directly; But also Video & Textures; Any shape that matches our description..<br />Any dream involving a precisely defined maths object that is a shape vector.<br /><br />This is not just a security device.<br /><br />RS<div><br /></div><div><h4 style="text-align: left;">Direct Rendering Matrix Vectors (c)RS</h4><br />a<br /> \__c<br /> |<br /> b<br />Now Matrix Vectors for vector rendering https://science.n-helix.com/2023/06/map.html<br /><br />DRMV Direct Surface Draw : Laser Printers, Screen, GPU, CPU & Applications of DirectX, Vulkan & OpenCL & Direct Compute HTML5 & JS Buffer<br /><br />With SiMD & Neon & AVX Features common to CPU & GPU, We can directly compose Vectors & Texture compose directly to the screen..<br /><br />Using Matrix Formula Maths : a, b, c, 3D render; We are not simply limited to enhanced eliptic curve & cubic functions..<br /><br />Optimised Eliptoid, Elliptic & Eccentric cuboid functions significantly improve a VESA Certified Render,<br /><br />QNON, Ellipto-centric force physics & dimensional realities; Become a Vector Render Reality Matrix : <br /><br />Holograms & Vector Drawing with SiMD, AVX, Matrix Units & FPU or Integers with RollINT.<br /><br />We can draw Squares, Cubes, Curves, Ovoids, Ellipsoids, Shapes & Voxels & Tixels directly to any renderable surface; Including VESA Approved Monitor standards to VecSR Standards..<br /><br />Directly from any available FPU, SiMD, Float or Integer unit.. Directly to any Video & Audio Buffer,<br />Therefore directly to Vector drawing surfaces such as: Laser Printers, Screen, GPU, CPU & Applications of DirectX, Vulkan & OpenCL & Direct Compute HTML5 & JS Buffer</div><div><br /></div>For reference to the functions of Curves, Elliptic & Cuboids that DRMV can run:<br />Architecture Fast Instructions for FMA <a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><div><br />Rupert S<br /><br />Reference operators</div><div><br /></div><div><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><br /><br />VecSR Anticipated Quadratic Array : Font Rendering<br /><a href="https://gpuopen.com/learn/mesh_shaders/mesh_shaders-font_and_vector_art_rendering_with_mesh_shaders/">https://gpuopen.com/learn/mesh_shaders/mesh_shaders-font_and_vector_art_rendering_with_mesh_shaders/</a></div><div><br /></div>Vector Font Render Sources{<br /><br /><a href="https://github.com/GreenLightning/gpu-font-rendering">https://github.com/GreenLightning/gpu-font-rendering</a><br /><br /><a href="https://github.com/azsn/gllabel">https://github.com/azsn/gllabel</a><br /><br /><a href="https://github.com/KeinR/Etermal/blob/master/README.md">https://github.com/KeinR/Etermal/blob/master/README.md</a><br /><br />};<div><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br /><a href="https://science.n-helix.com/2022/08/jit-dongle.html">https://science.n-helix.com/2022/08/jit-dongle.html</a><br /><br /><a href="https://science.n-helix.com/2022/06/jit-compiler.html">https://science.n-helix.com/2022/06/jit-compiler.html</a><br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a></div><div><br /></div><div><a href="https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/">https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/</a><br /><div><br /></div>*<br /><br /><h4 style="text-align: left;">BT-2.4G QT_SECC in context of VECSR</h4><br />Able to be used for Motion, Haptic, Video, Texture, Audio wavelet creation & use:</div><div><div><br /></div>The Wave pattern principle is in principle a content of pure colour curves, both depth & content of pixel,<br /><br />But also a means by which elliptic curves are created with great simplicity.. <br />So that singular hardware like F16 SiMD can truly create a master piece; Both Crypto & Dimensional 'art'</div><div><br />BT-2.4G Quartz Time Crystal Tick Simple Elliptic Curve to Support FIPS 128Bit on Unifier USB,<br /><br />Modulation to 16Bit& 32Bit & 64Bit & 128Bit allow for different types of SiMD & AVX<br />Allow for Android & Linux & Windows; ARM & X86 & GPU Processors<br /><br />Presented with a single tick \_/-\_/ Complex modulating Elliptic curves of 8Bit & 16Bit & 32Bit & 64Bit & 128Bit lengths,<br /><br />16Bit to 64Bit & 128Bit output curves; Through temporary ECC certificate..; Additionally ChaCha_Poly & AES Ciphers..<br /><br />Rupert S<br /><br />Principle: <br />Bluetooth dongle LE Protocol https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing<br /><br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/02/smart-compression.html<br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2021/11/ihmtes.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />*</div><div><br /><h4 style="text-align: left;">How JS & WebASM use a,b,i,c maths improves the total speed of application load & mouse control </h4><br />For reference to the functions of Curves, Elliptic & Cuboids that DRMV can run:<br />Architecture Fast Instructions for FMA <br /><br />https://science.n-helix.com/2023/06/map.html<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />FMA AVX Performance table: 2Flops per Cycle per FMA Unit<br />Architecture Fast Instructions for FMA<br /><br />Reference Tables https://www.uio.no/studier/emner/matnat/ifi/IN3200/v19/teaching-material/avx512.pdf<br /><br />Operators in C<br />● Arithmetic<br />a + b, a – b, a*b, a/b, a%b<br />● Bitwise <br />a | b, a & b, a ^ b, ~a<br />● Bit shift <br />a << b, a >> b (signed), a >> b (unsigned)<br />● Logical operators <br />a && b, a || b, !a<br />● Comparison operators<br />a == b, a != b, a < b, a <= b, a > b, a >= b<br />● Tertiary operator <br />x = a ? b : c<br />● Special functions:<br />sqrt(x), abs(x), fma(a,b,c), ceil(x), floor(x) <br /><br />Fast division for constant divisors<br /><br />Calculate r = a/b where b is a constant<br />With floating point we precompute (at compile time <br />or outside of the main loop) the inverse ib = 1.0/b.<br />r = ib*a<br />Floating point division with constant divisors <br />becomes multiplication<br />With integers the inverse is more complicated<br /> ib,n = get_magic_numbers(b);<br />r = ib*a >> n<br /><br />Integer division with constant divisors becomes<br />multiplication and a bit-shift<br /><br />Fast Division Examples<br />● x/3 = x*1431655766/2^32<br />27*1431655766/2^32 = 3<br />● x/1000 = x*274877907/2^38<br />10000*274877907/2^32 = 10<br />● x/314159 = x*895963435/2<br />7*314159*895963435/2^48 = 7<br /><br />Dividing integers by a power of two can be done with a bit shift which is very fast.<br /><br />RS</div><div><br /></div><div>High speed Per operation Cycle operations of D R² Pi<br /><br />An (A[diameter]*B²[Pi] : D * R² operation is 2 Cycles, this specialised Arc, Sin, Tan operation can be accomplished a couple of ways in a single cycle,<br /><br />Options table : D R² Pi<br /><br />Firstly by sideways memory load in lower Single Precision to double precision output in a SiMD<br /><br />You need to pre cache R²You can use the same value for R or for D &or both<br />You can pre cache all static D &or R, So you can vary either D or R & single cycle<br />You need to perform 2 operations , Diameter & R² & obviously they are relational!<br /><br />For examples:<br /><br />R = Atom Zink (standard size!) Cache D R<br />You move a compass but the needle is the same size! Cache D<br />You draw faces but the width is the same, Cache D<br />You draw faces but the Shape is the same but size is not! Cache R<br /><br />Rupert S</div><div><br />https://en.wikipedia.org/wiki/FMA_instruction_set<br />https://en.wikipedia.org/wiki/Advanced_Vector_Extensions<br />https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE)</div><div><br /></div><div>High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves<br />https://www.lasca.ic.unicamp.br/media/publications/FazHernandez_Armando_D.pdf<br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2022/04/vecsr.html</div><div><br />Updated JS Sourcery to be found at https://is.gd/LEDSource<br /><br />(Simple Install) Website Cache JS Updated 2021-11 (c)RS https://bit.ly/CacheJS <br />(Simple Install) Science & Research Node High Performance Computing Linux & Android https://is.gd/LinuxHPCNode<br /><br />Presenting JIT for hardware interoperability & function : https://is.gd/DisplaySourceCode<br /><br /><br />(Simple Install) Website Server Cache JS Updated 2021-11 (c)RS https://bit.ly/CacheJSm<br />(Simple Install) Website Server Cache JS Work Files Zip Updated 2021-11 (c)RS https://bit.ly/AppCacheJSZip<br /><br />https://npm.n-helix.com/bundles/<br /><br />Python Deep Learning:<br /><br />AndroLinuxML : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing<br />Linux : https://drive.google.com/file/d/1u64mj6vqWwq3hLfgt0rHis1Bvdx_o3vL/view?usp=sharing<br />Windows : https://drive.google.com/file/d/1dVJHPx9kdXxCg5272fPvnpgY8UtIq57p/view?usp=sharing<br /><br />Andro-linux libs : x86 & ARM : Learn<br />https://drive.google.com/drive/folders/1BRQOIK1eAUEMnTTGjsQ0h0g6jGLzWqZI<br /><br />good stuff for all networks nation wide, the software is certificate signed & verified<br />When it comes to pure security, We are grateful https://is.gd/SecurityHSM https://is.gd/WebPKI <br />TLS Optimised https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link<br />Ethernet Security https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link<br /><br />These are the addresses directly of some good ones; DNS & NTP & PTP 2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b 142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111<br /><br />*<br /><h4 style="text-align: left;">Drawing tools & functions that are the basis of our draw frame & font functions : Polygon maths</h4><br />Core Processor features : SVM, SiMD, FPU<br />Core tools : https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />Reference material for Drawing Elliptoids, Curves & Polygons<br /><br />SVM Elliptic Curve magic: <br />Fractal maths for improved efficiency & Combustion energy, Regard the photos & the FX8320E for details<br /><br />Effective Application of SVM Processor Elliptic Maths<br />https://is.gd/SVMefficiency<br /><br />Linear Bounding Volume Hierarchy & <br />Elliptic Bounding Volume Hierarchy for SVM Processor Feature: <br />SVM Can be emulated in SiMD pure 32Bit Single or 64Bit Double Precision, <br />& is for high complexity rendering such as non regular windows.<br /><br />https://www.phoronix.com/scan.php?page=news_item&px=RADV-LBVH-Lands<br /><br />SVM Can be emulated in SiMD pure 32Bit Single or 64Bit Double Precision..<br />Is useful for creating non Circle curves such as elliptoids & oblong wave boxes.<br /><br />In VSR & VSR Variable Lighting we can define spaces with eliptoids SVM,<br />Therefore shape around trees & grasses & animals &or people & Whales.<br /><br />https://www.youtube.com/watch?v=UojqzrPtR70<br /><br />(c)RS<br /><br />*<br /><br /><h4 style="text-align: left;">FFT or QFFT : Fast Fourier Transform</h4><br />FFT or QFFT is not only about audio; But also Video & 3D, Mouse & input/output devices (c)RS 2022<br /><br />FFT or QFFT is not only about audio; But also Video & 3D,<br />In fact FFT Fast Fourier Transforms are about any device such as a mouse that directly interacts with Waves,<br /><br />Such a device is the laser mouse & pointer; The primary reason is to use Noise reduction & path smoothing,<br />Primarily to create a 16Bit to 256Bit pure float with high compression or pack bit properties.<br /><br />Creating Sine-oidial curves & waves or SiMD, Float & packed integer/Float operations saves on bandwidth & increases messaging speed therefore!<br /><br />Both the input & output from Bluetooth, 2.4G & USB & Serial can in fact be reduced to mapped Curves & angles; While this introduces a small error factor & this is a factor that producers & driver developers need to work out & create error margins for.<br /><br />Creation & development of Ultra high precision Input & output for Humans, Robots & precision pointers; Requires a precise production FFT & to account for the fact surrounding the interactive motion of point A to point B; & In fact point C...<br /><br />Development continues & today's mission is to open minds about why we use FFT & noise reduction & Curve maps such as elliptic SVM & Bit Averaging Fast transforms for Center point Algebra & Math Tables & Graphs.<br /><br />Further study includes Raytracing & All Haptic motion; Sensors & Car engine Mechanics.<br /><br />(c)Rupert S<br /><br />*<br /><br />Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/<br /><br />https://science.n-helix.com/2016/04/3d-desktop-virtualization.html<br /><br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2019/06/kernel.html<br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br /><br />https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html<br /><br />https://bit.ly/VESA_BT<br /><br />https://science.n-helix.com/2023/03/path-trace.html<br /><br />https://science.n-helix.com/2023/02/smart-compression.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br /><br />https://science.n-helix.com/2022/08/simd.html</div><div><br /></div><div>*<br /><br /><h4 style="text-align: left;">Core Concepts of Direct Vector Render Frame Buffers & Cache</h4><br /><h4 style="text-align: left;">LHP_DSC_Xor : Screen Fast Buffer Access</h4><br />VESA Standard Ethernet Standard Frame Protocol for QFT, VRR & Low Latency High Performance Dynamic Compression XOR Frame Refresh : LLHP_DSCX : LHP_DSC_Xor<br /><br />QFT & VRR basically allow the TV to float a resolution refresh free from Frame Cache Memory Refresh (Refueling the Cache Buffer) ,<br />Basically the frame can be fetched from the Frame Cache (4MB to 64MB) Without interacting with the CPU<br /><br />This means a Fast Direct DMA Cache pull on frame to Screen & does not demand that the CPU need to perform this fast; Additionally the Frame comes without tearing or Frame pulls from the HDMI or display port VESA Ethernet Standard Frame Protocol.<br /><br />Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">Predicted Content Compression Frame Negotiation (c)RS</h4><br />Compression for HDMI & DP : VRR & QFT with frame content prediction & Minimal Adjust; X-OR Content replacement<br /><br />Compression Implicitly supported : STC, DXT, EAC & ATSC & DSC , Most of these compression forms are available in ARM, AMD, NVidia & Intel Hardware & therefore directly supported by us in creating the best frames & video; HDR WCG RGBA/X 4 Channel.<br /><br />Compression required for a display; Common details include using Compression as a last desperate measure to improve bandwidth for displays on High Definitions such as 4K on HDMI 2!<br /><br />My personal strategy is to implement compression that is transparent; Starting right at almost non,<br /><br />Frequently the problem with VRR & QFT is that a frame is sent or not sent...<br /><br />By utilizing Prediction in compression we force the prediction of an exact copy of present data,<br />We adjust the frame with X-OR & modify only a few details; Therefore we do not need to send a lot of data & can send more frames!<br /><br />*</div><div><br /></div><h4 style="text-align: left;">HDMI Input compression : Checker Board 2 frame compression with LZ Compression styles</h4><br />The application of GZIP Brotli ZSTD compression to screen data tunnels, Allows for 11K for connections on DisplayPort & HDMI, <br />With the simple switch to automatically lossless compression tunnels, <br /><br />The use of Checker Board 2 frame compression with LZ Compression styles allows most generic CPU to Deinterlace Double Scan data layers..<br /><br />Doubling effective resolutions.<br /><br /><h4 style="text-align: left;">QFT Quick Frame Transport in relation to HDMI Input compression:</h4><br />When you transmit serial frames with the same data compression comes in handy!<br />So enabling Brotli/ZSTD/GZip/DSC compression with Proofs of frame exact copy or slight modifications..<br /><br />Now transmit each part of the frame that is exactly the same as a compression copy, <br /><br />So in effect the frame is micro copied & each part is identified as part of the main frame repeat or new,<br /><br />In addition if the colour shifts but not the edges or shape; Most of the compression works in reference to HDMI Input compression,<br /><br />Brotli/ZSTD/GZip/DSC compression works fine in referencing colour shifting light or shape shifting but same light,<br /><br />Compression works fine.</div><div><br /></div><div>QFT with SSRTP is perfect for Web+ content refreshing 'Audio & Video' HDMI & VESA DisplayPort connection configurations.</div><div><br /></div><div>Aligned Byte Codes with 16bit compression codes ZSTD saves 80% of all data costs to content,<br />Small Byte dictionary compression saves 80% of transmit bandwidth.</div><div><br />(c)RS<div><br /></div>Bluetooth dongle LE Protocol <a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a><br /><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><div><br /></div><div>*</div><div><br /></div>The point of Brotli-G is that it minimises the network capacity needed for firmware updates or internet access, most devices use ethernet or wifi; however supporting Brotli-G is going to be fast!<br /><br />Additionally Brotli-G will allow compressed frames & sub-frames to be compressed flexibly,<br /><br />What DSC Allows in the form of sub-frames? However Brotli-G Allows sub-Frames...<br /><br />|FRAME FRAME|<br />|SF|SF|SF|SF|SF|SF|SF|<br /><br />As you can see the intention of sub-framing is to initiate a small section of the screen during the refresh cycles available to QFT & Fast Frame Transport,<br /><br />We thereby refresh only a small segment & can speed up the process!<br />Compression is required for efficient sending & we therefore will be using the suggested micro frame format : Brotli-G with Auto Encoding.<br /><br />Rupert S<div><br /></div>VESA + HDMI : Fast Pack Huffmans, Brotli, AutoEncoder https://is.gd/WaveletAutoEncoder https://github.com/GPUOpen-LibrariesAndSDKs/brotli_g_sdk<br /><br />https://is.gd/CJS_DictionarySort<br /><br />Python & JS Configurations<br />https://is.gd/DictionarySortJS<div><br /></div><div>*<br /><br /><h4 style="text-align: left;">Vector Compression VESA Standard Display protocol 3 +</h4>DSC : Zero compression or low level compression version of DSC<br />1.2bc<br /><br />Frame by Frame compression with vector prediction.<br /><br />Personally, QFT is a much more pleasurable experience than VRR at 2xFPS+<br />Stable FPS & X-OR Partial Frame Retention saving on compression.<br /><br />X-OR Frame Buffer Compression & Blank Space Compression:<br /><br />X-OR X=1 New Data & X=0 being not sent,<br />Therefore Masking the frame buffer,<br /><br />A Frame buffer needs a cleared aria; A curve or ellipsoid for example,<br />Draw the ellipsoid; This is the mask & can be in 3 levels:<br /><br />X-OR : Draw or not Draw Aria : Blitter XOR<br />AND : Draw 1 Value & The other : Blitter Additive<br />Variable Value Resistor : Draw 1 Value +- The other : Blitter + or - Modifier<br /><br />*</div><h4 style="text-align: left;">PCCFN</h4><div><br />The idea Behind PCCFN is to modify the frame by a smaller amount with low bandwidth & thereby increase frame rate by the following method:<br /><br />DSC Compression is used & Predict is enabled..<br />Predict is used to redisplay the frame on the screen; With no data needing to be sent : X-OR..<br />However Modifications are made to the frame by overruling parts of the Static frame with data..<br /><br />The effect is that only parts of the frame (Vector Motion Prediction); Are sent,<br /><br />Both bandwidth & speed are preserved & the same effect works from BFrames & Partial Full Frames.<br /><br />https://hdmi.org/spec21sub/variablerefreshrate<br />https://hdmi.org/spec21sub/quickframetransport<br /><br />*</div><div><br /><h4 style="text-align: left;">ITS_DHDR_VRR : Gaming & Desktop : HDR, Source-Based Tone Mapping (SBTM)</h4>High Efficiency DSC Screen Dynamic Shift State Screen blanking Replacement<br />Low Bandwidth Requirement for 40Hz to 240Hz+<br /><br />HDR, HDMI & Display-port Standards VESA 2022 : Independent Thread<br />Asymmetric Compute Frame Buffer Tree for HDR, Display & Compression<br />DSC : RS (c)Rupert S<br /><br />Composer Frame DSC is where we Compose a frame in the renderer, That<br />frame is for example the window task bar & another box for the<br />Explorer frame; The example is not OS Exclusive; Is an example.<br /><br />We implement DSC Display compression in the frame (smaller than the<br />display resolution or super sampled),<br /><br />Every piece of content in the Main Render Frame to HDMI & Display port<br />is computed independently with static content not being adjusted or<br />recompressed until needed,<br /><br />Our goal is to place Every frame or window in a Sub-Buffer Cache & Render to the main Frame Cache/Buffer,<br /><br />On completion of the frame at whatever FPS Refresh we desire for the Main Frame Buffer,<br />Effectively we Blitter &or Byte-swap our Window Frame Buffer to a location within the Main Frame buffer,<br /><br />The location of our window & our localised processing mean that content of each window & therefore process is independently proven to be the Same as the frame before (We X-OR),<br /><br />Therefore we Frame Predict (DSC) That a small portion of the main frame buffer has the same data,<br />We do not need to change a thing & so we do not need to utilize the processor to render it..<br /><br />However if data has changed; Then the change is localised to a single small render space in the main frame buffer & we therefore can refresh the screen faster & Frame Prediction (Like JPG & MPEG)<br /><br />Proves that we only need to inform the Screen (HDMI & DP Signal in our case);<br />That no additional date is sent; However any changes to the main frame buffer such as main view or video or text files or HTML Refresh will be Sent & Rendered,<br />Without Latency issues or large amounts of data being sent though the Cable..<br /><br />But we still render faster than recompressing a main frame buffer completely & in addition change what we wish per thread without the resulting processing Hanging or waiting on Data To arrive from a baton-pass.<br /><br />Our reasoning is that each frame is independent; Therefore we compose<br />in GPU or CPU & independently Compress the Frame within adjusted<br />context of the HDMI & DisplayPort,<br /><br />3 Frame Buffer; We can optimise the whole frame with Prediction<br />Compression if we wish,<br /><br />The Main goal : Independent Thread Render for Sub-Framing High Dynamic<br />Range with Independent Application Variable Refresh Rate :<br />ITS_DHDR_VRR.<br /><br />The main advantages are : Task bar is Low CPU Resource use but high<br />refresh rate; low data modification rate over a tiny area of the task<br />bar,<br /><br />The Game Window & the Frame (Mostly Square) are drawn with sub-pixel<br />precision on location..<br />But the frame that barely changes does not need recompression in DSC..<br /><br />The Game window does not need to compute or adjust content Compression<br />for the frame...<br /><br />Every piece of content in the Main Render Frame to HDMI & Display port<br />is computed independently with static content not being adjusted or<br />recompressed until needed.<br /><br />This works with the HDR, HDMI & Display-port Standards VESA<br /><br />(c)Rupert S<br /><br />*<br /><br /><h4 style="text-align: left;">Elliptic Curves & JPEG & MP4/ACC Presentation</h4><br />Ok so principally we want to create curves with ARC, Sin & Tan,<br />We can obviously present a curve in 16Bit or even 8Bit; So we can present a curve at the precision we have in the processor (such as 16Bit/32Bit SiMD),<br /><br />By presenting a curve at higher precision; We can upscale or super sample it,<br /><br />Super Sampling is principally presenting a curve at higher precision &or softening it with analogue/Digital filters..<br /><br />So by this example we present a case for elliptic curves presented within the scope of 16Bit or higher SiMD & Floats..<br /><br />The key idea is that we can use them!<br /><br />So we can present JPEG, ACC, MP4 as Elliptic curves for upscaling...<br />We can use Elliptic curves for encryption or presentation on GPU or other processors,<br />We can present curves to the pixels of a screen surface the same way; scaling them into higher precision.<br /><br />How well defined that curve is depends on our precision capacity; But we can still use Elliptic curves at any precision we have available.<br />So what do we want to use Elliptic curves to present ? Anything we need.<br /><br />RS</div><div><br />*<br /><br /><h4 style="text-align: left;">*Application of SiMD Polygon Font Method Render</h4>*3D Render method with Console input DEMO : RS<br /><br />3D Display access to correct display of fonts at angles in games & apps without Utilizing 3rd Axis maths on a simple Shape polygon Vector font or shape. (c)Rupert S<br /><br />3rd dimensional access with vector fonts by a simple method:<br /><br />Render text to virtual screen layer AKA a fully rendered monochrome, 2 colour or multi colour..<br /><br />Bitmap/Texture,<br /><br />Due to latency we have 3 frames ahead to render to bitmap DPT 3 / Dot 5<br /><br />Can be higher resolution & we can sub sample with closer view priority...<br /><br />We then rotate the texture on our output polygon & factor size differential.<br /><br />The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize<br /><br />Why ? Because rotating a polygon is harder than subtracting or adding width, Hight & direction to fully complex polygon Fonts & Polygon lines or curves...<br /><br />The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize.<br /><br />Such an example is my SiMD & MMX > AVX Image resizer,<br />Mipmapping fonts does tend to require over sized fonts..<br />For example Size 8 & 9 font output = Size 10 to 14 Font,<br /><br />TT-SVG & Open Fonts OT-SVG & Bitmap fonts compress well;<br />Mipmapped from 3 sizes larger & Cached as a DOT3/5 or NV12...<br />You have to save a cache; The Cache can be:<br /><br />Emulated or Dynamic Spacing (for difficult SETSPACE Console Font situations)<br />2 Tone, Grey, RGB, RGBA_8888, RGBA_1010102, RGBA_F16, P010, 444A, 888A or 101010A & <br />(DSC Precached Predicted Block Compression)tm<br /><br />The representation with alpha is mainly for smoothing & clean lines & is very quick to draw.<br /><br />Therefore we can Cache a Bitmap Version of any font,<br />We can of course Vector Render A font & directly to compressed surface rendering.<br /><br />The full process leads up to the terminal & how to optimize CON,<br />We can & will need to exceed capacities of any system & To improve them!<br /><br />*<br /><h4 style="text-align: left;">DSC Precached Predicted Block Compression</h4><br />We have a font for example with Alpha stored in the screen buffer & of a set size for BLITTING on top of a colour or image background,<br /><br />The alpha prevents the transposed X-OR Image or Font from having noise & creates ..a smooth sharp in-place modification of content.<br /><br />For our purpose X-OR can use Alpha instead of a single colour because this allows a very delicate smooth presentation on top of the background..<br /><br />Repeated application (& Probably Saving of, To save Resource usage); Can overlay graphic of Font Content.</div><div><br />*<br /><br />VecSR is really good for secondary loading of sprites & text; In these terms very good for pre loading on for example the X86, RISC, AMIGA & Famicom type devices,With appropriate loading into Sprite buffers or Emulated Secondaries (Special Animations) or Font Buffers.<br /><br />Font Drawing & Vector Render<br /><br />Although Large TT-SVG & OT-SVG fonts load well in 8MB Ram on the Amiga with Integer & Emulated Float (Library); Traditional Bitmap fonts work well in a Set Size & can resize well if cached & Interpolated &or Bilinear Anti-Alias & sharpened a tiny bit!<br /><br />presenting: Dev-Con-VectorE²<br />Fast/dev/CON 3DText & Audio Almost any CPU & GPU ''SiMD & Float/int"<br />Class VESA Console +<br /><br />With Console in VecSR you can 3DText & Audio,<br /><br />VecSR Firmware update 2022 For immediate implementation in all<br />operating systems & ROM's<br /><br />Potential is fast & useful.<br /><br />*<br />I will put this in print, My 3D & 2D Vector SiMD standard is the thing that i believe will save the most bandwidth on HDMI & DisplayPort Cables & Enable Vector 3D such as Laser Printers & Laser Screens, At the end of the day WE NEED VECTORS : RS<br />*<br /><br />https://science.n-helix.com/2022/04/vecsr.html<br /><br /><a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a></div></div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Web graphics & Games : RS : Deep Colour</h4>For the VESA & HDMI Display Standards & Web ICC Protocols</div><div><br />Integer 16Bit R, G, B FFFF,FFFF,FFFF & F16b R, G, B, A FFFFF, FFFFF,FFFFF, FFFF because F16b has 24Bit Integer & 8Bit float components.<br /><br />I have been thinking more about F16b; B Float with lower precision 8 bit remainder,<br />We can use it for HSL with Black to White levels (Light, Dark)<br /><br />5Bit per colour & light & dark as component 4 : R, G, B, A,<br /><br />Now before this i proposed F16 & F24 & F32 & F64, So what about the advantages of F16b?<br /><br />So most websites & games use Unsigned Integer F16; F16b is 24Bit Integer with 8 Bit sub pixel colours..<br />So the float component is mostly usable for games & major colour paint options in CSS Web page markup..<br /><br />But the Integer 24Bit allows a LOT of colour & we can use the float component in Super Resolution for precise colour additions & in Video as part of the Mpeg decompositions.<br /><br />Rupert S<br /><br />These are the main XRGB : RGBA Reference for X,X,X,X <br />https://drive.google.com/file/d/12vbEy_1e7UCB8nvN3hYg6Ama7HIXnjrF/view?usp=sharing<br />https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing<br /><br />Main interpolation references:<br /><br />Interpolation https://drive.google.com/file/d/1dn0mdYIHsbMsBaqVRIfFkZXJ4xcW_MOA/view?usp=sharing<br /><br />ICC & FRC https://drive.google.com/file/d/1vKZ5Vvuyaty5XiDQvc6LeSq6n1O3xsDl/view?usp=sharing<br /><br />FRC Calibration ><br />FRC_FCPrP(tm):RS (Reference)<br />https://drive.google.com/file/d/1hEU6D2nv03r3O_C-ZKR_kv6NBxcg1ddR/view?usp=sharing<br /><br />FRC & AA & Super Sampling (Reference)<br />https://drive.google.com/file/d/1AMR0-ftMQIIC2ONnPc_gTLN31zy-YX4d/view?usp=sharing<br />Audio 3D Calibration<br />https://drive.google.com/file/d/1-wz4VFZGP5Z-1lG0bEe1G2MRTXYIecNh/view?usp=sharing<br /><br />*<h4 style="text-align: left;">Camera & HDMI & DP Compression Modes</h4><br />Camera Modes<br />4:2:1 , 4:2:2 for the 4K Camera : HDR<br />4:4:4 for the faster 4K Camera : HDR<br />4:2:1 , 4:2:2 for the faster 8K Camera : HDR<br /><br />TV Modes<br /><br />HDMI 1.4 | 4:2:1 , 4:2:2 , 8bit, 10Bit for HD to HD+<br />HDMI 2 | 4:2:2 , 10Bit, 12Bit HDR 4K<br />HDMI 2.1 | 4:2:2, 10Bit, 12Bit, 16Bit 4K to 6K/8K..<br /><br />Example : 5120x2880x 60000Khz-GPixClock-DataRate GRefreshRate-38.365Hz-DBLScan 4:2:2 12Bit <div><br />If we had DSC compression modes installed in firmware ...<br /><br />BEST MODE : Can we upgrade this dynamically to HDMI 2.1 Standards with firmware & DSC Installed<br /><br />Question is can we implement BEST MODE for our Quality range & Also utilize DSC & Alternative Texture Mode Compression & Dynamic MAX Speed<br /><br />Yes We Can RS : DSC, ETC, ASTC & DTX Compression for display frames</div><div><br /></div><div>Yes for Studio recording 4:2:2 mode offers 2x the resolution & 4 extra Bit for the same money as 4:4:4 : 4:2:2 10Bit, 12Bit, 14Bit, 16Bit : Higher Dynamic Contrast & Colour<br /><br />Examples<br />https://youtu.be/VCdrB1b7wfc<br /><br />https://youtu.be/NIsoSA8uO04<br />https://youtu.be/Suc0OV_9TiA<br /><br />Render Folder https://bit.ly/VESA_BT<div><br /></div>*<br /><br />ASTC, EAC, DXT, PVRTC & DSC with firmware updated & need to be<br />included in the standards & firmware.<br /><br /><h4 style="text-align: left;">YCoCg-R</h4><br />https://en.wikipedia.org/wiki/YCoCg<br /><br />The screen content coding extensions of the HEVC standard and the VVC standard include an adaptive color transform within the residual coding process that corresponds with switching the coding of RGB video into the YCoCg-R domain.<br /><br />The use of YCoCg color space to encode RGB video in HEVC screen content coding found large coding gains for lossy video, but minimal gains when using YCoCg-R to losslessly encode video</div><div><br /></div><div>Yes for Studio recording 4:2:2 mode offers 2x the resolution & 4 extra Bit for the same money as 4:4:4 : 4:2:2 10Bit, 12Bit, 14Bit, 16Bit : Higher Dynamic Contrast & Colour<br /><br />HDMI 1.4 | 4:2:1 , 4:2:2 , 8bit, 10Bit for HD to HD+<br />HDMI 2 | 4:2:2 , 10Bit, 12Bit HDR 4K<br />HDMI 2.1 | 4:2:2, 10Bit, 12Bit, 16Bit 4K to 6K/8K..<br /><br />Example : 5120x2880x 60000Khz-GPixClock-DataRate<br />GRefreshRate-38.365Hz-DBLScan 4:2:2 12Bit<br /><br />https://www.cablematters.com/blog/DisplayPort/hdmi-2-1-vs-displayport-2-0<br /><br />https://www.cablematters.com/blog/DisplayPort/what-is-display-stream-compression<br /><br />https://en.wikipedia.org/wiki/YCoCg<br /><br />https://is.gd/Dot5CodecGPU<br /><br />*<div><br /></div><h4 style="text-align: left;">Things Task Shaders can (c)RS</h4><br />https://www.phoronix.com/scan.php?page=news_item&px=AMD-RDNA3-More-5.19-Tasks-RADV<br /><br />Task Shaders can be launched to implement Elliptic & Polygon MESH & thus create:<br /><br />Things Task Shaders can implement though MESH Shading & Polygons:<br /><br />(Direct Load of a preform MESH)<br /><br />Multi-Threaded+<br />Tundra & fauna<br />Polygon Fonts<br />Video Rendering Polygon interpretative interpolation..<br />Polygon MESH Conceptualised Vector Audio.<br />X-OR DSC Blank space removal<div>Polygon math & viewer & Viewer Angle based dynamic MESH Subtraction & Addition..<br />Close loop Tessellation</div><div><br />OpenCL Group micro tasks</div><div>Direct Compute/DirectedCL Group micro tasks<br />Multi-Threading<br />*<br /><br /> "Task shader is an optional stage that can run before a Mesh shader in a graphics pipeline. It's a compute-like stage whose primary output is the number of launched mesh shader workgroups (1 task shader workgroup can launch up to 2^22 mesh shader workgroups), and also has an optional payload output which is up to 16K bytes."</div></div></div><div><br /></div><div>**************</div><div><br /></div>Future minimal VSR : fm-VSR : RS<br /><br />Inference on any device with a C99 compiler<br />https://pypi.org/project/emlearn/<br /><br />to run without activating C99; Installs under Python 3.10+<br />https://github.com/emlearn/emlearn-micropython<br />https://github.com/emlearn/emlearn-micropython/releases<br />git clone https://github.com/emlearn/emlearn-micropython<br /><br />With EmLearn you can compile really tight models of tensors & random forest & Gaussian Matrix,<br />These are very good for: <br /><br />A1: Anti-Aliasing ( Gaussian, Tensor error diffusion, forested Random spread )<br />A2: sharpening & Shaping ( Tensor Edge detect with enhance, Gaussian estimation & line fill, Random forest A to B to D: E to B to F X + )<br />A3: Line & Curve estimation fills & Tessellation ( forested Random spread (Dither fills) & A1 & A2 & Differentiation in 3D Space : 1:2:3{ A B C : E B F }<br />A4: HDR & WCG, Combinations of dithering in colour space & light/Shadow differentiation in 3D Space : 1:2:3{ A B C : E B F }<br /><br /><a href="https://science.n-helix.com/2019/06/vulkan-stack.html">https://science.n-helix.com/2019/06/vulkan-stack.html</a><br /><br />VSR <a href="https://drive.google.com/file/d/1hewfYqLmY0z-Am800LMR-6H-P5J0Sr0N/view?usp=drive_link">https://drive.google.com/file/d/1hewfYqLmY0z-Am800LMR-6H-P5J0Sr0N/view?usp=drive_link</a><br /><br />VecSR <a href="https://drive.google.com/file/d/1WDvpD9a6TttMTmIz_sRYWaQT3RExBuSq/view?usp=drive_link">https://drive.google.com/file/d/1WDvpD9a6TttMTmIz_sRYWaQT3RExBuSq/view?usp=drive_link</a><br /><br /><a href="https://science.n-helix.com/2022/10/ml.html">https://science.n-helix.com/2022/10/ml.html</a><br /><br /><a href="https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html">https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html</a><br /><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><br /><br /><a href="https://science.n-helix.com/2016/04/3d-desktop-virtualization.html">https://science.n-helix.com/2016/04/3d-desktop-virtualization.html</a><br /><br /><a href="https://science.n-helix.com/2022/09/audio-presentation-play.html">https://science.n-helix.com/2022/09/audio-presentation-play.html</a><br /><br />Innate Compression, Decompression<br /><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br /><br />ML tensor + ONNX Learner libraries & files<br />Model examples in models folder<br /><br /><a href="https://is.gd/DictionarySortJS">https://is.gd/DictionarySortJS</a><br /><a href="https://is.gd/UpscaleWinDL">https://is.gd/UpscaleWinDL</a><br /><a href="https://is.gd/HPC_HIP_CUDA">https://is.gd/HPC_HIP_CUDA</a><div><br /></div><div><a href="https://is.gd/UpscalerUSB_ROM">https://is.gd/UpscalerUSB_ROM</a><br /><br /><a href="https://is.gd/OpenStreamingCodecs">https://is.gd/OpenStreamingCodecs</a><br /><br /><a href="https://drive.google.com/file/d/1li5MDf5FFPMEdpsgX6OEpn79aWZE19PW/view?usp=drive_link">https://drive.google.com/file/d/1li5MDf5FFPMEdpsgX6OEpn79aWZE19PW/view?usp=drive_link</a><br /><a href="https://is.gd/HuffBrotliAE">https://is.gd/HuffBrotliAE</a></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-84783830081717193802022-03-25T05:42:00.131+01:002023-12-01T01:21:52.602+01:00ICE-SSRTP GEA Replacement 2022 + (c)RS<h4 style="text-align: left;">ICE-SSRTP GEA Replacement 2022 + (c)RS</h4><div><br /></div><div>"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension<br />of GEA-1 with a higher amount of processing, and apparently not<br />weakened) are bit-oriented stream ciphers."</div><div><br /></div><div>GEA-2 > GEA-3 is therefor 64Bit Safe (Mobile calls) & 128Bit Safe (Reasonable security)</div><div>SHA2, SHA3therefor 128Bit Safe (Reasonable security Mobile) ++</div><div>AES & PolyChaCha both provide a premise of 128Bit++</div><div><br /></div><div>So by reason alone GEA has a place in our hearts.</div><div><br /></div>*<br /><br />ICE-SSRTP GEA Replacement 2022 + (c)RS <a href="https://is.gd/CryptographicProves">https://is.gd/CryptographicProves</a><br /><br />ICE-SSRTP constitutes 2 parts:<br /><br />The nonce: Time Value Inverted Nonce Packet: Obfuscation<br />The Main Cypher: AES, CHACHA20-POLY1305, GEA, 3DES & Other RTP Classifications<br /><br />*<br />In the case of Audio & Video; The Nonce is transmitted per frame group & displaces the content in the correct manner.<br />In the case of Data; Per group of packets.<br />*<div><br /><h4 style="text-align: left;">ICE-SSRTP : Network Protocol</h4><br />Main Cypher Package is a recommended Cypher; for example AES, Aria, Clefia & hardware Decrypted & Encrypted where possible,<br /><br />The containment is a Tunnel; Such as maintained by a video streaming service & GSM voice call (on reception of call & Arrangement of reception),<br /><br />The tunnel is a security certificates main job & is from source to end & routed,<br />Normally 128Bit to 512Bit RSA,EEC: AES, GEA, ARIA, CLEFIA<br /><br />Nonces are used for Identification & Verification, Special perposes & Small packet carrying (with me)<br />Nonces can arrange data & offer order garentees under routing protocols.<br /><br />Cases of nonce Encryption:<br /><br />Ideally due to internet traffic protocols (examples):<br />NTP 73bits, DNS 53Bits, Rout Mapping 50bits to 370bits estimated.<br /><br />due to these main protocols being small they almost exclusively advise use as nonce encryption; most probably 64bit enclosed in a tunnel,<br /><br />To & From the DNS & NTP if used regularly & due to NTP being specialised low traffic workload in most cases & DNS being regular traffic...<br /><br />Containment on encrypted tunnel is recommended in the case of main traffic & therefore,<br />Can use 64Bit EEC NONCE & because larger encryption blocks are not recommended & they clog the internet with larger bandwidth requirements,<br /><br />We can use 64Bit Ciphers with packets like DNS & With NTP (A Single QUICC protocol delivery with a EEC/RSA Delivery)<br />*<h4 style="text-align: left;">Nonce ICE-SSRTP:</h4><div><h4 style="text-align: left;">Time Value Inverted ICE-SSRTP (c)Rupert S</h4><div>The Nonce Variable</div><div><br />Needed content list<br /><br />Time inverted : Value T:<br /><br />Consisting of T(time) Tick(How many seconds),<br />Variable Inversion of content though FFT & Variable reversal of nonce & main Enciphered package<br /><br />Encryption methods:<br /><br />Bit length Nonce : 16Bit & 32Bit (SiMD decrypt)<br />Bit length Main Encryption Packet : 32Bit, 48Bit, 64Bit (SiMD decrypt)<br />Bit length Main Encryption Packet H : 64Bit, 96Bit, 128Bit (TPM/Security unit/SiMD decrypt)<br /><br />Methods of obfuscation:<br /><br />Packet swap (order)<br />Inversion (Data & band, Data Band order(High/Low)<br />Time Variable addition to Nonce &or Data<br /><br />Compression of packet with nonce decompression list: BZip, GZip, LHZ<br /><br />Main Core Accelerated Encryption Blocks:<br /><br />GEA (all version) & bit depth<br />CHACHA20-POLY1305<br />AES<br />GCM : CCM : CBC<br /><br />Value T : Nonce { Packet A : Packet B : Packet C } T = Inversion of 1 = { Nonce : Packet Order : Content }<br />Value of Nonce = { Noise Removal (wavelet) : Bit Addition : Byte Order }<br /><br />*****<br /><br /><h4 style="text-align: left;">Nonce reasoning : Dual Cypher : RS</h4>Larger packets (Hardware Decrypt), Smaller Encrypted nonce (CPU Processed)<br /><br />By the nonce we can therefor obfuscate the content of the Cryptic packet<br /><br />For examples:<br /><br />Nonce = Elliptic Noise<br />Packets are noisy<br /><br />Nonce = Swap<br />Packets are swapped in order<br /><br />Nonce = Bit addition / Byte swap<br />We do maths on the solved packets<br /><br />Nonce = Banding arrangements<br />We swap bands in the Audio & Video Data<br /><br />Nonce = Inversion<br />We invert the packets<br />before or after processing<div><br /></div><div>*<br /><br /><h4 style="text-align: left;">Main Cypher Package : ICE-SSRTP</h4><br />The Main Cypher: AES, CHACHA20-POLY1305, GEA, 3DES & Other RTP Classifications<br /><br />Encryption methods:<br /><br />Bit length Nonce : 16Bit & 32Bit (SiMD decrypt)<br />Bit length Main Encryption Packet : 32Bit, 48Bit, 64Bit (SiMD decrypt)<br />Bit length Main Encryption Packet H : 64Bit, 96Bit, 128Bit (TPM/Security unit/SiMD decrypt)<br /><br />Refer to Nonce ICE-SSRTP for packet dual Decryption/Encryption</div><br />Main Cipher Package is a recommended Cipher; for example AES, Aria, Clefia & hardware Decrypted & Encrypted where possible,<br /><br />The containment is a Tunnel; Such as maintained by a video streaming service & GSM voice call (on reception of call & Arrangement of reception),<br /><br />The tunnel is a security certificates main job & is from source to end & routed,<br />Normally 128Bit to 512Bit RSA,EEC: AES, GEA, ARIA, CLEFIA<br /><br />Nonce are used for Identification & Verification, Special purposes & Small packet carrying (with me)<br />Nonce can arrange data & offer order guarantees under routing protocols.<br /><br />*<br /><h4 style="text-align: left;">ICE-SSRTP Block Compressed Encipher</h4><br />ICE-SSRTP Encryption uses 2 Attributes & on the whole compression does not affect security of the Encipher.<br /><br />Nonce 16Bit/32Bit AES/GEA<br />Compression header (Encrypted)<br />Main Block (Block compressed with header & then lightly Encipher) (*3 or 4)<br /><br />The header keeps the Data compressed a secret & is useful for EXE & DLL because headers auto load exe's in the right order.</div><div><br /></div><div>Websites intend to send files on webpages so the main header is pre-planed..<br />So compressing the entire file is a lot more compressed; However you can compress chunks of 32KB/16KB/8KB/4KB/1KB..<br />You can go larger but the web packet size is the main container unit size.<br /><br />Header Compression examples:<br /><br />User interaction, 4KB or 1KB to be fast<br /><br />A small JS, Single header<br />Large JS, 16KB * 8<br />Picture or video & Audio, 16KB or 8KB chunks because wavelet size is 16x16 or 8x8</div><div><br /><div>Refer to Code-Speed & ICE-SSRTP</div><br />*</div><br /><h4 style="text-align: left;">Correct Time : EEC Elliptic & Nonce timer function:</h4><br />"The thing about random unique nonce with :dev/rng is that verifying<br />the nonce's uniqueness is an issue, with SSRTP nonce, Time intrinsics<br />allow only one play time https://datatracker.ietf.org/doc/rfc8954/ <br /><br />So what about if they have a reset phone & have not got the correct time ? mine wouldn't do NTP until i set it to pools.ntp.org, the telephone network would not change the time!"<br /><br />So the nonce may need a seconds from arrival timer; So that it is from the time it arrives (in your terms) & additionally a sent and arrival time so that when you get the correct time; It still works!<br /><br />In essence TLS & OSCP need a time from arrival (to verify link/Security CRT), It does not matter if that NTP timer is off by 5 Minutes...<br /><br />You can use the Time related EEC Elliptic curve & as long as it is timed from arrival & sends back a sample with a from time & until...<br /><br />That EEC Elliptic & Nonce will work.<br /><br />RS</div><div><br /><div>*</div><div><h4 style="text-align: left;">TLS key sharing agreement : RS</h4><br />I have regarded the tls key sharing agreement & it occurs to me that all modes may be improved with combination of a Nonce-PSK-Type-Key,<br /><br />For example held by the verifying certificate agency such as lets encrypt & SafeSSL & Cloudflare,<br /><br />Submitting a lightly cyphered PSK Key would take milliseconds & consume only 10000th of a second on GB/S Ethernet & therefor be unnoticeable and thus secure for the initiation encounter,<br /><br />So the proposal is TLS combine an additional initiation:<br /><br />Changing Nonce:PSK (from secure source)<br />+ verification<br />TLS Main initiation : ECDHE FFDHE DHE P256>P384 etcetera (under PSK)<br /><br />Key exchange > Final EEC Key with variable updates,<br /><br />So PSK can find a use that does not involve directly divulging the PSK to over use & secures the PSK by hour & variance.<br /><br />PSK<br /><a href="https://datatracker.ietf.org/doc/rfc9258/">https://datatracker.ietf.org/doc/rfc9258/</a><br /><a href="https://datatracker.ietf.org/group/tls/about/">https://datatracker.ietf.org/group/tls/about/</a><br /><br />(c)Rupert S</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">PSK AnonyCRT (c)RS</h4><br />PSK & AnonySecureCERT & TPM Client CRT & Anonymous Identity Email/Site Cert Identity (Replace PSK with one of them)<br /><br />PSK is usable for initial Key exchange if the PSK ID is loaded from the certificate provider, The cloud Provider or the Source Server; If the initial PSK is for example 8 Characters sent compressed & encoded with an Open EEC Certificate that the Browser or application uses....<br /><br />One may be thinking; what the hell? Well the idea is to provide a list of PSK's with a time function &or a message count (so the next PSK can be loaded..<br /><br />The reasoning is, We can use the PSK from the Client/Server side to guarantee & Secure sent data,<br />So essentially if a PSK is regarded as an elliptic curve initiator code; We can use any EEC we like from a PSK,<br /><br />We can for example use a certificate-less TLS by initiating 2 PSK per round (segment of time),<br />We can check NTP Sync with Time Protocol on send & receive of PSK/CERT/EEC<br /><br />1 PSK is EEC Curve<br />2 PSK is CERT HASH (EEC, RSA, AES, PolySHA, GEA)<br /><br />This provides a time limited window to decode & anonymity.<br /><br />PSK <br />AnonySecureCERT <br />TPM Client CRT <br />Anonymous Identity Email/Site Cert<br /><br />The idea being the Server can verify the correct receiver of TDP / UDP / DNS / NTP & other internet protocols such as Ethernet routing<br /><br /><h4 style="text-align: left;">Subject: Re: [TLS] I-D Action: draft-ietf-tls-rfc8447bis-02.txt -<br />Space & Aviation & Shipping & GSM</h4><br />https://datatracker.ietf.org/doc/draft-mattsson-tls-psk-ke-dont-dont-dont/<br /><br />I would like to point out that :<br /><br />PSK_PSK could use Elliptic PSK for PSK1(encapsulation : EEC, AES, GCM)<br />& PSK as a certificate replacement (the PSK would have to be a<br />HASH:RSA, AES For example)<br /><br />There are two fundamental uses for PSK; Voyager is an example (NASA);<br />Where a long voyage in space does not allow a long range high latency<br />connection to verify certificate chain & Certificate verification is<br />not recommended (7Years)!<br /><br />Shipping Radio and GSM & Global positioning : Open PSK from space<br /><br />The use of Registered Certificates for these jobs helps; When making a<br />Sub-Certificate verify depends on reliable certificate verification &<br />distance counts in Aviation<br />(can work though but must not verify with an offsite server for secrecy)<br /><br />Static (Self updated by firmware) Certificates work for the ECDHE_CERT<br />pairing or the PSK_DHE/ECDHE (certificate) pairing, However<br />verification on first initiation is Local<br /><br />(c)Rupert S</div><div><br />*</div>Very usable /dev/rnd Random Ring : TRNG : GPU : CPU : Asics : Using Chaos Wavelet<br />(Usable as encryption archetype): Chaos:A:B:T:Pi:Arc:Sin:Tan<div><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><br />*<div><div><div><br /></div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a></div><div><br /></div><div><a href="https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/">https://gpuopen.com/learn/matrix-compendium/matrix-compendium-intro/</a><br /><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />Code Speed<br /><a href="https://science.n-helix.com/2022/08/simd.html">https://science.n-helix.com/2022/08/simd.html</a><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><br />Chaos<br /><a href="https://science.n-helix.com/2022/02/interrupt-entropy.html">https://science.n-helix.com/2022/02/interrupt-entropy.html</a><br /><a href="https://science.n-helix.com/2022/02/rdseed.html">https://science.n-helix.com/2022/02/rdseed.html</a><br /><a href="https://science.n-helix.com/2020/06/cryptoseed.html">https://science.n-helix.com/2020/06/cryptoseed.html</a></div><div><br /></div>sRTP Chaos Nonce: Certificate transactions; TLS & OCSP Security Protocols<br /><a href="https://datatracker.ietf.org/doc/rfc8954/">https://datatracker.ietf.org/doc/rfc8954/</a><div><br /></div>RSA-PSS<br />RSASSA-PSS is a probabilistic signature scheme (PSS) with appendix<br />RSAES-OAEP (Optimal Asymmetric Encryption Padding)<br /><br /><a href="https://www.cryptosys.net/pki/manpki/pki_rsaschemes.html">https://www.cryptosys.net/pki/manpki/pki_rsaschemes.html</a><br /><a href="https://www.rfc-editor.org/rfc/rfc8017">https://www.rfc-editor.org/rfc/rfc8017</a><br /><a href="https://www.rfc-editor.org/rfc/rfc5756">https://www.rfc-editor.org/rfc/rfc5756</a></div><div><br /></div><div>PSK</div>Pre-Shared Key Cipher Suites for TLS with SHA-256/384 and AES Galois Counter Mode<br /><a href="https://datatracker.ietf.org/doc/rfc5487/">https://datatracker.ietf.org/doc/rfc5487/</a></div><div><a href="https://datatracker.ietf.org/doc/rfc8442/">https://datatracker.ietf.org/doc/rfc8442/</a></div><div><a href="https://datatracker.ietf.org/doc/rfc9258/">https://datatracker.ietf.org/doc/rfc9258/</a></div><div><br />Nonce & Plaintext, Token & SequenceID (Bearing in mind that ICE-SSRTP Nonce is compatible)<br /><a href="https://www.ietf.org/id/draft-howard-gssapi-aead-01.txt">https://www.ietf.org/id/draft-howard-gssapi-aead-01.txt</a></div><div><br /></div>AES-GCM-SIV: Nonce Misuse-Resistant Authenticated Encryption<br /><a href="https://datatracker.ietf.org/doc/rfc8452/">https://datatracker.ietf.org/doc/rfc8452/</a></div><div><div><br /></div>Adding the nonce to GMAC makes GMAC's unique : ICE-ssRTP<br /><a href="https://www.zerotier.com/2019/09/04/aes-gmac-ctr-siv/">https://www.zerotier.com/2019/09/04/aes-gmac-ctr-siv/</a><br /><a href="https://www.rfc-editor.org/rfc/rfc5297#page-15">https://www.rfc-editor.org/rfc/rfc5297#page-15</a></div><div><br />AES-GCM SRTP<br /><a href="https://datatracker.ietf.org/doc/rfc7714/">https://datatracker.ietf.org/doc/rfc7714/</a><br />AES-CCM<br /><a href="https://datatracker.ietf.org/doc/rfc6655/">https://datatracker.ietf.org/doc/rfc6655/</a></div><div><br /></div><a href="https://docs.google.com/document/d/12oNEcgjAjQERMvATCVCWpoTxNU47NRUzxCK5g0FysTk/edit?usp=sharing">RTP-ICE</a><br />https://chromestatus.com/feature/6276032524976128</div><div>https://science.n-helix.com/2022/03/ice-ssrtp.html</div><div><br /></div><div>AES Based Cryptography of the 3G, 4G, 5G LTE Networks - Implement solutions to tackle security threats in Mobile Cloud Gaming<br /><a href="https://is.gd/TelecomsNetworkSecurity">https://is.gd/TelecomsNetworkSecurity</a><br /><a href="https://is.gd/FastElliptic">https://is.gd/FastElliptic</a></div><div><a href="https://is.gd/KeylessEdgeDelivery">https://is.gd/KeylessEdgeDelivery</a></div><div><a href="https://is.gd/DeviceSecurityAdvice">https://is.gd/DeviceSecurityAdvice</a></div><div><br /></div>General Security TLS 2023-10:<br />RSA_PSS (Ideal Win7+) SHA1 potential exclusion (not good for win7),<br />+2 Post Quantum Cypher exchanges,<br /><a href="https://chromestatus.com/features#algorithm">https://chromestatus.com/features#algorithm</a><div><br /></div>JS Security<br /><a href="https://is.gd/NaCL_LockDoor">https://is.gd/NaCL_LockDoor</a><br />(Simple Install) Website Server Cache JS Work Files Zip Updated 2021-11 (c)RS <a href="https://bit.ly/AppCacheJSZip">https://bit.ly/AppCacheJSZip</a><br /><a href="https://npm.n-helix.com/bundles/">https://npm.n-helix.com/bundles/</a><div><br /></div><div>Time-Based-ECC - RSMS Towards Reliable and Secure Metaverse Service Provision</div><div><a href="https://is.gd/MetaverseEdgeDelivery">https://is.gd/MetaverseEdgeDelivery</a><div><br /></div><div>Lightweight Cryptography</div><div><a href="https://www.cryptrec.go.jp/report/cryptrec-gl-2003-2016en.pdf">https://www.cryptrec.go.jp/report/cryptrec-gl-2003-2016en.pdf</a><br /><a href="https://www.scitepress.org/papers/2014/49006/49006.pdf">https://www.scitepress.org/papers/2014/49006/49006.pdf</a><br /><br />TLS 1.3 on Lightweight Crypto<br /><a href="https://eprint.iacr.org/2023/095.pdf">https://eprint.iacr.org/2023/095.pdf</a></div><div><br />Performance Evaluation Comparison LIGHTWEIGHT CIPHERS NIST LightWeight Cryptography Requirements<br /><a href="https://scholarworks.calstate.edu/downloads/k0698968b">https://scholarworks.calstate.edu/downloads/k0698968b</a></div><div><br /></div>GCM - Galois Field - Permuting Bits with GF2P8AFFINEQB<br />https://news.ycombinator.com/item?id=37630391<div><br /></div><div>Lattice Maths ECC-AES-Kyber</div><div><a href="https://www.redhat.com/en/blog/post-quantum-cryptography-lattice-based-cryptography">https://www.redhat.com/en/blog/post-quantum-cryptography-lattice-based-cryptography</a></div><div><br />Computation of Hilbert class polynomials and modular polynomials from super-singular elliptic curves<br /><a href="https://eprint.iacr.org/2023/064.pdf">https://eprint.iacr.org/2023/064.pdf</a></div><div><br /></div><div>Super-singular Elliptic Curves for ECDHE EEC PQC - Deuring for the People - Super-singular Elliptic Curves with Prescribed Endomorphism Ring in General Characteristic - 2023-106<br /><a href="https://eprint.iacr.org/2023/106.pdf">https://eprint.iacr.org/2023/106.pdf</a></div><div><br />The Security of ChaCha20-Poly1305 in the Multi-user Setting<br /><a href="https://eprint.iacr.org/2023/085.pdf">https://eprint.iacr.org/2023/085.pdf</a></div><div><br /></div><div>Verification ECDHE<br />ECDHE Grotto, framework & C++ library for space- & time-efficient -party piecewise polynomial 'i.e, spline' evaluation on secrets additively shared over, Grotto improves on the state-of-the-art approaches of DCF 2023-108<br /><a href="https://eprint.iacr.org/2023/108.pdf">https://eprint.iacr.org/2023/108.pdf</a></div><div><br /></div><div>High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves<br /><a href="https://www.lasca.ic.unicamp.br/media/publications/FazHernandez_Armando_D.pdf">https://www.lasca.ic.unicamp.br/media/publications/FazHernandez_Armando_D.pdf</a></div><div><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a></div><div><br /></div><div>Depending on SVE & AES-NI's Capacity to Dynamically accelerate TLS, We may have sufficient Lattice support even for Kyber! & other Lattice Encryption types.<br /><div><br /></div>AES-NI Compatible Ciphers : AES, ARIA, CLEFIA<br /><a href="https://datatracker.ietf.org/doc/html/draft-irtf-cfrg-cipher-catalog-01#page-3">https://datatracker.ietf.org/doc/html/draft-irtf-cfrg-cipher-catalog-01#page-3</a><br /><br />CLEFIA : Large size table, Pure function<br /><a href="https://datatracker.ietf.org/doc/html/rfc6114">https://datatracker.ietf.org/doc/html/rfc6114</a><br /><br />ARIA : Random is a big+ to anonymity bit 128Bit's of data<br /><a href="https://datatracker.ietf.org/doc/html/rfc5794">https://datatracker.ietf.org/doc/html/rfc5794</a><br />ARIA is conformant<br /><a href="https://datatracker.ietf.org/doc/html/rfc6209">https://datatracker.ietf.org/doc/html/rfc6209</a><br />ARIA SRTP<br /><a href="https://datatracker.ietf.org/doc/html/rfc8269#page-14">https://datatracker.ietf.org/doc/html/rfc8269#page-14</a></div><div><br /></div><div>Post Quantum:<br />Verification of Correctness and Security Properties for CRYSTALS-KYBER<br /><a href="https://eprint.iacr.org/2023/087.pdf">https://eprint.iacr.org/2023/087.pdf</a><br /><br />Verification of the (1–δ)-Correctness Proof of CRYSTALS-KYBER with Number Theoretic Transform<br /><a href="https://eprint.iacr.org/2023/027.pdf">https://eprint.iacr.org/2023/027.pdf</a><br /><br />A Practical Template Attack on CRYSTALS-Dilithium<br /><a href="https://eprint.iacr.org/2023/050.pdf">https://eprint.iacr.org/2023/050.pdf</a></div><div><br /></div>AES-NI & SVE Matrix Acceleration<br />Kyber ML-KEM Module-Lattice-based Key-Encapsulation Mechanism Standard<br /><a href="https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.203.ipd.pdf">https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.203.ipd.pdf</a><br /><br />Dilithium ML-DSA Module-Lattice-Based Digital Signature Standard <br /><a href="https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.204.ipd.pdf">https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.204.ipd.pdf</a><br /><br />SHA2 Acceleration<br />SPHINCS+ SLH-DSA Stateless Hash-Based Digital Signature Standard<br /><a href="https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.205.ipd.pdf">https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.205.ipd.pdf</a><div><br /></div>Q: We would like to thank you for your additional cyphers<br /><a href="https://csrc.nist.gov/projects/pqc-dig-sig/round-1-additional-signatures">https://csrc.nist.gov/projects/pqc-dig-sig/round-1-additional-signatures</a><br /><a href="https://csrc.nist.gov/projects/pqc-dig-sig/standardization/call-for-proposals">https://csrc.nist.gov/projects/pqc-dig-sig/standardization/call-for-proposals</a><br /><br />Hail Kyber, Dilithium, Spincs & Falcon moving forward very nicely!<br /><a href="https://csrc.nist.gov/news/2023/three-draft-fips-for-post-quantum-cryptography">https://csrc.nist.gov/news/2023/three-draft-fips-for-post-quantum-cryptography</a><div><br /></div><div>NTRU, Kyber Hardware Acceleration - Gate-Level Masking of Streamlined NTRU Prime Decapsulation in Hardware 2023-105<br /><a href="https://eprint.iacr.org/2023/105.pdf">https://eprint.iacr.org/2023/105.pdf</a></div><div><br /></div>Isogeny : SIKE & SIDH & Elliptic Curves<br /><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br />Matrix Processors - Useful multiplication matrix maths in Isogeny creations - New proof systems and an OPRF from CSIDH<br /><a href="https://eprint.iacr.org/2023/1614.pdf">https://eprint.iacr.org/2023/1614.pdf</a></div><div><br /></div><div>Matrix Processors - Efficient Hardware Implementation of Elliptic-Curve Diffie–Hellman Ephemeral on Curve25519<br /><a href="https://www.mdpi.com/2079-9292/12/21/4480">https://www.mdpi.com/2079-9292/12/21/4480</a></div><div><br />(Simplification process) Improved algorithms for finding fixed-degree isogenies between supersingular elliptic curves<br /><a href="https://eprint.iacr.org/2023/1618.pdf">https://eprint.iacr.org/2023/1618.pdf</a><br /><br />Efficient ZK Compiler from SIMD Circuits to General Circuits<br /><a href="https://eprint.iacr.org/2023/1610.pdf">https://eprint.iacr.org/2023/1610.pdf</a><br /><br />FPGA Design - Complex reduction for Lattice Algorithms with The Number Theoretic Transform (NTT) like FFT<br /><a href="https://eprint.iacr.org/2023/1617.pdf">https://eprint.iacr.org/2023/1617.pdf</a><div><br /></div>ECH : Encrypted Client Hello SNI<br /><a href="https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/">https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/</a><br /><a href="https://blog.cloudflare.com/encrypted-client-hello/">https://blog.cloudflare.com/encrypted-client-hello/</a><br /><br />Post-Q ECH ECC<br /><a href="https://datatracker.ietf.org/doc/html/rfc9180">https://datatracker.ietf.org/doc/html/rfc9180</a><br /><div><br /></div>VXEdDSA & XEdDSA & X25519 & X448<br /><a href="https://signal.org/docs/specifications/xeddsa/">https://signal.org/docs/specifications/xeddsa/</a><div><br /></div><div>PQXDH Key Agreement Protocol : <br />XEdDSA:{HASH SHA-256 or SHA-512 & curve25519 or curve448} & KEM Crystals-Kyber-1024<br /><a href="https://signal.org/docs/specifications/pqxdh/">https://signal.org/docs/specifications/pqxdh/</a><br /><br />X3DH XEdDSA:{HASH SHA-256 or SHA-512 & Curve X25519 or X448}<br /><a href="https://signal.org/docs/specifications/x3dh/">https://signal.org/docs/specifications/x3dh/</a></div><div><br /></div><div><div>Model & Create S-Box (AES & ARIA & CLEFIA S-Box Modelling)</div><div>AES & ARIA & CLEFIA S-Box Modelling - Advanced Crypto Algorithms - Modelling for Large S-boxes Oriented to Differential Probabilities and Linear Correlations (Long Paper) 2023-109</div><div><a href="https://eprint.iacr.org/2023/109.pdf">https://eprint.iacr.org/2023/109.pdf</a></div><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<div><br /></div>Compact TLS 1.3<br /><a href="https://datatracker.ietf.org/doc/draft-ietf-tls-ctls/">https://datatracker.ietf.org/doc/draft-ietf-tls-ctls/</a><br />DTLS 2023<br /><a href="https://datatracker.ietf.org/doc/draft-ietf-tsvwg-dtls-over-sctp-bis/">https://datatracker.ietf.org/doc/draft-ietf-tsvwg-dtls-over-sctp-bis/</a><div><div>TLS 1.2 <br /><a href="https://datatracker.ietf.org/doc/rfc5246/">https://datatracker.ietf.org/doc/rfc5246/</a><br /><br /><a href="https://datatracker.ietf.org/group/tls/about/">https://datatracker.ietf.org/group/tls/about/</a><br /><a href="https://blog.cloudflare.com/post-quantum-for-all/">https://blog.cloudflare.com/post-quantum-for-all/</a></div><div><br /></div><div>Network Time Protocol Version 4: Protocol and Algorithms Specification<br /><a href="https://datatracker.ietf.org/doc/rfc5905/">https://datatracker.ietf.org/doc/rfc5905/</a></div><div><br /></div><div><a href="https://science.n-helix.com/2022/01/ntp.html">https://science.n-helix.com/2022/01/ntp.html</a><br /><div><br /></div><div>Securing TLS</div><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM</a></div><div><a href="https://is.gd/WindowsSecureHSM_PKI">https://is.gd/WindowsSecureHSM_PKI</a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a><div><br /></div>Crypto Libraries<br /><a href="https://github.com/miracl/core">https://github.com/miracl/core</a><br /><a href="https://github.com/jedisct1/libsodium">https://github.com/jedisct1/libsodium</a><br /><br />About Circl library<br /><a href="https://github.com/cloudflare/circl">https://github.com/cloudflare/circl</a><br /><a href="https://blog.cloudflare.com/inside-geo-key-manager-v2/">https://blog.cloudflare.com/inside-geo-key-manager-v2/</a></div><div><br /></div><div>FPGA & ASIC Libraries<br /><a href="https://si2.org/open-cell-library/">https://si2.org/open-cell-library/</a><br /><br />JS Crypto Libraries<br />https://www.npmjs.com/package/tweetnacl<br />https://cure53.de/tweetnacl.pdf<br />https://www.npmjs.com/package/@stablelib/nacl<br />https://www.npmjs.com/package/@stablelib/ed25519<br />https://www.npmjs.com/package/libsodium<br />https://www.npmjs.com/package/js-nacl<br />https://www.npmjs.com/package/crypto-js<br />https://www.npmjs.com/package/source-map-explorer<br /><br />Official HSM Hardware<br /><br /><a href="https://www.nitrokey.com/products/nitrokeys">https://www.nitrokey.com/products/nitrokeys</a><br /><a href="https://www.nitrokey.com/files/doc/Nitrokey_HSM_factsheet.pdf">https://www.nitrokey.com/files/doc/Nitrokey_HSM_factsheet.pdf</a><br /><br /><a href="https://www.yubico.com/products/">https://www.yubico.com/products/</a><br /><a href="https://www.yubico.com/products/hardware-security-module/">https://www.yubico.com/products/hardware-security-module/</a><br /><a href="https://resources.yubico.com/53ZDUYE6/at/q4bsft-z2wi8-fo7aqg/YubiHSM2_Product_Brief.pdf?format=pdf">https://resources.yubico.com/53ZDUYE6/at/q4bsft-z2wi8-fo7aqg/YubiHSM2_Product_Brief.pdf?format=pdf</a><br /><a href="https://resources.yubico.com/53ZDUYE6/at/937nrcp925s6jhnxktpzhnfh/YubiHSM_2_Technical_Data_Sheet.pdf?format=pdf">https://resources.yubico.com/53ZDUYE6/at/937nrcp925s6jhnxktpzhnfh/YubiHSM_2_Technical_Data_Sheet.pdf?format=pdf</a><br /><br /><a href="https://www.nitrokey.com/products/nethsm">https://www.nitrokey.com/products/nethsm</a><br /><a href="https://github.com/Nitrokey/nitrokey-app/releases/tag/v1.4">https://github.com/Nitrokey/nitrokey-app/releases/tag/v1.4</a><br /><br />Officially Software 4 HSM<br /><br /><a href="https://is.gd/SecurityHSM">https://is.gd/SecurityHSM </a><br /><a href="https://is.gd/WindowsSecureHSM_PKI">https://is.gd/WindowsSecureHSM_PKI </a><br /><a href="https://is.gd/WebPKI">https://is.gd/WebPKI</a> </div><div><br /></div><div>TLS Optimised<br /><a href="https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link">https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link</a></div><div><br />Ethernet Security<br /><a href="https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link">https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link</a><br /><br />(Simple Install) Website Server Cache JS Work Files Zip Updated 2021-11 (c)RS</div><div><a href="https://bit.ly/AppCacheJSZip">https://bit.ly/AppCacheJSZip</a></div><div><a href="https://npm.n-helix.com/bundles/">https://npm.n-helix.com/bundles/</a><div><br /></div>*<br /><br />AES-SIV & ARIA & CLEFIA the merits of 2023-01 RS<br /><br />As documentation shows ARIA uses a Random noise input in the encryption,<br />I believe this is so that it is hard to pick up the signals...<br />On the other hand it has a max data size of 192bit (AES does not),<br />I feel that ARIA has merits in WiFi & Telecoms.<br /><br />CLEFIA has a large data pathway; So could be good for large transfers & Drive Storage.<br /><br />As i say : ARIA, The Random element is about Stealth<br />AES-SIV has merits like AES-GCM, fast and relatively Safe.<br /><br />RS<br /><br />*</div><div><br /></div><div>ICE-SSRTP is relatively simple & involves a Dual Cypher of many classifications<br />AES, CHACHA20-POLY1305, GEA, 3DES & Other RTP Classifications such as UDP & TCP & GRE<br /><br />ICE-SSRTP is useful for:</div><div><br />TV & Satellite encoding & decryption<br />Messaging applications; Video & Call Encoding<br />Improved AES, CHACHA20-POLY1305, GEA, 3DES & Other RTP Classifications such as UDP & TCP & GRE<br />3G, 4G LTE & 5G Encoding<br />Radio & Telecoms<br /><br />*</div><div><br /></div><h4 style="text-align: left;">Sub-Band strobing & Statistical Adaptive frequency-hopping (AFH) & (s-AFH) : RS</h4><br />Firstly Sub-Band Passive Scanning:<br /><br />If you have 2G,3G, 4G, 5G, 6G, 7G on Bluetooth, WiFi & Telecoms network & in principle Radio's such as naval and satellite<br /><br />On detection of a receiver asking for a band:<br /><br />The following protocols to obey freely:<br /><br />General statistics and news emissions on the lowest bands; Statistics shall be used to select a band for tower or Bluetooth or WiFi reception<br /><br />The band shall be selected classified by priorities such as:<br /><br />Availability<br /><br />Required data capacity; such data as upload length & average load are part of the profile for faster & slower link status & application profiling & activation of higher energy requirement or lower average battery costs to mobile devices.<br /><br />Emissions profile.<br /><br />Power use of the band (if reception only, the most clear & data rich)<br /><br />Number of clients on the tower; for example the power requirements of a single antenna reduce in efficiency if under utilised..<br />If overused the requirement of the antenna increases as the capacitors & processor elements overload,<br />Reduction of load can optimise efficiency at around 60% Capacity as observed in magazine 'telecoms DE'.<br /><br />Usage of bands such as 3G instead of 4G for lower data usage,<br />While observing that clients already on 4G active antennas create the active antenna energy profile active priority.<br /><br />Secondly, Channel selection based on advanced statistical data & lower band submitted data,<br />Sub-Band clients shall be grouped so that they align clear of each other but in approximate proximity due to the fact that a single antenna can Multi-Band Emit & receive.<br /><br />Rupert S<br /><br />Let the Statistical Adaptive frequency-hopping (s-AFH) commence.<br /><br />*<div><br /><h4 style="text-align: left;">Common Sub-Band strobing with Adaptive frequency-hopping (AFH) : RS</h4>(Does not have to be Bluetooth, can be GSM & LTE & WiFi & Digital Radio)<br /><br />{<br />Bluetooth employs UHF radio waves in the ISM bands, from 2.402 GHz to 2.48 GHz,<br />Bluetooth divides transmitted data into packets, and transmits each packet on one of 79 designated Bluetooth channels, <br />Bluetooth Low Energy uses 2 MHz spacing, which accommodates 40 channels.<br />Each channel has a bandwidth of 1 MHz. It usually performs 1600 hops per second, with adaptive frequency-hopping (AFH) enabled, <br />} <br /><br />Synchronous Transmit:<br /><br />The Two devices Sync & exchange ECC Security; Time Sync & Band Selection, ECH Encryption Type & Certificate Synchronisations.<br /><br />Statistical Noise Analysis for band selections: (does not have to be ML or overly adaptive)<br /><br />Band order & Selection comes from Statistical Noise Listening; Where the Signal to Noise of locally transmitted signals is listened to over the device finding stage & If enabled from general pulsed noise listening..<br /><br />(on Selection of Device)<br />On selection of device scan on the Device; The Device strobes the lower frequency..<br />Device Sync Channels & Syncs with all devices submitting for scan..<br /><br />Device Scan, ECH Encryption Type & Certificate Synchronisations & Time Sync:<br />https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/<br /><br />{ON Time}ECH<br />Time Synce & ECH Client Hello Sync on previous data if the device is already connected during this {ON Time},<br /><br />If not then ECH & Time is synced with modern Certificate Key Exchange Protocols.<br /><br />Bands are selected in the Radio range available BT:{2.402 GHz to 2.48 GHz}:{79, 40} & Selections for channel order create Synchronisation between the devices..<br /><br />Time Syncing channel swapping with statistical S/N,<br />This allows the receiver to focus on specific bands as a priority & the order in unity synchronisations.<br /><br />Rupert S<br /><br />Bluetooth dongle LE Protocol <a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a><div><br /></div>*</div><br /><h4 style="text-align: left;">Client Hello ECH Time Sync Streaming</h4><br />The prospect of the client hello on a Mouse; Keyboard or System Device; Only makes sense in that SNI can be defined by the controller,<br /><br />But 'yes we can' Time Sync; TLS & Certificates &or metrics & data,<br />Client Hello ECH; Does have some usable function in cloud computing; HPC & Intra Networks such as: <br /><br />Controllers on a motherboard<br />WiFi, BT? Radio, Networking & Ethernet transports.<br /><br />Time Sync can also be set according to my T/ECC & is workable on low latency networking such as Bluetooth & dongles & GSM/LTE Telecoms & ICE-SSRTP<br /><br />Device Scan, ECH Encryption Type & Certificate Synchronisations & Time Sync:<br />https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/<br /><br />Much higher precision time & clock synchronisation can occur with ECH Client Hello, If Time variable is stored fresh along with synchronisation data & that is a sensible security profile for Time Sync ECC<br /><br />Examples: Gamer gear, Bolt & Unifying advanced mice & keyboards, WiFi & Bluetooth & DisplayPort & HDMI, Webcams & focusing, DAB+ & DVB Streaming,</div><div><br /></div><div>Common perception synchronisation issues with mice & controllers, video & audio frames to be removed with ECH Clock Sync & PTP,</div><div><br /></div><div>ECH would be used in Bluetooth & 2.4G Dongles & WiFi to identify a cloud of devices on the network,<br />On the motherboard GUID send & receive encryption, particularly CPU/GPU/HDD/SDD/RAM with integral TLS Encryption..<br /><br />Networked devices need a strong location saved; What is better than ECH? almost nothing but hard location,<br />ECH Network-IP/SID/GUID/BUSS is quick & adaptable.<br /><br />But all these need 2 things; Certified addresses & these could be IP & Identity!<br />By utilising GUID/Network location & Identity & Certificate & Qualified Security (AES-128-GCM & CHACHA20-POLY1305),<br /><br />Direct Raid Storage/RAM particularly has a hardware controller located at a specific register address & also a direct physical storage location on the media; That data is cached for cycles & refreshed though cache fetch.<div><br /></div>RS</div><div><br />*<br /><br /><h4 style="text-align: left;">SNI Tagged PSK : RS</h4>SNI Tagged Specific ECC / Elliptic<br /><br />SNI combined with Pre-Pin sharing AKA PSK<br /><br />Now PSK may not seem that useful to some people; But PSK Key-Sharing though DNS has some validity,<br /><br />Now how does this work? Factors to consider:<br /><br />Browsers like Chrome Preload site data before opening the tab<br /><br />You can use an ECC Certificate that Pre shares a Micro PSK per hour for initiation of contact?<br />Now ideally The Pre-Share PSK Key would verify against the server if required..<br /><br />Now TLS 1.3 & TLS 1.2 require a method of securing initial exchange (So the ECC & Elliptic Curve used are secret),<br />The majority of all Site encryption today is ECC & Elliptic RSA; So Pre-Shared PSK makes sense!<br /><br />So how do we go about this?<br /><br />SNI From the client contacting the server; When the Client contacts the server they receive a SNI Tagged PSK,<br />SNI Tagged PSK is a single Elliptic Curve output that is connected to the Client; So no one else could use it..<br />So PSK is secure; If SNI Tagged PSK; Because this is unique.<br /><br />SNI Tagged PSK also works for elliptic curves because an individual TCP UDP connection to the server can have an SNI Tagged Specific ECC / Elliptic.<br /><br />Rupert S<br /><br />*</div><div><div><br /></div><h4 style="text-align: left;">Device Security CRT Initiations for URT, USB, Wireless & other Device Interactions : (c)RS</h4><br />Origin device<br />GUID Certificates are renewable & Provide Encrypted Transport<br /><br />A very good way to think about a mouse, Keyboard & device AES & Crypto security is that a device needs to be in the certificate store,<br /><br />Two reasons Hardware acceleration is OS Store & Security; The device(computer) specifically requests all interactions with the CRT with a level of privacy & security, By GUID Definition & identity; Secondly limiting the function to parameters so it will not hack the system..<br /><br />So firstly the device certificate needs to interact with a store for a temporary cert & therefore we need a device Certificate store that contains the equivalent of the Secure client key in SHELL,<br /><br />This does not need to worry us; But we need a store! if not the device driver needs to initiate the system Store DL & AES Systems so that the device is secured with a personal store & main key (probably ECC-AES-'GCM<>FF3-1' )<br /><br />Certificate Store in OS<br /><br />Device can be Physical or Software Application Device..<br /><br />Origin System <> Origin device <> Sub-Device : OS <> OD <> SD1 <> SD2 <> SDn<br />GUID Certificates are renewable & Provide Encrypted Transport<br /><br />Computer, Certificate with machine ID<br />Device in OS,Device Verified Certificate, Certificate with GUID<br /><br />Device RAM:ROM, Certificate with GUID (Created by device driver with system Entropy)<br /><br />Device2 TV, Monitor, Webcam, Mouse, Keyboard :<br />RAM:ROM, Certificate with GUID (Created by device driver with system Entropy)<br /><br />Device3 in chain:<br />RAM:ROM, Certificate with GUID (Created by device driver with system Entropy)<br /><br />All GUID certificates are verified against the origin device GUID Certificate..<br />All GUID Certificates are renewable & Provide Encrypted Transport<br /><br />Rupert S<div><br /></div><div><h4 style="text-align: left;">Light# Sharp Security : Latency & Speed</h4><br />Bluetooth, Bolt (BT), Unifying Receiver: ICE-SSRTP<br /><br />Observations of devices such as:<br /><br />Logitech Bolt (ECDH AES GCM)<br />Amazons Keyboard & Mouse (AES Secure)<br /><br />Logitech Unifying Receiver & Bluetooth (Varies);<br /><br />Personally i forward ICE-SSRTP,<br />ICE-SSRTP is based on flexible encryption channels (1 to 7) & Wave banding (separate wave threads)<br /><br />According to reports the Unifier USB was not compatible with 256Bit GCM ECDH,<br />Now i would observe that ICE-SSRTP has several options available that are competitive:<br /><br />Multiple Sub-Banding (MP4, AC3, AC4, SBC, BT)<br /><br />Improved AES,<br />CHACHA20-POLY1305,<br />GEA,<br />3DES<br /><br />& Other RTP Classifications such as UDP & TCP & GRE<br />3G, 4G LTE & 5G Encoding.<br /><br />So as follows, In principle 3 Sub-Band 64Bit AES/GCM/GEA/3DES; Offers quite a lot of security!<br /><br />Now hold on! 64Bit/96Bit AES? <<br /><br />Cypher Keys : 64Bit/96Bit/128Bit/192Bit/256Bit<br /><br />AES,<br />CHACHA20_POLY1305,<br />GEA,<br />3DES, 5DES,<br /><br />3/5 AES key DES ,<br />3/5 CHACHA20_POLY1305 key DES<br />3/5 GEA DES ,<br /><br />Elliptic Curves<br /><br />curve25519<br />nistP256<br />nistP384<br /><br />brainpoolP256r1<br />brainpoolP256t1<br />brainpoolP384r1<br />brainpoolP384t1<br /><br />nistP521<br />brainpoolP512r1<br />brainpoolP512t1<br /><br />3 Bands! Even 5 &<br />2 to 4 Keys CRT<br />&or<br />2 to 5 Timing Syncs<br /><br />Yes this is ECDH & Time is involved; So who says 2 bands have the same moment to Sync?<br /><br />In terms of lightweight security (Bluetooth ear-buds & other tiny things) :<br />64Bit AES/3DES/GEA with ICE-SSRTP Nonce makes perfect sense.<br /><br />In Terms of heavier (in terms of ARM Core Phones & Network-boxes) :<br /><br />Both the 64Bit Instruction-set & the 32Bit SiMD/NANO + AES-NE + Advance Crypto Instruction ACI,<br />96Bit/128Bit AES/3DES/GEA * 3 Packets per nonce ICE-SSRTP<br /><br />In Terms of larger demands: With 64Bit/128Bit Instruction-set & the 32Bit SiMD/NANO/AVX128Bit+, + AES-NE + Advance Crypto Instruction ACI<br /><br />96Bit * 5 /128Bit/256Bit/384Bit *3 AES/3DES/GEA * 3 Packets per nonce ICE-SSRTP<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">DES-5 CommonKey : RS</h4>To explain DES-5 First i have to explain that encryption key passes to key in DES,<br />Firstly One small key 96Bit, 192Bit, 256Bit <> 512Bit(quite a bit higher than we want to use for speed),<br />Now firstly using AES we would be using an RSA/ECC Key 2048Bit/384Bit with 3 public facing dynamic certificate shards,<br /><br />The primary principle of DES3 is dynamic key exchange & change,<br />variability is crucial.<br /><br />What we need is Acceleration & for this we will use AES, GEA, ChaCha_Poly,<br />But in the case of AES accelerating USB; AES Obviously & 3 Keys Time Synced Encryption,<br /><br />Because as we know Time Nonce encryption is secure.<br /><br />RS<br /><br /><h4 style="text-align: left;">Shard Certificate(tm) : RS</h4><br />Shard server certificate is RSA or ECC with 3 or more random public exchangeable product,<br />The regular public key also.<br /><br />Shard otherwise known as Public certificate; But a Dynamic shard is a created and exchanged random 'public facing'...<br /><br />Micro certificate & I call this a Shard Certificate(tm).<br /><br />A Shard Certificate is part of my DES project in 3 to 7 Bands & the main project is to reason around the topic of DES3 that needs varying cryptographic keys..<br /><br />Rupert S</div><div><br /></div><div><br /></div><h4 style="text-align: left;">(QT_SECC) ECC Temporal Tick for low energy devices & computer systems : RS</h4><br />(including GPU & RAM & Fast Storage),<br />Fast & high performance Elliptic Curves 8Bit to 128Bit<br /><br />Ideal standards of 16Bit Elliptic curves for Audio, Video, 3D Texture & Edge shaping...<br />As described here we create edges & cubes & fills & Obviously Elliptic Curves!<br /><br />We can shape digital audio directly; But also Video & Textures; Any shape that matches our description..<br />Any dream involving a precisely defined maths object that is a shape vector.<br /><br />This is not just a security device.<h4 style="text-align: left;">BT-2.4G QT_SECC</h4>Able to be used for Motion, Haptic, Video, Texture, Audio wavelet creation & use:</div><div><br /></div>The Wave pattern principle is in principle a content of pure colour curves, both depth & content of pixel,<br /><br />But also a means by which elliptic curves are created with great simplicity.. <br />So that singular hardware like F16 SiMD can truly create a master piece; Both Crypto & Dimensional 'art'</div><div><br /><div>BT-2.4G Quartz Time Crystal Tick Simple Elliptic Curve to Support FIPS 128Bit on Unifier USB,<br /><br />Modulation to 16Bit& 32Bit & 64Bit & 128Bit allow for different types of SiMD & AVX<br />Allow for Android & Linux & Windows; ARM & X86 & GPU Processors<br /><br />Presented with a single tick \_/-\_/ Complex modulating Elliptic curves of 8Bit & 16Bit & 32Bit & 64Bit & 128Bit lengths,<br /><br />16Bit to 64Bit & 128Bit output curves; Through temporary ECC certificate..; Additionally ChaCha_Poly & AES Cyphers..</div><div><br /></div><div>Depending on SVE & AES-NI's Capacity to Dynamically accelerate TLS, We may have sufficient Lattice support even for Kyber! & other Lattice Encryption types.<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">Encrypted Dictionary Compression for Distributed Media (c)RS</h4><br />As you may know wise people encrypt trademarked work that is worthy of viewing in the video world HDCAP is usually used because video encryption with AES at 20GB/s is quite impossible... <br /><br />However the configuration that i have developed allows the coded wavelet main data pack to be encrypted..<br /><br />You may however be aware that statistically most compressed files do not decompress without dictionary files being loaded, <br /><br />While not ideal Dictionary compression with encrypted dictionary provides much security & deep compression advantages.<br /><br />Rupert S</div><div><br /></div><div><h4 style="text-align: left;">Compression, Dictionary Sort & Same Size Copy Match & Unite Same with location in 2D Matrix #JS #C #Python RS 2023</h4><br /><a href="https://is.gd/CJS_DictionarySort">https://is.gd/CJS_DictionarySort</a><h4 style="text-align: left;">Ellipso formula for compressed media:</h4><br />The headers are encrypted with AES:{GCM, CCM}, CHACHA20-POLY1305<br />The header containing compression words, File List, Directory & Data chunks for replication..<br /><br />Ellipso encoded data segments for example graphs, Curves, Shapes, A:B:C colour or audio & math scaling curves,<br />Representing data curves such as colour gradients & corners or ellipses; In Lines or Cubes..<br /><br />Conception is similar to compression data compression shapes; But defining most shapes & colour or sound samples.<br /><br /><a href="https://science.n-helix.com/2022/09/ovccans.html">https://science.n-helix.com/2022/09/ovccans.html</a><br /><a href="https://science.n-helix.com/2022/11/frame-expand-gen-3.html">https://science.n-helix.com/2022/11/frame-expand-gen-3.html</a><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br />Bluetooth dongle LE Protocol<br /><a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a><br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">Compression A,B,C Matrix Comparators, 2+ Layers compression comparators</h4><br />A C<br />| /<br />+----B <br />As in layers comparisons in 8Way x 3D cross comparisons with similar data unification & replications:<br /><br />These are called pages; Pages exist in RAM Layouts like EPR Extended Page RAM (4GB Pages),<br /><br />We compare pages and reduce data footprint by reducing Double copies & compressing,<br />We compress by combining objects transparently.<br /><br />Right so working 2+ layer compression is comparing layer 1 with 2 & compressing them with ZSTD/GZip/Brotli<br /><br />We will be using Multiple Page Compression & for that reason we Double page for example by:<br /><br />Checkerboard rendering on 3 Pages..<br /><br />By combining core Kernel Registers & Hardware Addresses in the same virtual space...<br /><br />By storing 8,16>n blocks of the same data on a single block with Data8x, Data16x > DataNxBy mapping patterns<br /><br />RS<div><h4 style="text-align: left;">AES-GCM Compressing RAM : RS</h4><br />AES-GCM Compressing RAM has never been so easy !: RAM frame compression with LZ Compression styles<br /><br />In the principle Header Encryption does not interfere with the fact that the Header is a LZ Compression Frame!<br /><br />But the content is secure & compressed with the GZip/LSTD formula,<br />Because as we know EXE Headers decompress chunk<br /><br />RS<br /><br /><h4 style="text-align: left;">HDMI Input compression : Checker Board 2 frame compression with LZ Compression styles</h4><br />The application of GZIP Brotli ZSTD compression to screen data tunnels, Allows for 11K for connections on DisplayPort & HDMI, <br />With the simple switch to automatically lossless compression tunnels, <br /><br />The use of Checker Board 2 frame compression with LZ Compression styles allows most generic CPU to Deinterlace Double Scan data layers..<br /><br />Doubling effective resolutions.</div><div><br /></div><div><h4 style="text-align: left;">QFT Quick Frame Transport in relation to HDMI Input compression:</h4><br />When you transmit serial frames with the same data compression comes in handy!<br />So enabling Brotli/ZSTD/GZip/DSC compression with Proofs of frame exact copy or slight modifications..<br /><br />Now transmit each part of the frame that is exactly the same as a compression copy, <br /><br />So in effect the frame is micro copied & each part is identified as part of the main frame repeat or new,<br /><br />In addition if the colour shifts but not the edges or shape; Most of the compression works in reference to HDMI Input compression,<br /><br />Brotli/ZSTD/GZip/DSC compression works fine in referencing colour shifting light or shape shifting but same light,<br /><br />Compression works fine.</div><div><br /></div>QFT with SSRTP is perfect for Web+ content refreshing 'Audio & Video' HDMI & VESA DisplayPort connection configurations.<div><br /></div><div>Aligned Byte Codes with 16bit compression codes ZSTD saves 80% of all data costs to content,<br />Small Byte dictionary compression saves 80% of transmit bandwidth.<div><br />(c)RS</div><div><br /></div><div>*<br /><h4 style="text-align: left;">Encoding with Encryption Developments</h4><br />Brilliant example use : JPEG-Compatible Joint Image Compression and Encryption Algorithm with File Size Preservation<br /><a href="https://is.gd/CypherMJPG">https://is.gd/CypherMJPG</a><br /><br />We with method AC4 & AAC Shall - Fully Justified 1.2Khz Chaos Maps Discrete Cosign - Speech encryption algorithm based on two newly designed chaotic maps<br /><a href="https://is.gd/AudioDCzipMatrix">https://is.gd/AudioDCzipMatrix</a><br /><br />An Image Encryption Method Based on Lorenz Chaotic Map and Hunter-Prey Optimization<br /><a href="https://is.gd/QualityImageEncode">https://is.gd/QualityImageEncode</a><br /><br />SemiClearImage Detailed - A visually secure image encryption method based on semi-tensor product compressed sensing and IWT-HD-SVD embedding<br /><a href="https://is.gd/FuzzImageEncode">https://is.gd/FuzzImageEncode</a><br /><br />1 https://dl.acm.org/doi/10.1145/3633459<br />2 https://www.sciencedirect.com/science/article/pii/S277318632300049X<br />3 https://www.researchgate.net/publication/375917450_An_Image_Encryption_Method_Based_on_Lorenz_Chaotic_Map_and_Hunter-Prey_Optimization</div><div>*<div><h4 style="text-align: left;">Elliptic Curves & JPEG & MP4/ACC Presentation</h4><br />Ok so principally we want to create curves with ARC, Sin & Tan,<br />We can obviously present a curve in 16Bit or even 8Bit; So we can present a curve at the precision we have in the processor (such as 16Bit/32Bit SiMD),<br /><br />By presenting a curve at higher precision; We can upscale or super sample it,<br /><br />Super Sampling is principally presenting a curve at higher precision &or softening it with analogue/Digital filters..<br /><br />So by this example we present a case for elliptic curves presented within the scope of 16Bit or higher SiMD & Floats..<br /><br />The key idea is that we can use them!<br /><br />So we can present JPEG, ACC, MP4 as Elliptic curves for upscaling...<br />We can use Elliptic curves for encryption or presentation on GPU or other processors,<br />We can present curves to the pixels of a screen surface the same way; scaling them into higher precision.<br /><br />How well defined that curve is depends on our precision capacity; But we can still use Elliptic curves at any precision we have available.<br />So what do we want to use Elliptic curves to present ? Anything we need.<br /><br />RS<div><br /></div><div>The Certificate is so that Radio/BT/2.4G is secure on all devices; We intend to use AES & PolyCha (which ever is easier) To produce a device connection that is hard to crack & therefore secure!<br /><br />But we achieve one more thing; We verify that the signal is correct & therefore we secure the signal's against noise!<br /><br />Because of the speed PolyCha Encodes at; AES Is faster on most CPU,<br />We can use what we like! The 112.79 MB/sec of Polycha is ok! AES is much faster! 0.56 GB/sec<br /><br />AES-128-GCM - TLS1.2 0.56 GB/sec<br />AES-128-GCM - TLS1.3 0.57 GB/sec<br />CHACHA20-POLY1305 - TLS1.2 112.79 MB/sec<br /><br />But we do not Have to use AES/PolyCha But we should!<br /><br />RS</div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">Ellipic Example : TVarEllipsoRS</h4></div><div>var RealCurves = {<br /><br />/* definition<br />var Diameter D = 1<br />var Time default = 2<br />var Forward motion = T seconds<br />var Backward motion = T Hours<br />*/<br /><br />R = 1/360<br /><br />E = /dev/rnd<br /><br />Tv1 = D * (seconds - Microseconds)<br />TV2 = R * micro seconds<br /><br />var D = T Hours - T Seconds<br />var R = T Seconds - T Hours<br /><br />var Ellipse1 = (Tv1 * D) * (R / Second)<br />var Ellipse2 = (Tv2 * D) * (R / (Second - microseconds))<br /><br />Curve = modulus Ellipse1 * Ellipse2 / Time minutes<br />Curve2 = modulus Ellipse1 * Ellipse2 / Time seconds<br /><br />entropy fetch = E<br /><br />Query = Real_Curves { E + Curve + curve2 }<br /><br />}};<br /><br />fetch = (RealCurves)};<br /><br />}<br /><br /><br />Rupert S<br /><br /><br /><h4 style="text-align: left;">Elliptic Example2 : TVarEllipsoDelipsoRS</h4><br />var RealCurves = {<br /><br />/* definition<br />var Diameter D = 1<br />var Time default = 2<br />var Forward motion = T seconds<br />var Backward motion = T Hours<br />*/<br /><br />R = 1/360<br /><br />E = /dev/rnd<br /><br />Tv1 = D * (seconds - Microseconds)<br />TV2 = R * micro seconds<br /><br />var D = T Hours - T Seconds<br />var R = T Seconds - T Hours<br /><br />var Ellipse1 = (Tv1 * D) * (R / Second)<br />var Ellipse2 = (Tv2 * D) * (R / (Second - microseconds))<br /><br />Curve1 = modulus Ellipse1 * Ellipse2 / Time minutes<br />Curve2 = modulus Ellipse1 * Ellipse2 / Time seconds<br />Curve3 = mean deviation {Curve1, Curve2}<br />Curve4 = mean deviation {Curve2, Curve1}<br /><br />entropy fetch = E<br /><br />Query = Real_Curves1 { E + Curve1 + curve2 }<br />Query = Real_Curves2 { E + Curve2 + curve1 }<br />Query = Real_Curves3 { E + Curve3 + curv4 }<br />Query = Real_Curves4 { E + Curve4 + curve3 }<br /><br />Group_Curve1 {Real_Curves1, Real_Curves3, Real_Curves2, Real_Curves4}<br /><br />}};<br /><br />/* Fetch in order */<br /><br />fetch = (Group_Curve1)};<br /><br />}<br /><br />Rupert S</div><div><br /></div><div>*<br /><br /><h4 style="text-align: left;">ECC Time Curves Mate A:B | Basic</h4><br />/*<br />X<br /> Y<br />*/<br /><br />for string length = SL<br />Origin point = OP<br />for End of string = EP<br />Total Length of string a = TLSa<br />though Radius Length RL<br />Till motion stop = TMS<br />Total Length of String b = TLSb<br /><br />a : For when OP + TLSa begin calculate (RL=(Time microseconds))*TLSa<br /><br />b : then calculate TLSb & calculate From EP + (RL=(Time microseconds))*TLSb<br /><br />then for a complete, start b & for b complete then start a<br /><br />Curves Mate A:B | B:A <> B:A | A:B<br /><br />function run = T | TMS<br /><br />Rupert S<div><br /></div><div>*</div><div><br /></div><div>ECH : Encrypted Client Hello SNI</div><div><a href="https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/">https://datatracker.ietf.org/doc/draft-ietf-netconf-tls-client-server/</a><br /><a href="https://blog.cloudflare.com/encrypted-client-hello/">https://blog.cloudflare.com/encrypted-client-hello/</a><br /><br />Post-Q ECH ECC<br /><a href="https://datatracker.ietf.org/doc/html/rfc9180">https://datatracker.ietf.org/doc/html/rfc9180</a></div><div><br />PQXDH Key Agreement Protocol : <br />XEdDSA:{HASH SHA-256 or SHA-512 & curve25519 or curve448} & KEM Crystals-Kyber-1024<br /><a href="https://signal.org/docs/specifications/pqxdh/">https://signal.org/docs/specifications/pqxdh/</a><br /><br />X3DH XEdDSA:{HASH SHA-256 or SHA-512 & Curve X25519 or X448}<br /><a href="https://signal.org/docs/specifications/x3dh/">https://signal.org/docs/specifications/x3dh/</a></div><div><br /></div><div>Bluetooth dongle LE Protocol <a href="https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing">https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing</a><br /><br /><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a><br /><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a><br /><br /><a href="https://science.n-helix.com/2022/02/interrupt-entropy.html">https://science.n-helix.com/2022/02/interrupt-entropy.html</a><br /><br />*</div><br />In my opinion RSA_ECC & CryptoKey_ECC_AES is perfectly acceptable (in terms of cost vs home user); PassKey_ECC_AES is quite industrially acceptable; For example an HMS System with passcards (HashPassKey_ECC_AES) is quite a fort!<br /><br />So in effect the Changing:(RSA ECC) key is an incredible break for our business & infact.. creating a solution of our privacy is very expensive to the adversary; Sadly for us? it is all entirely possible..<br /><br />But not too easy for them or us.<br /><br />https://en.wikipedia.org/wiki/Elliptic-curve_cryptography<br /><br />RS<br /><br />"Shor's algorithm can be used to break elliptic curve cryptography by computing discrete logarithms on a hypothetical quantum computer. <br /><br />The latest quantum resource estimates for breaking a curve with a 256-bit modulus (128-bit security level) are 2330 qubits and 126 billion Toffoli gates.<br /><br />For the binary elliptic curve case, 906 qubits are necessary (to break 128 bits of security).<br /><br />In comparison, using Shor's algorithm to break the RSA algorithm requires 4098 qubits and 5.2 trillion Toffoli gates for a 2048-bit RSA key.. <br /><br />The evidence suggesting that ECC is an easier target for quantum computers than RSA. <br /><br />All of these figures vastly exceed any quantum computer that has ever been built, and estimates place the creation of such computers at a decade or more away.<br /><br />Supersingular Isogeny Diffie–Hellman Key Exchange claimed to provide a post-quantum secure form of elliptic curve cryptography by using isogenies to implement Diffie–Hellman key exchanges. <br /><br />This key exchange uses much of the same field arithmetic as existing elliptic curve cryptography and requires computational and transmission overhead similar to many currently used public key systems,<br /><br />However, new classical attacks undermined the security of this protocol."<br /><br />*<div><br /></div><div><h4 style="text-align: left;">8Bit Galois Field operations GF2P8AFFINEQB</h4><br />"<br />A Galois Field is a mathematical structure where addition and multiplication have been redefined so that some very useful properties are retained. Galois Fields can exist with any prime number or an "extension field" where that prime-number is vectorized. In this case, the GF2 field (prime number 2) has been extended to 8-bits (aka: a GF(2^8), aka 8-bit Galois Field).<br /><br />"Addition"'s new definition is simply XOR.<br /><br />"Multiply"'s new definition is bitshift and then add. (ie: 0b10101010 x 0b00010010 == bitshift(x, 4) + bitshift(x, 1), because the 4th and 1st bits are set to 1). And remember that "addition" has been redefined to XOR in this math, so that + means XOR.<br /><br />An Affine Transformation is A * x + B, where x is the original value. As a "Galois Field Affine Transformation", A * x and + B are all done in "Galois Field" terms.<br /><br />This is an AVX512 instruction, meaning there are 32-parallel versions of this 8-bit computation happening in parallel across a 512-bit vector.<br /><br />Note: operation traditionally happens modulo a particular GF(number) to create a field. The above operations are "primitives" that can eventually create a field, but aren't making a field just yet.<br /><br />Perhaps the more accurate names for these operations is "GF-addition" and "GF-pseudo-multiplication". In any case, multiplication is any combination of the 8-bitshifts (bitshift0, bitshift1, bitshift2...) and the 8x such results added together (depending on the 1 or 0 on that bit). Meaning you can very easily describe bitshift-and-xor operations to other cryptographers who are operating in "GF-language""<br /><br />GCM - Galois Field - Permuting Bits with GF2P8AFFINEQB<br />https://news.ycombinator.com/item?id=37630391</div><div><br /><div>*</div><br /><h4 style="text-align: left;">Due to the Lattice nature of SVE & AES-NI : Matrix & SiMD : RS</h4><br />Use AES-NI S Letter Box & SVE & Matrix & SiMD to our advantage for many Lattice operations.<br /><br />AES-NI & SVE are relevant because Lattices are created in such a way that is similar to AES & S-Boxes are a primary form of what is called a Lattice; Now a lattice is better presented in what is called a Matrix processor!<br /><br />Now a Matrix processor is a feature that will be more common & is relatively similar to an Abacus with a multiple array of + & * Operators..<br /><br />Now a Matrix Array is X1 > Xn & Y1 > Yn<br /><br />Commonly an array of 16 x 16 but can be 8 x 8 or 4 x 4,<br /><br />Now we can perform such operations as Relativity & String theory on a lattice & that is very fast!<br /><br />We can also perform these functions on SiMD, AVX in parallel; Such that 256Bit SiMD is 32Bit x 8 Parallel & so forth<br /><br />Parallel<br />a : 64Bit<br />b : 64Bit<br />c : 64Bit<br />d : 64Bit<br /><br />Matrix<br />a1a2a3a4<br />b1b2b3b4<br />c1c2c3c4<br />d1d2d3d4<br /><br />Now we can see that we can perform a matrix operation such as lattice with both SiMD & SiMD-Matrix,<br /><br />We can also see that a Matrix shall & can present our solution & that SiMD can also!<br />But we need Long operation SiMD or many passes to complete our operations; If Larger than our size..<br /><br />We can also therefore most likely..<br /><br />Use AES-NI S Letter Box & SVE & Matrix & SiMD to our advantage for many Lattice operations.<br /><br />Multiplier Matrix Accelerated Encryption, Like i said A Parallel SiMD array may do the same; If all memory arrays are connected by a single RAM/Cache ALU Node,<br /><br />As stated Parallel Arrays & Parallel Matrix Arrays.<div><br /></div>Rupert S<br /><br />*</div><div><br /><h4 style="text-align: left;">Examples of Parallel execution pipeline : Parallel arrays:</h4><br />Crypto lattice, Kyber/ML-KEM, AES : Parallelised Lattices, 8x & 16x Parallel SiMD F16/32/64/128/192/256Bit<br /><br />parameterisation of groups of 4x Parallel SiMD F16 & 8x Parallel SiMD F16<br /><br />Parallelised motion & Video/Audio Deblocking/Blocking<br /><br />8x8 16x16 quantification of video is common in VVC & H265 & H264 & JPEG & MP3, MP4a & AAC,<br />Suggested parameterisation of 4x Parallel SiMD F16<br /><br />8x8 16x16 quantification of video is common in HDR VVC & H265 & H264 & JPEG & MP3, MP4a & AAC & AC3 & AC4,<br />Suggested parameterisation of 4x Parallel SiMD F32<br /><br />Shapes in motion 2D : 4x per Cube in motion,<br />Shapes in motion 2D : 6x per Texture Shaded Cube in motion,<br /><br />Shapes in motion 3D : 6x per Cube in motion,<br />Shapes in motion 3D : 8x per Texture Shaded Cube in motion,<br /><br />RS<br /><br />*</div><div><br /><h4 style="text-align: left;">S-Box Lattice Matrix 8x8, 16x16, 32x32, 36,36 & more : RS</h4><br />So AES is an 8x8 S-Box Grid/Lattice,<br />Kyber/ML-Kem fits inside the parameters of AES?<br /><br />So what Size S-Box Lattice do most of the Lattice Cyphers fit into; Should we optimise them to 8x8?<br />Should we fit a 32x32 S-Box/Lattice or 16x16 Lattice S-Box in our configurations?<br /><br />Do we need that much complexity? or can we simply SiMD Matrix most of that...<br /><br />But we could use a good 16x16 or better yet 32x32, 36x36 for our research into time & space!<br />But we can manage something with 8x8.<br /><br />S-Box Lattices<br /><a href="https://csrc.nist.gov/projects/pqc-dig-sig/round-1-additional-signatures">https://csrc.nist.gov/projects/pqc-dig-sig/round-1-additional-signatures</a></div><div><br /></div><div><a href="https://science.n-helix.com/2023/06/map.html">https://science.n-helix.com/2023/06/map.html</a><br /><br />Rupert S<br /><br />*</div><div><br /></div><h4 style="text-align: left;">Lattice problems with errors : ML-KEM/Kyber - AES - ECC + Random Key</h4><div><br /></div><div><div>Lattice Maths ECC-AES-Kyber</div><div>https://www.redhat.com/en/blog/post-quantum-cryptography-lattice-based-cryptography</div></div><div><br /></div><div>Lattice problems with errors : ML-KEM/Kyber - AES - ECC + Random Key,</div><div><br /></div><div>Now according to him the lattice has solutions such as similar geometric triangles being mapped,</div><div><br /></div><div>Random Bytes Principle:</div><div><br /></div><div>So what happens if we generate a 16KB /dev/random & Hash it with AES & send from A (server) to B (client); The HASH?</div><div><br /></div><div>Supposing that A knows B's HASH & B knows A's Hash,</div><div><br /></div><div>So in essence A & B both know a hash from the other party.</div><div><br /></div><div>Rupert S</div><div><br /></div><div>*</div><div><div><br />https://www.theregister.com/2021/09/01/logitech_bolt_devices_support_secure/<br /><br />https://www.theverge.com/2021/9/1/22651973/logitech-logi-bolt-usb-dongle-bluetooth-security-le-keyboard-mouse-accessories<br /><br />https://www.makeuseof.com/what-are-logitechs-unifying-bolt-wireless-technologies/<br /><br />https://www.onesdr.com/logi-bolt-vs-logitech-unifying-receiver-which-one-should-i-buy/<br /><br />Audio, Visual & Bluetooth & Headset & mobile developments only go so far:<br /><br />Bluetooth dongle LE Protocol https://drive.google.com/file/d/17csRnAfdceZiTSnQZvhaLqLSwL__zsIG/view?usp=sharing<br /><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br />https://science.n-helix.com/2021/11/ihmtes.html<br /><br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.html<br /><br />https://science.n-helix.com/2023/06/map.html<br />https://science.n-helix.com/2023/02/smart-compression.html<br />https://science.n-helix.com/2022/04/vecsr.html<br /><br />https://science.n-helix.com/2022/10/ml.html<br />https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html<br /><br />https://science.n-helix.com/2018/12/rng.html<br />https://science.n-helix.com/2022/02/rdseed.html<br />https://science.n-helix.com/2017/04/rng-and-random-web.html<br />https://science.n-helix.com/2022/02/interrupt-entropy.html<br /><br />https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html<br />https://science.n-helix.com/2021/11/wave-focus-anc.html<br />https://science.n-helix.com/2021/12/3d-audio-plugin.html<br /><br />*</div><div><br />In terms of lightweight security (Bluetooth ear-buds & other tiny things) :</div><div>64Bit AES/3DES/GEA with ICE-SSRTP Nonce makes perfect sense.<br /> <br />In Terms of heavier (in terms of ARM Core Phones & Network-boxes) :</div><div><br /></div><div>Both the 64Bit Instruction-set & the 32Bit SiMD/NANO + AES-NE + Advance Crypto Instruction ACI,</div><div>96Bit/128Bit AES/3DES/GEA * 3 Packets per nonce ICE-SSRTP</div><div><br /></div><div>In Terms of larger demands: With 64Bit/128Bit Instruction-set & the 32Bit SiMD/NANO/AVX128Bit+, + AES-NE + Advance Crypto Instruction ACI</div><div><br /></div><div>96Bit * 5 /128Bit/256Bit/384Bit *3 AES/3DES/GEA * 3 Packets per nonce ICE-SSRTP</div><div><br />*</div><div><br /></div><div><h4 style="text-align: left;">DPI BAUD Maths with BT-2.4G QT_SECC</h4><br />Now a 1000DPI mouse that maps a 1000x1000 space requires 1Mb/s; But obviously we are not expecting to map..<br />1000000 different spaces on a cube cm²..<br /><br />But with 100x100 Cube we can map any displacement of 100 units per cycle; 1Kb/s..<br /><br />But at that rate we map a path & that takes at least 50 points at 16Bit compressed.<br /><br />So! Table (tick table)<br /><br />100x100 1Kb<br />500x500 5Kb<br />1000x1000 25Kb<br />10000x10000 100Kb<br />So each download takes upto 25Kb/s at 1000 & 100Kb/s at 10000 point mapping..<br /><br />Keep in mind we have to literally map 10000 points for 100Kb & that we will be using Elliptic Curves & Shapes..<br />Both improving precision & also reducing bandwidth costs.<br /><br />Protocol for mouse:<br /><br />BT-2.4G QT_SECC<br /><br />Able to be used for Motion, Haptic, Video, Texture, Audio wavelet creation & use:<br /><br />BT-2.4G Quartz Time Crystal Tick Simple Elliptic Curve to Support FIPS 128Bit on Unifier USB,<br /><br />Modulation to 16Bit& 32Bit & 64Bit & 128Bit allow for different types of SiMD & AVX<br />Allow for Android & Linux & Windows; ARM & X86 & GPU Processors<br /><br />Presented with a single tick \_/-\_/ Complex modulating Elliptic curves of 8Bit & 16Bit & 32Bit & 64Bit & 128Bit lengths,<br /><br />16Bit to 64Bit & 128Bit output curves; Through temporary ECC certificate..; Additionally ChaCha_Poly & AES Ciphers..<br /><br />(c)Rupert S</div><div> <br /><div>*</div></div><br /><h4 style="text-align: left;">Mouse & Pointers : Position X, Y, Z : Example : RS</h4><br />Example Move: {A2 to E7}<br /><br />compare : {<br /><br />var X = N1<br />var Y = N2<br />var Z = N3<br /><br />};<br /><br />N1, N2, N3 = {<br />N:0123456789<br /><br />A:0123456789<br />B:0123456789<br />C:0123456789<br />D:0123456789<br />E:0123456789<br />F:0123456789<br /><br />};<br /><br />{<br /><br />draw curve {(X, Y)+(xZ, yZ)};<br /><br />RS<br /><br />*<div><br /></div><div><div>When it comes to pure security, We are grateful</div><div>https://is.gd/SecurityHSM https://is.gd/WindowsSecureHSM_PKI https://is.gd/WebPKI TLS Optimised</div><div>https://drive.google.com/file/d/10XL19eGjxdCGj0tK8MULKlgWhHa9_5v9/view?usp=share_link</div><div>Ethernet Security</div><div>https://drive.google.com/file/d/18LNDcRSbqN7ubEzaO0pCsWaJHX68xCxf/view?usp=share_link</div><div><br /></div><div>These are the addresses directly of some good ones; DNS & NTP & PTP</div><div><br /></div><div>2600:c05:3010:50:47::1 2607:fca8:b000:1::3 2607:fca8:b000:1::4 2a06:98c1:54::c12b </div><div>142.202.190.19 172.64.36.1 172.64.36.2 38.17.55.196 38.17.55.111</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">#FreeRAND #Proverbs</h4><br />Random is made to be free, to be as free as a bird, it becomes the<br />certificate of our freedom<br />and is cherished as born free, As free as Random is! Born to be free;<br />But Born forth freely by the angels of our seed.<br /><br />JN<br /><br />dev-rnd windows<br /><br />Nothing like leaching Rand from ubuntu! no not at all! but you can<br />build pollinate and pollen for windows I would be greatful! thank you<br />bill gates (as apps because windows update does not work for me & I<br />built a dev/rnd for windows with a friend from a defence group before<br />he disappeared!, be a hero bill)<br /><br />DiHARD This *Random* for your /dev/rnd *file*<br /> MiniSeed2023.zip<br />https://drive.google.com/file/d/1LjUsVd6W38y0RPau7M7UyfUhoYsagxoC/view?usp=drive_web<br /> MiniSeed2023b.zip<br />https://drive.google.com/file/d/14vs4xkD9QgtDhROcS5TDwGKDd4TxvloA/view?usp=drive_web<br /> MiniSeed2023c.zip<br />https://drive.google.com/file/d/15CRO97oXsoAe7wdh6yYeHhJi9cKLfExs/view?usp=drive_web<br /> MiniSeed2023d.zip<br />https://drive.google.com/file/d/12viSYnqwwzJh9jQdUuxDYO0mCwdHmxzM/view?usp=drive_web<br /> MiniSeed2023E.zip<br />https://drive.google.com/file/d/1b1Jd4QTKB8-ADrtzikK73SXvQB0jZpiZ/view?usp=drive_web<br /> MiniSeed2023f.zip<br />https://drive.google.com/file/d/1EYpbQdBSp-fmU1XTb9BrJoE9UyXKQpK1/view?usp=drive_web<br /> MiniSeed2023G.zip<br />https://drive.google.com/file/d/1ZJLKjLrLfrdMxVCzNzKEw3DcDg__ZgE3/view?usp=drive_web<br /><br />Entropy / Chaos for /dev/rnd available whenever you like from<br />https://pollinate2.n-helix.com/ https://pollinate.n-helix.com/<br /><br />Constantly active rings<br /><br />if you do not know about Pollen & Pollinate ubuntu, google it!<br /><br /><a href="https://science.n-helix.com/2018/12/rng.html">https://science.n-helix.com/2018/12/rng.html</a><br /><a href="https://science.n-helix.com/2017/04/rng-and-random-web.html">https://science.n-helix.com/2017/04/rng-and-random-web.html</a><br /><br /></div><div><a href="https://science.n-helix.com/2020/06/cryptoseed.html">https://science.n-helix.com/2020/06/cryptoseed.html</a><br /><a href="https://science.n-helix.com/2022/02/rdseed.html">https://science.n-helix.com/2022/02/rdseed.html</a><br /><br />RS<br /><br />*</div><div><div><div><h4>ICE-SSRTP GEA Replacement 2022 + (c)RS</h4></div><div><br /></div><div>IiCE-SSR for digital channel infrastructure can help heal GPRS+ 3G+ 4G+ 5G+</div><div><br /></div><div>Time NTP Protocols : is usable in 2G+ <> 5G+LTE Network SIM</div><div><br /></div>ICE-SSRTP Encryption AES,Blake2, Poly ChaCha, SM4, SHA2, SHA3, GEA-1 and GEA-2 <div>'Ideal for USB Dongle & Radio' in Rust RS ' Ideal for Quality TPM Implementation'<div><br /></div><div>"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension<br />of GEA-1 with a higher amount of processing, and apparently not<br />weakened) are bit-oriented stream ciphers."</div><div><br /></div><div><div>IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol</div><div><br /></div><div>Interleaved signals help Isolate noise from a Signal Send & Receive ...</div><div><br /></div><div>Overlapping inverted waves are a profile for complex audio & FFT is the result.</div><div><br /></div><div>Interleaved, Inverted & Compressed & a simple encryption?</div><div><br /></div><h4 style="text-align: left;">Time differentiated : Interleave, Inversion & differentiating Elliptic curve.</h4><br />We will be able to know and test the Cypher : PRINCIPLE OF INTENT TO TRUST<br /><br />We know of a cypher but : (Principle RS)<br /><br /></div><div>We blend the cypher..<br />Interleaved pages of a cypher obfuscate : PAL CScam does this<br /><br />Timed : Theoretically unique to you in principle for imprecision, But we cannot really have imprecise in Crypto!<br /><br />But we can have a set time & in effect Elliptic curve a transient variable T,<br />With this, Interleave the resulting pages (RAM Buffer Concept)<br /><br />Invert them over Time Var = T<br /><br />We can do all & principally this is relatively simple.<br /><br />(c)RS</div><div><br /></div><div><div>*</div><br /><h4 style="text-align: left;">Modulus Dual Encrypt & Decrypt package : Processor feature (c)RS</h4><br />AES-CCM & AES-GCM & Other Cypher Modulus + CCM & GCM can be accelerated with a joint AES Crypto module,<br /><br />Processor feature & package : Module list:<br /><br />2 Decryption pipelines working in parallel,<br />With a Shared cache & RAM Module<br />Modulus & Semi-parallel modulating decryption & Encryption combined with Encapsulation Cypher IP Protocol packet</div><div><br /></div><div><h4 style="text-align: left;">Parallax Cryptographic Processing Unit: RS</h4><br />The capacity To Multiply decryption on specific hardware in situations such as lower Bit precision is to be implemented as follows:<br /><br />On AES-NI & ARM Cryptographic processors; In particular PSP+PPS(ARM+) & SiMD ..<br /><br />The capacity to exploit the fact that the nonce is 16Bit to 64Bit & full float upto 128Bit for legal decryption (client) means there is a simple method to use:<br /><br />In situations that a AES-NI & ARM Cryptographic unit can process 2 threads on a 256Bit Function we can do both the main 128Bit/192Bit & the nonce 16Bit to 64Bit & Enable a single instruction Roll to Synchronise both The main HASH & Nonce.<br /><br />AES & Crypto hardware can utilise the CPU/GPU/Processor FPU & SiMD to decrypt the nonce (smaller so fast) & in the same 8bto to 64Bits of code; Inline & parallax the cryptographic function.<br /><br />With a 256Bit AES-NI & Cryptographic unit : Parallel Decryption & Return Encryption by using 2x 128Bit & a Processor Enciphered Nonce.</div><div><br /></div><div><h4 style="text-align: left;">Security Relevant Extensions</h4>SVM : Elliptic Curves & Polynomial graphs & function<br />AES : Advanced Encryption Standard Functions<br />AVX : 32Bit to 256Bit parallel Vector Mathematics<br />FPU : IEEE Float Maths<br />F16b : 16Bit to 32Bit Standards Floats<br />RDTSCP : Very high precision time & stamp<br /><br />Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1</div><div><br /></div><div>32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)<br />(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second</div><div><br /></div><h4 style="text-align: left;">AES & Elliptic Hardware Acceleration : AES & SVM along with AVX Micro-block decoding.</h4><br />ECC Elliptic Curve encrypt is 20% to 40% more efficient than Large Size RSA AES on game packets @ QUICC<br />512/384/256 AES Elliptic is clearly advantageous because of compression block size on small network packets,</div><div><br />Larger streams such as video clearly favour 2048 Bit RSA AES; With SVM Elliptic feature,</div><div><br /></div><div>RSA,512, 384 AES Elliptic curve is a clear winner!</div><div><br /><div>(c)Rupert S</div><div><br />*reference*</div><div><br /></div><div><div><a href="https://science.n-helix.com/2022/02/interrupt-entropy.html">https://science.n-helix.com/2022/02/interrupt-entropy.html</a></div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a></div><div><a href="https://science.n-helix.com/2022/01/ntp.html">https://science.n-helix.com/2022/01/ntp.html</a></div><br />Performance Comparison of AES-CCM and AES-GCM Authenticated Encryption Modes <br />http://worldcomp-proceedings.com/proc/p2016/SAM9746.pdf<br /><br />Basic comparison of Modes for Authenticated-Encryption -IAPM, XCBC, OCB, CCM, EAX, CWC, GCM, PCFB, CS<br />https://www.fi.muni.cz/~xsvenda/docs/AE_comparison_ipics04.pdf<br /><br />*<br /><h4 style="text-align: left;">Example Encryption Results:</h4><br />gnutls-cli --benchmark-tls-ciphers<br /><br />Testing throughput in cipher/MAC combinations (payload: 1400 bytes)<br /><br /> AES-128-GCM - TLS1.2 0.56 GB/sec<br /> AES-128-GCM - TLS1.3 0.57 GB/sec<br /> AES-128-CCM - TLS1.2 185.36 MB/sec<br /> AES-128-CCM - TLS1.3 182.74 MB/sec<br /> CHACHA20-POLY1305 - TLS1.2 112.79 MB/sec<br /> CHACHA20-POLY1305 - TLS1.3 111.61 MB/sec<br /> AES-128-CBC - TLS1.0 168.16 MB/sec<br /> CAMELLIA-128-CBC - TLS1.0 53.82 MB/sec<br /> GOST28147-TC26Z-CNT - TLS1.2 15.39 MB/sec<br /><br />As can be seen:<br /><br />AES-GCM is <br />1056x better than Camellia & <br />508x Better than ChaChaPoly <br />309x Better than AES-CCM<br /><br /></div><div>So what about ChaChaGCM?<br /><br />RS</div><div><br />*<div><br /></div><div>Example of use:</div><div><br /></div><div>Nostalgic TriBand : Independence RADIO : Send : Receive :Rebel-you trade marker<br /><br />Nostalgic TriBand 5hz banding 2 to 5 bands, Close proximity..<br />Interleaved channel BAND.<br /><br />Microchip clock and 50Mhz Risc Rio processor : 8Bit : 16Bit : 18Bit<br />Coprocessor digital channel selector &<br /><br />channel Key selection based on unique..<br /><br />Crystal time Quartz with Synced Tick (Regulated & modular)<br /><br />All digital interface and resistor ring channel & sync selector with<br />micro band tuning firmware.<br /><br />(c)Rupert S</div><div><br /></div><div>*</div><div><br /></div><div>Good for cables ? and noise ?</div></div><div><br /></div><div><div>Presenting : IiCE-SSR for digital channel infrastructure & cables</div><div><Yes Even The Internet &+ Ethernet 5 Band></div><div><br /></div><div>So the question of interleaved Bands & or signal inversion is a simple</div><div>question but we have,</div><div><br /></div><div>SSD & HDD Cables & does signal inversion help us? Do interleaving bands help us?</div><div><br /></div><div>In Audio inversion would be a strange way to hear! but the inversion</div><div>does help alleviate ...</div><div><br /></div><div>Transistor emission fatigue...</div><div><br /></div><div>IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol</div><div><br /></div><div>Interleaved signals help Isolate noise from a Signal Send & Receive ...</div><div><br /></div><div>Overlapping inverted waves are a profile for complex audio & FFT is the result.</div><div><br /></div><div>Interleaved, Inverted & Compressed & a simple encryption?</div><div><br /></div><div>Good for cables ? and noise ?</div><div><br /></div>Presenting : IiCE for digital channel infrastructure & cables <Yes<br />Even The Internet &+ Ethernet 5 Band><br /><br />(c) Rupert S</div><div><br /></div>*<br />Given the ZFS Results the strategy to utilize (c)RS<br /><br /><h3 style="text-align: left;">Crypto Storage & RAM Strategy (c)RS</h3><br />GCM : Accelerated by SVM Elliptic Curve & AES & ARM Crypto-Extensions,<br />Processor Compression Accelerated,<br /><br />2 to 64 Blocks,<br />Header Separated; GZIP, BZip & LZ8 & LZH & Wavelet & Hardware Compression with independent Encrypted Segmentation & Sub-Grouping.<br /><br />Hash main block group listing & Tables for drive repair and DIR & Access Acceleration.<br /><br />https://www.medo64.com/content/media/ubuntu-2204-zfs-speed.png<br />AES-128-GCM - TLS1.2 0.56 GB/sec<br />AES-128-GCM - TLS1.3 0.57 GB/sec</div><div><br /></div><div>*<div><br /></div><div>https://science.n-helix.com/2018/12/rng.html<br /><br />https://science.n-helix.com/2022/02/rdseed.html<br /><br />https://science.n-helix.com/2017/04/rng-and-random-web.html<br /><br />https://science.n-helix.com/2022/02/interrupt-entropy.html<br /><br />https://science.n-helix.com/2021/11/monticarlo-workload-selector.html<br /><br />https://science.n-helix.com/2022/03/security-aspect-leaf-hash-identifiers.html</div><div><br /></div><a href="https://www.fi.muni.cz/~xsvenda/docs/AE_comparison_ipics04.pdf" target="_blank">Basic comparison of Modes for Authenticated-Encryption -IAPM, XCBC, OCB, CCM, EAX, CWC, GCM, PCFB, CS</a><div><br /></div><div><br /></div><div>Integral to Telecoms Security TRNG<br /><br />*RAND OP Ubuntu : https://manpages.ubuntu.com/manpages/trusty/man1/pollinate.1.html<br /><br />https://pollinate.n-helix.com</div><div><br /></div>*<br /><br /><h4 style="text-align: left;">Audio, Visual & Bluetooth & Headset & mobile developments only go so far:</h4><br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html</div><div><br /></div><div>https://science.n-helix.com/2021/11/ihmtes.html<br /><br />https://science.n-helix.com/2022/03/ice-ssrtp.html<br /><br />https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html<br />https://science.n-helix.com/2021/11/wave-focus-anc.html<br />https://science.n-helix.com/2021/12/3d-audio-plugin.html<br /><br />*<div><br /><h4 style="text-align: left;">***** Dukes Of THRUST ******</h4><br />Nostalgic TriBand : Independence RADIO : Send : Receive :Rebel-you trade markerz<br /><br />Nostalgic TriBand 5hz banding 2 to 5 bands, Close proximity..<br />Interleaved channel BAND.<br /><br />Microchip clock and 50Mhz Risc Rio processor : 8Bit : 16Bit : 18Bit<br />Coprocessor digital channel selector &<br /><br />channel Key selection based on unique..<br /><br />Crystal time Quartz with Synced Tick (Regulated & modular)<br /><br />All digital interface and resistor ring channel & sync selector with<br />micro band tuning firmware.<br /><br />(c)Rupert S</div><div><br /></div><div>Dev/Random : Importance<br /><br />Dev/Random : Importance : Our C/T/RNG Can Help GEA-2 Open Software implementation of 3 Bits (T/RNG) Not 1 : We need Chaos : GEA-1 and GEA-2 Implementations we will improve with our /Dev/Random<br /><br />Our C/T/RNG Can Help GEA-2 Open Software implementation of 3 Bits<br />(T/RNG) Not 1 : We need Chaos : GEA-1 and GEA-2 Implementations we<br />will improve with our /Dev/Random<br /><br />We can improve GPRS 2G to 5G networks still need to save power, GPRS<br />Doubles a phones capacity to run all day,<br /><br />Code can and will be improved, Proposals include:<br /><br />Blake2<br />ChaCha<br />SM4<br />SHA2<br />SHA3<br /><br />Elliptic Encipher<br />AES<br />Poly ChaCha<br /><br />Firstly we need a good solid & stable /dev/random<br /><br />So we can examine the issue with a true SEED!<br /><br />Rupert S https://science.n-helix.com/2022/02/interrupt-entropy.html<br /><br />TRNG Samples & Method DRAND Proud!<br /><br />https://drive.google.com/file/d/1b_Sl1oI7qTlc6__ihLt-N601nyLsY7QU/view?usp=drive_web<br />https://drive.google.com/file/d/1yi4ERt0xdPc9ooh9vWrPY1LV_eXV-1Wc/view?usp=drive_web<br />https://drive.google.com/file/d/11dKUNl0ngouSIJzOD92lO546tfGwC0tu/view?usp=drive_web<br />https://drive.google.com/file/d/10a0E4Gh5S-itzBVh0fOaxS7JS9ru-68T/view?usp=drive_web<br /><br />https://github.com/P1sec/gea-implementation<br /><br />"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension<br />of GEA-1 with a higher amount of processing, and apparently not<br />weakened) are bit-oriented stream ciphers."<br /><br />"A stream cipher, such as the well-known RC4 or GEA-1, usually works<br />through using the Xor operation against a plaintext. The Xor operation<br />being symmetrical, this means that encrypting should be considered the<br />same operation as decrypting: GEA-1 and GEA-2 are basically<br />pseudo-random data generators, taking a seed (the key, IV and<br />direction bit of the GPRS data, which are concatenated),<div><br /><div>The generated random data (the keystream) is xored with the clear-text<br />data (the plaintext) for encrypting. Then, later, the keystream is<br />xored with the encrypted data (the ciphertext) for decrypting. That is<br />why the functions called in the target library for decrypting and<br />encrypting are the same.<br /><br />GEA-1 and GEA-2 are bit-oriented, unlike RC4 which is byte-oriented,<br />because their algorithms generate only one bit of pseudo-random data<br />at once (derived from their internal state), while algorithms like RC4<br />generate no less than one byte at once (in RC4's case, derived from<br /><br />permutation done in its internal state). Even though the keystream<br />bits are put together by the current encryption / decryption C and<br />Rust libraries into bytes in order to generate usable keystream,<br />obviously.<br /><br />Based on this, you can understand that GEA-1 and GEA-2 are LFSR:<br />Linear Feedback Shift Register-oriented ciphers, because their<br />internal state is stored into fixed-size registers. This includes the<br />S and W registers which serve for initialization / key scheduling<br />purposes and are respectively 64 and 97-bit wide registers, and the A,<br />B, C (and for GEA-2 only D) registers which serve for the purpose of<br />keystream generation, which are respectively 31, 32, 33 and 29-bit<br />wide registers.<br /><br />On each iteration of the keystream generation, each register is<br />bit-wise rotated by one position, while the bit being rotated from the<br />left towards the right side (or conversely depending on in which bit<br />order you internally represent your registers) is fed back to the<br />algorithm and mutated depending on given conditions. Hence, the<br /><br />shifted-out bit is derived from other processing, and reinserted,<br />while being for this reason possibly flipped depending on conditions<br />depending on bits present at the other side of the given register.<br /><br /><div>This is the explanation for the name of linear feedback shift register<br />(shift because of the shift operation required for the rotation, and<br />linear feedback because of the constant-time transform operation<br />involved).<br /><br />The rest of the register may also be mutated at each iteration steps,<br />as in the case of the GEA-1 and 2, whole fixed Xor sequences (which<br />differ for each register) may be applied depending on whether the<br />rotated bit is a 0 or a 1.<br /><br />Note that a step where the register iterates is called clocking (the<br />register is clocked), and that the fixed points where the register may<br />be Xor'ed when the rotated bit becomes a 1 are called taps. The linear<br />function which may transmute the rotated bit at the clocking step<br />(taking several bits of the original register as an input) is called<br />the F function.<br /><br />Those kind of bit-oriented LFSR algorithms, such as GEA-1 and 2 (for<br />GPRS) and A5/1 and 2 (for GSM), were designed this way for optimal<br />hardware implementations in the late 80's and early 90's."</div><div><br /></div><div>*****</div><div><br /></div><div><div><div>IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol</div><div><br /></div><div>Interleaved signals help Isolate noise from a Signal Send & Receive ...</div><div><br /></div><div>Overlapping inverted waves are a profile for complex audio & FFT is the result.</div><div><br /></div><div>Interleaved, Inverted & Compressed & a simple encryption?</div><div><br /></div><div>Good for cables ? and noise ?</div></div><div><br /></div><div><div>Presenting : IiCE-SSR for digital channel infrastructure & cables</div><div><Yes Even The Internet &+ Ethernet 5 Band></div><div><br /></div><div>So the question of interleaved Bands & or signal inversion is a simple</div><div>question but we have,</div><div><br /></div><div>SSD & HDD Cables & does signal inversion help us? Do interleaving bands help us?</div><div><br /></div><div>In Audio inversion would be a strange way to hear! but the inversion</div><div>does help alleviate ...</div><div><br /></div><div>Transistor emission fatigue...</div><div><br /></div><div>IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol</div><div><br /></div><div>Interleaved signals help Isolate noise from a Signal Send & Receive ...</div><div><br /></div><div>Overlapping inverted waves are a profile for complex audio & FFT is the result.</div><div><br /></div><div>Interleaved, Inverted & Compressed & a simple encryption?</div><div><br /></div><div>Good for cables ? and noise ?</div><div><br /></div>Presenting : IiCE for digital channel infrastructure & cables <Yes<br />Even The Internet &+ Ethernet 5 Band><br /><br />(c) Rupert S</div><br /><br /></div></div></div></div></div></div></div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-71152427256814996302022-03-22T11:44:00.009+01:002022-03-22T14:09:55.642+01:00Security Aspect Leaf HASH Identifiers<div>VM Virtual Call Frame : Security Aspect Leaf HASH Identifiers : Rupert S</div><div><br /></div>Leaf HASH Identifiers in 16Bit/32Bit/64Bit : RS<br /><br />With this example in mind 16Bit HASH Values & identifiers make sense.<br /><br />16Bit HASH Reasoning Table: based upon Leaf HASH Identifiers in 16Bit/32Bit/64Bit<br /><br />16Bit Leaf HASH, Compatible max RAM) : 4GB Large Page<br /><br />16 Million HASH groups for identifiers with 128MB RAM per HASH Master group..<br /><br />256 HASH master Table<br />256 HASH Per Group<br /><br />16:32MB up to 4GB(16Bit Leaf HASH, Compatible max RAM) : RAM per group<br /><br />16Bit Hash identifier tables load into 16KB of processor cache<br />Load, Save & Store can be done in a higher Bit depth; 32Bit for example<br />SiMD can operate in Half, Single & Double Float capacity<br /><br />Micro work loads such as motion & video & 3D Tessellation<br /><br />*<br /><br />VM Virtual Call Frame : Security Aspect Leaf HASH Identifiers in 16Bit/32Bit/64Bit : RS<br /><br />If the CPU Manager can call Compression & Cypher independently on TASK Call,<br />If the Processor Manager can call from Virtualisation functions for each secure task group.<br /><br />Security Aspect : With CPU Cache in the 8MB+ Region Leaf HASH Identifiers can be stored:<br /><br /><div>Compressed if Processor has Compression such as BZip<br />Encrypted Compressed if Processor has Compression such as AES<br /><br />In a Secure &+ Work Isolation Container : WIC or SWIC contained L2 (Compress Store Small Identifier List)<br /><br />In a Secure &+ Work Isolation Container : WIC or SWIC contained L3 (larger identifier lists), <br /><br />(c)Rupert S<br /><br />Reference Kernel Security:</div><div><br />https://science.n-helix.com/2021/11/monticarlo-workload-selector.html<br /><br />https://science.n-helix.com/2022/02/interrupt-entropy.html<br /><br />https://science.n-helix.com/2018/12/rng.html<br /><br />https://science.n-helix.com/2022/02/rdseed.html<br /><br />https://science.n-helix.com/2017/04/rng-and-random-web.html</div><div><br /></div><div>Leaf HASH Identifier Paths to clear logic:</div><div><br /></div><div>Performance issues related to handheld would be solved with the use of:<br /><br />FP16 packed pixel<br />FP16 background object maths<br />FP/Int8/4 Machine learning adaptive code...<br />Compute Shaders<br />Compression > DOT Image format<br /><br />With these resources available, We can potentially do more!</div><div><br /></div><div><div>https://science.n-helix.com/2019/06/vulkan-stack.html</div><div>https://science.n-helix.com/2022/03/fsr-focal-length.html</div><div>https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html</div><div>https://science.n-helix.com/2022/03/simd-render.html</div></div><div><br /><div>*</div><div>https://science.n-helix.com/2019/06/kernel.html</div><div><br /></div><div>Trace ID : Kernel & Bios HASH Reference</div><div>https://lkml.org/lkml/2022/3/22/446</div><div><br /></div><div>Jumpless Security HASH</div><div>https://lkml.org/lkml/2022/3/22/440</div><div><br /></div><div><div>SPE Decode & Encode</div><div>https://lkml.org/lkml/2022/3/22/415</div></div><div><br /></div><div><div>IDR Transaction ID's VMBus : HASH</div><div>https://lkml.org/lkml/2022/3/22/459</div></div><div>*</div></div><div><br /></div><div>As you know in my studies i found that 16x AA rarely has a performance hit on all verified hardware since RX200 3GB (and the RX560) & even the RX5770 1GB.The NVidia 1080 can manage most of this & i optimised Elite Dangerous for the 1080 & RX200 market.<br /><br /><br />A lot of the performance issues related to handheld would be solved with the use of:<br /><br />FP16 packed pixel<br />FP16 background object maths<br />FP/Int8/4 Machine learning adaptive code...<br />Compute Shaders<br />Compression > DOT Image format<br /><br />With these resources available, We can potentially do more!</div><div><br /></div><div>*</div><div><br /></div><div>"Apex Legends : I get the feeling that the lower final precision on the screen output is the result of a 4x Anti Aliasing layer and lower Image compression settings,"<br /><br />*</div><div><br />Elite Dangerous Reference Videos:https://www.youtube.com/watch?v=JmMQPS_azJA&list=PL8DNvgnwiUU1cezx_Y9DraHjyqJxnrrN7<br /><br />ML & Game performance improvement https://is.gd/ProcessorLasso<br /><br />Rupert S<br /><br />The Handheld market performance ratings are :<br /><br />Snapdragon (often used & is good)<br /><br />High quality option based upon Notebook expectations<br /><br />AMD Chipset<br />NVidia<br /><br />My studies concluded that both NVidia and AMD have little to worry about AA performance upto 16x and it makes almost no performance advantage to use less in my performance tuning...<br /><br />I am frequently in possession of older hardware; Like many users i cannot always afford all the best gear,<br /><br />However there are examples of things that make a bigger hit:<br /><br />16x tessellation rarely causes a problem (RX200 3GB+)24 & 32 both dynamically jiggle FPS around heavy asteroids & space stations in frontier elite.. <br /><br />but looks amazing!<br /><br />Multisampling is manageable at 2x on RX200 on elite dangerous <br /><br />(a quite intense graphic space MMO)<br />4x MultiSampling does involve a 20% frame rate drop, Quality is preferred but i went for 2x as it rarely causes issues.<br /><br />Texture Image compression format optimisation is a priority NO.1 Priority..<br /><br />You save a lot of space & heavy usage of DOT 1 > 5 compression management is advised..<br />10Bit sampling is perfectly logical.<br /><br />https://www.nintendolife.com/news/2021/03/video_check_out_this_side-by-side_comparison_of_apex_legends_running_on_switch_and_ps4_pro<br /><br />https://www.youtube.com/watch?v=uGrPwt_KHRE<br /><br />Elite Dangerous 64Bit PvP Arena DeathMatch 4Q 2xMultiSampling.mp4 (93.26 MB) https://mirrorace.org/m/6qr3y<br /><br />Elite Dangerous 64 Sub.FM Rastafari PvP 2016-04-23 19-27-22-552.mp4 (89.27 MB) https://mirrorace.org/m/54waA<br /><br />EliteDangerous - CQC PvP Arena - Bloody is the bath of kings - 2016-05-05 14-30-27-909.mp4 (277.04 MB) https://mirrorace.org/m/3IO7p<br /><br />yes cloudflare apex_eoso.nx7v.icu apex_eu.nx7v.icu apex_wes.nx7v.icu apex_eas.nx7v.icu <br /><br />USA: pop: apex_sv1.nx7v.icu apex_sv2.nx7v.icu apex_sv3.nx7v.icu<br /><br />*<br /><br /></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-87981884442377623352022-03-10T13:06:00.003+01:002022-04-16T16:55:20.615+02:00SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts<h3 style="text-align: left;">VESA Standards : Vector Graphics, Boxes, Ellipses, Curves & Fonts : Consolas & other brilliant fonts : (c)RS</h3><div>SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts<br /><br />Improve Console & TV & BIOS & General Animated Render<br /><br />Vector Display Standards with low relative CPU Weight<div>SiMD Polygon Font Method Render<br /><br />Default option point scaling (the space) : Metadata Vector Fonts with Curl mathematical vector :<br /><br />16 Bit : SiMD 1 width<br />32 Bit : SiMD Double Width<br /><br />High precision for AVX 32Bit to 256Bit width precision.<br /><br />Vectoring with SiMD allows traditional CPU mastered VESA Emulation desktops & safe mode to be super fast & displays to conform to VESA render standards with little effort & a 1MB Table ROM.<br /><br /><a href="https://science.n-helix.com/2022/04/vecsr.html">https://science.n-helix.com/2022/04/vecsr.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2016/04/3d-desktop-virtualization.html">https://science.n-helix.com/2016/04/3d-desktop-virtualization.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2019/06/kernel.html">https://science.n-helix.com/2019/06/kernel.html</a></div><div><br /></div><div><a href="https://science.n-helix.com/2022/03/fsr-focal-length.html">https://science.n-helix.com/2022/03/fsr-focal-length.html</a><br /><br /><a href="https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html">https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html</a><br /><br />*<div><br /><h4 style="text-align: left;">*Application of SiMD Polygon Font Method Render</h4>*3D Render method with Console input DEMO : RS<br /><br />3D Display access to correct display of fonts at angles in games & apps without Utilizing 3rd Axis maths on a simple Shape polygon Vector font or shape. (c)Rupert S<br /><br />3rd dimensional access with vector fonts by a simple method:<br /><br />Render text to virtual screen layer AKA a fully rendered monochrome, 2 colour or multi colour..<br /><br />Bitmap/Texture, <br /><br />Due to latency we have 3 frames ahead to render to bitmap DPT 3 / Dot 5<br /><br />Can be higher resolution & we can sub sample with closer view priority...<br /><br />We then rotate the texture on our output polygon & factor size differential.<br /><br />The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize<br /><br />Why ? Because rotating a polygon is harder than subtracting or adding width, Hight & direction to fully complex polygon Fonts & Polygon lines or curves...<br /><br />The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize.</div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-86079549017876207382022-03-05T09:33:00.012+01:002022-12-03T01:22:10.315+01:00FSR-Focal LengthFast FSR-Focal Length Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS<br /><br />FSR Focal Length Box Image Scaling Sharpening & blurring &or expansion with mathematical sharpening interpolation (c)Rupert S<br /><br />*<br /><br />Some photos of L2, Close to L2 may be an impossible focus; Unless image enhancement is used<br />(Sharpening & light angle mathematical focal length shift<br />(Computational Focal Length Sharpening Enhanced by Ray-Tracing)<br /><br />*<div><br />We need to utilize diffraction & ray dispersion mathematics from physics,<br />For example for opaque surfaces & water ripples; Or by our personal preference lenses <br /><br />For digital image focusing, Sharpening, Clarity & Depth Of Field DOF, <br />& When processing photos, video & art.<br /><br />For this we present: Fast FSR-Focal Length; <br />With the intention of Sharply defined focus & processing.<br /><br />*</div><div><br />Fast FSR-Focal Length Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS<br /><br />& FSR Focal Length Box Image Scaling Sharpening & blurring &or expansion with mathematical sharpening interpolation (c)Rupert S<br /><br />3d Graphics, Frame Render & Texture Image enhancement:<br /><br />(Sharpening & light angle mathematical focal length shift<br />(Computational Focal Length Sharpening Enhanced by Ray-Tracing)<br /><br />Focal length works by expanding an image by the refraction index,<br />In Figure 1 a simple example is offered:<br /><br />fig 1 (I)=Light Ray Path (===)=lens<br /><br /><div><br /></div><div><span style="white-space: pre;"> </span>(object or image)</div><div><span style="white-space: pre;"> </span> I<span style="white-space: pre;"> </span>I</div><div><span style="white-space: pre;"> </span>I<span style="white-space: pre;"> </span> I</div><div><span style="white-space: pre;"> </span> I =============== I</div><div><span style="white-space: pre;"> </span>\<span style="white-space: pre;"> </span> /</div><div><span style="white-space: pre;"> </span> =======================</div><div><span style="white-space: pre;"> </span>==I===I===I===I==I==</div><div><span style="white-space: pre;"> </span> =====================</div><div><span style="white-space: pre;"> </span> / I / I \ / I \ I \</div><div><br /></div><br /><a href="https://bit.ly/VESA_BT">https://bit.ly/VESA_BT</a><div><br /></div><div><a href="https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html">https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html</a></div><div><br /></div><div><div>https://science.n-helix.com/2022/03/fsr-focal-length.html</div><div>https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html</div><div>https://science.n-helix.com/2022/03/simd-render.html</div><div>https://science.n-helix.com/2019/06/vulkan-stack.html</div><div><br /></div><div>https://github.com/GPUOpen-Effects/FidelityFX-FSR2/releases/tag/v2.0.1a</div><div>https://github.com/GPUOpen-Effects/FidelityFX-FSR/releases/tag/v1.0.2</div><br />Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS<br /><br />We utilize refraction, Expansion & Compression math code to work out the Image formed on the other side..<br /><br />With Refraction & Reflection Simplex Raytracing models (15 to 400 Rays normally)..<br /><br />We are able to sharpen or blur a scene by depth or by focus or by density or optical capacities of materials & matter or curvature for water surfaces..<br /><br />To simplify matters for computational performance we work out the multiplication or division factors involved in compressing or expanding the image or audio compared to the perspective of the perceiver, Viewer or camera, Ear or Eye or infact sensation.<br /><br />FSR & FSR-FL (Camera lens & CMOS Sharpening & Focus adjustment)<br /><br />Methods To clarify (Hardware)<br /><br />OpenCL (Microsoft CL pack is available to DX12 V11 Devices to OPenCL 1.2 + Khronos)<br /><br />SiMD, AVX-256, AVX-512(bit) FPU(183Bit + 256 on Epyc Zen3)<br />Precision Double, Precision Single Float<br /><br />Ray-Tracing SiMD (Such as PS5 & XBox & RX5770 :2019+)<br /><br />PhysicsX (NVidia & CPU)<br /><br />Also works for Thrust & Curvature motion & momentum.<br /><br />Rupert S<br /><br />(c)Rupert S https://science.n-helix.com<br /><br />*<br /><br />FSR-FL Magnifex3D(tm)RS<br /><br />3d image Phase differentiation through differential : Magnifex3D(tm)RS<br /><br />The objective of this phase is to create 2 objectives:<br /><br />3D positioning & shape<br />Focus the image or sound impression<br /><br />FSR-FL Calculations of diffraction do 2 things:<br /><br />Focus the image around 0.00+-3<br />Calculate Distance & 3D Parameters though Differential Diffraction<br /><br />The same can be stated of audio & the parameters are the same in effect.<br /><br />3d image Phase differentiation through differential : Magnifex3D(tm) (c) Rupert S https://science.n-helix.com<br /><br />3d image including distance : WEBB : During the watching of this video<br /><br />James Webb Telescope shares first focused Image of star HD 84406<br />https://www.youtube.com/watch?v=-wo_AT8pR6o<br /><br />It came to my attention that 18 segments obviously produce location specific data,<br />Additional calculations would be required to calculate distance though ARC<br /><br />List<br /><br />18 Diverse ANGLES<br /><br />1 View<br /><br />18 impressions of star HD 84406<br /><br />Phase decouple a single frame per 17 produces a 3D image with distance...<br /><br />Calculating the 18 mirror Angle differentials with slightly different data will create a 3D view,<br /><br />For example of a chemical; A multiple angle refraction image results in a 3D image.<br /><br />Common Usage : 3D<br /><br />Magnifiers, Telescopes, Microscopes, Atomic Wave Analysis.</div><div><br /></div>*<div><br />Research topic RS : https://is.gd/Dot5CodecGPU https://is.gd/CodecDolby https://is.gd/CodecHDR_WCG https://is.gd/HPDigitalWavelet https://is.gd/DisplaySourceCode<br /><br />*<br />Sharp Blur Depth Perception : (c)RS</div><div><h4 style="text-align: left;">FSR FL Sharp Blur Depth Perception : (c)RS 3D From 2D for eyes</h4><br />For the re-creation of 3D Geometry from a single focus viewer point & abstracting of 3D & 4D viewpoints on more viewpoints & inferencing of camera shake in 3D Geometry realisation.<br /><br />Focus a lens & the sharpest bit is in focus; Indeed we can improve focus by searching mathematically for sharpness..<br />Once we understand how this works.<br /><br />A lens group set to focus at 1 Meter (50mm Lens example) has a sharp content in the 1m range..<br />Things that are closer are blurred a little; But the blur is a wavelet examination away from 3D!<br /><br />We know that subjects in focus have an ideal perfect sharpness.<br />When we know the lens used we may prove focus depth; We can then prove how close or far away objects are in the photo! How ?<br /><br />Sharpness & blur examination.<br /><br />A human eye has an average Sharp range of around 6cm of depth variance; So we can judge depth by observing if the object is in the foreground (Side to side scan: Habitual)..<br /><br />Mathematically provable sharpness in range of the focusing point if ISO, Focal Width & focus length are known,<br /><br />We can therefore assess how close things are by focusing to know distances & depths,<br />The further away the subject content is the slower sharpness is lost over distance.<br /><br />Close focusing brings the angle closer to the triangle & therefore objects further away are quickly blurry if further away.<br /><br />Long focus is a === linear view & focus sharpness varies slightly over distance.<br /><br />*</div><div><a href="https://is.gd/LEDSource">https://is.gd/LEDSource</a><br /><br />Utility of FSR-FL-RT<br />Minimal Process Compute<br />Fast FSR-Focal Length Ray-Tracing Code<br /><br />Portable OpenCL<br />OpenCL may be ideal for TV & Device, Display & Audio rendering & Upscaling with integral POCCL Support<br /><br /><a href="https://is.gd/DisplaySourceCode">https://is.gd/DisplaySourceCode</a><br /><br />https://aka.ms/clglcp-faq<br />http://portablecl.org/<br />https://github.com/pocl/pocl<br /><br /><a href="https://apps.microsoft.com/store/detail/9NQPSL29BFFF?hl=en-us&gl=US">https://apps.microsoft.com/store/detail/9NQPSL29BFFF?hl=en-us&gl=US</a><br /><br /><a href="http://portablecl.org/downloads/pocl-3.0.tar.gz">http://portablecl.org/downloads/pocl-3.0.tar.gz</a></div></div><div><br /></div><h4 style="text-align: left;">Fast FSR-Focal Length Ray-Tracing for 3D realisation (c)Rupert S</h4><br />Fast FSR-Focal Length Ray-Tracing with dynamic contrast emulation<br />Fast FSR-Focal Length Ray-Tracing with dynamic contrast 3D Shaped LED emulation<br />Fast FSR-Focal Length Ray-Tracing with dynamic contrast emulation & 3D Directional DOT Bead for micro deformation pixel 3D Holography<br /><br />Fast FSR-Focal Length Ray-Tracing for 3D realisation though depth emulation & light angle (LED Glass) replication; Such as side by side shaping of the LED,<br />So that eyes are different due to angle require processing<br /><br />Fast FSR-Focal Length Ray-Tracing with dynamic contrast 3D Shaped LED emulation<br /><br />Side by Side LED, Left & Right & Up and Down matrix around a tiny refraction curvature..<br />Create a 3D Image<br />|_[_]_|<br />|_[_]_| Lenses on top<br />|_[_]_|<br /><br />Fast FSR-Focal Length Ray-Tracing with dynamic contrast emulation & 3D Directional DOT Bead for micro deformation pixel 3D Holography<br /><br />3D micro bump with a higher index wide angle, the light comes from multiple LED Colours & can be mathematically shaped to curve the LED 6/9/12 pattern into a blend that a single pixel looks of all colours.<br /><br />(_O_)<br />(_O_) Lenses on top<br />(_O_)<br /><br /><h4 style="text-align: left;">4 primary colour composure: RS</h4><br />What does decomposing a frame into 4 colour groups mean?<br />Red, Green, Blue, Grayscale<br />Each pixel on a screen has 4 colour components & they are on a different place on the screen,<br />So when we sharpen; We sharpen to the closest pixel LED of the right colour, <br />Obtaining the best colour with the most logical of LED content,<br />the right colour sharpened for the right LED<div><br />(c)RS<br /><div><br /></div><h4 style="text-align: left;">Drill texture & image format (with contrast & depth enhancement)</h4><br /><a href="https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing">https://drive.google.com/file/d/1G71Vd9d3wimVi8OkSk7Jkt6NtPB64PCG/view?usp=sharing</a><br /><a href="https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing">https://drive.google.com/file/d/1u2Qa7OVbSKIpwn24I7YDbwp2xdbjIOEo/view?usp=sharing</a><br /><br /><a href="https://science.n-helix.com/2022/08/simd.html">https://science.n-helix.com/2022/08/simd.html</a><br /><br />Research topic RS : <a href="https://is.gd/Dot5CodecGPU">https://is.gd/Dot5CodecGPU</a> <a href="https://is.gd/CodecDolby">https://is.gd/CodecDolby</a> <a href="https://is.gd/CodecHDR_WCG">https://is.gd/CodecHDR_WCG</a> <a href="https://is.gd/HPDigitalWavelet">https://is.gd/HPDigitalWavelet</a> <a href="https://is.gd/DisplaySourceCode">https://is.gd/DisplaySourceCode</a></div><div><br /></div>*****<br /><br /><h4 style="text-align: left;">FSR_FL RT: Proven</h4>ML Training Telescope, Camera, Video & Image Display Enhancement, Produced 2 Hours ago! 2022-12-02 <a href="https://www.science.org/doi/pdf/10.1126/sciadv.add3433?download=true">https://www.science.org/doi/pdf/10.1126/sciadv.add3433?download=true</a><br /><br /><a href="https://is.gd/MLCodecShaping">https://is.gd/MLCodecShaping</a><br /><br />https://science.n-helix.com/2022/03/fsr-focal-length.html<br />https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html<br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html<br />https://science.n-helix.com/2019/06/vulkan-stack.html<br /><br />https://science.n-helix.com/2022/03/simd-render.html<br /><br />https://science.n-helix.com/2022/09/ovccans.html<br />https://science.n-helix.com/2022/11/frame-expand-gen-3.html<br />https://science.n-helix.com/2022/10/ml.html<br /><br />https://science.n-helix.com/2022/08/jit-dongle.html<br />https://science.n-helix.com/2022/06/jit-compiler.htmlRed Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0tag:blogger.com,1999:blog-7073760888741218176.post-69631618454878156092022-02-18T20:57:00.035+01:002023-09-24T23:41:02.894+02:00Interrupt Entropy<h4 style="text-align: left;">NT Interrupt counter Entropy : A counter theory : RS</h4><br />"more importantly, our<br />distribution is not 2-monotone like NT's, because in addition to the<br />cycle counter, we also include in those 4 words a register value, a<br />return address, and an inverted jiffies. (Whether capturing anything<br />beyond the cycle counter in the interrupt handler is even adding much of<br />value is a question for a different time.)"<br /><br />NT Interrupt counter Entropy : A counter theory : RS<br /><br />To be clear interrupts are old fashioned (NT & Bios) : Points<br /><br />Network cards have offloading? Yes & why cannot we?<br /><br />Offloaded does not mean that a time differential matrix HASH AES of 32Bit words,<br />Cross pollinated though MMX, AVX , SiMD is plausible!<br /><br />Combined with even network latency timing & interrupt latency...<br /><br />Various system differentials can alternate line in our table per clock sync!<br /><br />In this reference Quartz clock instability is not only counter acted by NTP...<br />But also utilized as a variable co-modifier.<br /><br />So why not also advantage ourselves of the clock frequency scaling effect to confuse odds again for Entropy (Random, Not Entropy)<br /><br />SSD does also have a write counter & a cleared state, not so boring as one thinks if per 32KB segment is hashed in 4Bit, 8,Bit 32Bit float! (remember we have DOT3 DOT 4 & INT8 in ML)<br /><br />We can utilize write cycle statistics & all hardware; Interrupts by themselves are rather Boring!<br /><br />Computed timings on processes multiplexed over 3 Threads per group in competition is also a potential complexifier of Random<br /><br />Rupert S<div><br /></div>*<br />Very usable /dev/rnd Random Ring : TRNG : GPU : CPU : Asics : Using Chaos Wavelet<br />(Usable as encryption archetype): Chaos:A:B:T:Pi:Arc:Sin:Tan<br /><a href="https://science.n-helix.com/2023/02/smart-compression.html">https://science.n-helix.com/2023/02/smart-compression.html</a><div><div>*</div><div><br /></div><div>Pollinate nodes : <a href="https://pollinate.n-helix.com/">https://pollinate.n-helix.com/</a> <a href="https://pollinate2.n-helix.com/">https://pollinate2.n-helix.com/ </a><br /><br />https://science.n-helix.com/2018/12/rng.html<br /><br />https://science.n-helix.com/2022/02/rdseed.html<br /><br /><div>https://science.n-helix.com/2017/04/rng-and-random-web.html</div><div><br /></div><div>https://science.n-helix.com/2022/02/interrupt-entropy.html</div><div><br /></div><div><div>https://science.n-helix.com/2018/05/matrix-of-density.html</div><div><br /></div><div>https://science.n-helix.com/2019/10/classic-physics.html</div><br />https://science.n-helix.com/2021/11/monticarlo-workload-selector.html</div><div><br /></div><div>https://science.n-helix.com/2022/03/security-aspect-leaf-hash-identifiers.html<br /><br />https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html</div><div><br /></div><div>****</div><div><br /></div><h4 style="text-align: left;">PreSEED Poly Elliptic SiMD RAND : RS</h4><br />Preseed ; 3 Seeds with AES or Poly ChaCha or even 1 : 2 would be rather fast Init <br /><br />Blending them would make a rather paranoid Kernel developer feel safe! :D<br /><br />Like so List:<div><br />3 seeds 32Bit or 64Bit : <br />Examples : <br /><br />1 Seed : Pre seeded from CPU IRQ & Net 16Bit values each & merged<br />2 & 3 from server https://pollinate.n-helix.com &or System TRNG<br /><br />4 Seed mix 128Bit Value<br /><br />Advantages :<br /><br />AVX & SiMD Mixxer is fast 'Byte Swap & Maths etcetera" & MultiThreaded<br />AES Support is common :<br /><br />*<br /><h4 style="text-align: left;">HASH : RSA Source Cert C/TRNG : (c)RS</h4><br /></div><div>Elliptic RSA : Cert Mixer : RSA 4096/2048/1024Temporal : 384/256/192 ECC Temporal</div><div><br /></div><div>Centric Entropy HASH: Butterfly Effects</div><div><br /></div><div>ChaCha</div><div>SM4</div><div>SHA2</div><div>SHA3</div><div><br /></div><div>Elliptic Encipher</div><div>AES<br />Poly ChaCha</div><div><br />Elliptic : Time Variance : Tick Count Variance : On & Off Variance : IRQ<br /><br />*</div><h4 style="text-align: left;">Time & Crystal : Quartz as a diffraction point fractal differentiator : RS</h4><div><br /></div>RDTSC Variable bit differentiation & deviation of the quartz sub .0001 Value combined with complexity of unique interplay with Alternative clocks such as Network cards, Audio cards & USB Sticks & Bluetooth radio clocks & Ultimately the NTP Pools themselves when required.<br /><br /> (TIME Differential Float maths) TSC : RDTSC : RDTSCP : TCE supports single and half precision floating-point calculations<br /><br /><h4 style="text-align: left;">Security Relevant Extensions</h4><div>SVM : Elliptic Curves & Polynomial graphs & function<br />AES : Advanced Encryption Standard Functions<br />AVX : 32Bit to 256Bit parallel Vector Mathematics<br />FPU : IEEE Float Maths<br />F16b : 16Bit to 32Bit Standards Floats<br />RDTSCP : Very high precision time & stamp<br /><br />Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1<br /><br />32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)<br />(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second<br /><div><br /></div><div>*</div><div><br /></div><div>For RDTSCP = TValue TV1=16.0685 TV2=16.1432 TV3=15.1871</div><div>When Processor Mzh = PV1 PV2 PV3</div><div>RAND Source = Es1 Es2 Es3</div><div><br /></div><div>If Xt = 1.9 < then roll right</div><div><br /></div><div>((TV1 - TV2) * (PV1 - PV2)) / ((TV1 - TV3) * (PV1 - PV3)) = FractorXt(Xt)</div><div><br /></div><div>Es1 * Xt = Differential</div><div><br /></div><div>Es2 Es3</div><br />(c) Rupert S<div><br /></div>Quartz as a diffraction point fractal differentiator : RS<div><br /></div><div><div>https://science.n-helix.com/2022/02/interrupt-entropy.html</div><div><a href="https://science.n-helix.com/2022/03/ice-ssrtp.html">https://science.n-helix.com/2022/03/ice-ssrtp.html</a></div><div><a href="https://science.n-helix.com/2022/01/ntp.html">https://science.n-helix.com/2022/01/ntp.html</a></div><br /><a href="https://tches.iacr.org/index.php/TCHES/article/download/7274/6452">https://tches.iacr.org/index.php/TCHES/article/download/7274/6452</a><br /><a href="https://perso.univ-rennes1.fr/david.lubicz/articles/gda.pdf">https://perso.univ-rennes1.fr/david.lubicz/articles/gda.pdf</a><br /><a href="https://patents.google.com/patent/US9335971">https://patents.google.com/patent/US9335971</a><div><div>*</div><div><br />"Taking spinlocks from IRQ context is problematic for PREEMPT_RT. That<br />is, in part, why we take trylocks instead. But apparently this still<br />trips up various lock dependency analysers. That seems like a bug in the<br />analyser's that should be fixed, rather than having to change things<br />here.<br /><br />But maybe there's another reason to change things up: by deferring the<br />crng pre-init loading to the worker, we can use the cryptographic hash<br />function rather than xor, which is perhaps a meaningful difference when<br />considering this data has only been through the relatively weak<br />fast_mix() function.<br /><br />The biggest downside of this approach is that the pre-init loading is<br />now deferred until later, which means things that need random numbers<br />after interrupts are enabled, but before work-queues are running -- or<br />before this particular worker manages to run -- are going to get into<br />trouble. Hopefully in the real world, this window is rather small,<br />especially since this code won't run until 64 interrupts have occurred."<br /><br />https://lore.kernel.org/lkml/Yhc4LwK3biZFIqwQ@owl.dominikbrodowski.net/T/<br /><br />Rupert S</div><div><br /></div><div><div>*</div><h4 style="text-align: left;">Asymmetry dev/random:</h4></div><div>Explain it & code it please :D We most certainly know what Asymmetry is in PCI Transactions for GPU & Audio!<br /><br />The high precision clock source is a CPU feature, but what one forgets is that other processors & network cards have Clock Crystals & So do local networks though the Ethernet Time Sync protocol, PCI Cards with Fast Sync, Repeaters & Boosters..</div><div><br />We need Asymmetric T/T2 or (T * T2)/T3 Etcetera<br />The main feature is a Timer & The Synchronicity of that timer; Being Asymmetric on time is a feature!<br /><br />We laugh but yes Asymmetry Is a feature!<br />But we utilize the Asymmetry to provide CHAOS or Random Patterns,Not Precisely with a single Digit; We may? But we do not have to.<br /><br />RDTSC is a logical choice for a processor; However our timers can also simply be a tick,<br />Network Ethernet, PCI-E, Audio BUS, HDD & SSD, Timing Sync Events,</div><div>In the case (Example) Network PCI Cards; They do indeed have a precise & variable clock..</div><div>In addition they have Network Traffic & Chaotic Packet IRQ; Timed IRQ & Offloaded IRQ & Data,</div><div>Also TLS Cypher packets; (Events Sometimes Offloaded & Sometimes not).</div><div><br />In a single System Time Crystals & Sync Events are simply the beginning of "The EventFul Day - Crypto"<br /><br />Rupert S</div><div><br /></div><h4 style="text-align: left;">Elliptic Curve Erratic Time Diffraction:</h4><br />Relatively Subtle Timers, Clock Timers from NIC's or Statistical packet flows, Timer offsets & data flow Engrams & Anagrams & Flow patterns, Timers & Interrupts!<br /><br />But real Timing & Sync Crystals are a work of real logic & Therefor potent in their Patterns & Powerfully influential on the Dynamic Maximum System Potential,<br /><br />However played or used, Timers & Sync are the heart of a well centered Kye!<br /><br />So as to timers & statistics; We do have to flow charts though ECC Elliptic Anonymizers.<br /><br />We frequent the waters of personal & business & We do know so little from that,<br /><br />Elliptic Curve Erratic Time Diffraction!<br /><br />Unique Precise clocks & How many? Depends on how Expensive Your Mainframe is! Asymmetry dev/random: Explain it & code it please :D We most certainly know what Asymmetry is in PCI Transactions for GPU & Audio!<br /><br />Rupert S</div><div><br /></div><div><h4 style="text-align: left;">VMTGate2022:RS</h4><br />What we are looking for essentially is 2 things:<br />Clock differential; As in speed & frequency shifts Electric signal variance,<br /><br />The time shifting a number that does not guarantee forward (not obligatory),<br />For example a certificate ECC Elliptic that shifts 0.0005>6 to 4èéç=4 3fdé=5,<br /><br />However a differential does Vary, <br /><br />Still need system time to be precise (for Time NTP) & observations of differential are how we adjust..<br />Imprecision; Crystal Variance & imprecision is a core topic,<br />But we adapt imprecise results in NTP into precise ones.<br /><br />Nanosecond TSC : RSTSCP<br />https://lkml.org/lkml/2022/4/25/57 </div><div><br /></div>Some Random for various needs<br />https://is.gd/DEV_Random</div><div><br /><div>RS<br /><br /><div><div><br /></div><div>[PATCH RFC v1 09/10] sparc: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 08/10] um: use sched_clock() for random_get_entropy( ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 07/10] arm64: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 06/10] x86: use sched_clock() for random_get_entropy ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 05/10] arm: use sched_clock() for random_get_entropy ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 04/10] mips: use sched_clock() for random_get_entrop ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 03/10] riscv: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 02/10] m68k: use sched_clock() for random_get_entrop ... "Jason A. Donenfeld"</div><div>[PATCH RFC v1 01/10] random: use sched_clock() for random_get_entr ... "Jason A. Donenfeld"</div><div>[New] [PATCH RFC v1 00/10] archs/random: fallback to using sched_clock() ... "Jason A. Donenfeld"</div><div><br /></div><div>https://lkml.org/lkml/2022/4/8/945</div><div>https://lkml.org/lkml/2022/4/8/946</div><div>https://lkml.org/lkml/2022/4/8/947</div><div>https://lkml.org/lkml/2022/4/8/948</div><div>https://lkml.org/lkml/2022/4/8/949</div><div>https://lkml.org/lkml/2022/4/8/950</div><div>https://lkml.org/lkml/2022/4/8/951</div><div>https://lkml.org/lkml/2022/4/8/952</div><div>https://lkml.org/lkml/2022/4/8/953</div><div>https://lkml.org/lkml/2022/4/8/954</div><div>https://lkml.org/lkml/2022/4/8/955</div></div><div><br /></div><div><div>Timers</div><div>https://lkml.org/lkml/2022/4/9/459</div><div>https://lkml.org/lkml/2022/4/9/366</div></div><div><br /></div><div><div>RDTSC</div><div>https://lkml.org/lkml/2022/4/9/482</div></div><div><br /></div><div>Nanosecond TSC : RSTSCP</div><div><div>https://lkml.org/lkml/2022/4/25/57</div></div><div><br /></div>*<br /><br />Random : (Dynamic Elliptic Curve / T) * Factor Of T : <br /><br />"Problems for Arm (32-bit), Motorola 68000 (M68k), Microblaze, SPARX32, Xtensa, and other niche architectures."<br /><br />NoJitter - Initiating the dev/random ; Initiating Random with a SEED is the prospect I propose,<br />My personal Time Crystal RNG is based upon the variable clock rate principle of Quartz clock crystals & could potentially sound too regular.<br /><br />However as we know very small variabilities in Super Stable Quartz crystals (Factory made) causes doubt,<br /><br />However in the 0.005 or smaller range & Especially with variable frequencies & power input levels to controlled crystals; Creative Chaos Exists,<br /><br />Particular market is motherboards that tweak frequencies to improve performance!<br /><br />Clock rate variance is combined with a seed; As a Factoring agent & Again as a differentiator.<br /><br />What Is a Factoring Differentiator ? a Math that shifts values subtly & therefor shifts our results from predictable to unpredictable; Well hard to!<br /><br />The more effort we make; The harder it will be to see our Dynamic Elliptic Curve.<br /><br />Rupert S <br /><br /><a href="https://www.phoronix.com/scan.php?page=news_item&px=Linux-RNG-Opportunistic-urandom">https://www.phoronix.com/scan.php?page=news_item&px=Linux-RNG-Opportunistic-urandom</a><br /><br /><div>*****</div><div><h3 style="text-align: left;">Serve C-TRNG QT Fractional Differentiator(c)RS</h3><div><br /></div><div>Server C/TRNG Quarts Time * Fractional differentiator : 8Bit, 16Bit, 32Bit, Float Int32 : Fractional Differentiator : fig-mantuary micro differentiator.</div></div><div><br /></div><div><br /></div><div><div>SipHash: a fast short-input PRF</div><div><br /></div><div>Rotation Alignment : "The advantage of choosing such “aligned” rotation counts is that aligned rotation counts are much faster than unaligned rotation counts on many non-64-bit architectures."</div><div><br /></div><div>http://cr.yp.to/siphash/siphash-20120918.pdf </div><div><br /></div><div>https://www.aumasson.jp/siphash/siphash.pdf</div><div><br /></div><div>"Choice of rotation counts. Finding really bad rotation counts for ARX algorithms turns out to be difficult. For example, randomly setting all rotations in</div><div>BLAKE-512 or Skein to a value in {8, 16, 24, . . . , 56} may allow known attacks</div><div>to reach slightly more rounds, but no dramatic improvement is expected.</div><div>The advantage of choosing such “aligned” rotation counts is that aligned rotation counts are much faster than unaligned rotation counts on many non-64-bit</div><div>architectures. Many 8-bit microcontrollers have only 1-bit shifts of bytes, so</div><div>rotation by (e.g.) 3 bits is particularly expensive; implementing a rotation by</div><div>a mere permutation of bytes greatly speeds up ARX algorithms. Even 64-bit</div><div>systems can benefit from alignment, when a sequence of shift-shift-xor can be</div><div>replaced by SSSE3’s pshufb byte-shuffling instruction. For comparison, implementing BLAKE-256’s 16- and 8-bit rotations with pshufb led to a 20% speedup</div><div>on Intel’s Nehalem microarchitecture."</div><div><br /></div><div>https://www.kernel.org/doc/html/latest/security/siphash.html</div><div><br /></div><div>https://en.wikipedia.org/wiki/SipHash</div><div><br /></div><div>Code SIP-HASH</div><div>https://github.com/veorq/SipHash</div><div><br /></div><div><div>Serve C-TRNG QT Fractional Differentiator(c)RS</div><div><br /></div><div>Server C/TRNG Quarts Time * Fractional differentiator : 8Bit, 16Bit, 32Bit, Float Int32 : Fractional Differentiator : fig-mantuary micro differentiator.</div></div><div><br /></div><div>As we see rotation may benefact from the addition of Quartz crystal alignment sync data from 4 cycles & aligning data blocks,</div><div><br /></div><div>Obviously we can pre share 4 64Bit blocks use use a pre seed AES/ChaCha Quad!</div><div>Indeed we can have 16 64Bit pre Seeds & chose them by time sync for kernel</div><div><br /></div><div><div>Security bug; Solutions & explanation's (contains additional RANDOM Security Methods) :RS</div><div><br /></div><div><a href="https://science.n-helix.com/2020/06/cryptoseed.html">https://science.n-helix.com/2020/06/cryptoseed.html</a></div><div><a href="https://science.n-helix.com/2019/05/zombie-load.html">https://science.n-helix.com/2019/05/zombie-load.html</a></div><div><a href="https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html">https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html</a></div></div><div><br /></div><div>Rupert S https://science.n-helix.com</div><div><br /></div><div>*RAND OP Ubuntu : https://manpages.ubuntu.com/manpages/trusty/man1/pollinate.1.html</div><div><br /></div><div>https://pollinate.n-helix.com</div><div><br /></div><div>https://science.n-helix.com/2018/12/rng.html</div><div><br /></div><div>https://science.n-helix.com/2022/02/rdseed.html</div><div><br /></div><div>https://science.n-helix.com/2017/04/rng-and-random-web.html</div><div><br /></div><div>https://science.n-helix.com/2021/11/monticarlo-workload-selector.html</div><div><br /></div><div>https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html</div><div><br /></div><div>https://science.n-helix.com/2022/02/interrupt-entropy.html</div></div><div><br /></div><div>*</div><div><br /></div><div><h3 style="text-align: left;">Encryption Methods:</h3><div>https://tools.ietf.org/id/?doc=hash</div><div><br /></div><div>https://tools.ietf.org/id/?doc=encrypt</div><div><br /></div><h4 style="text-align: left;">HASH :</h4><div><br /></div><div>https://datatracker.ietf.org/doc/html/draft-ietf-cose-hash-algs</div><div><br /></div><div>https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html</div><div><br /></div><div>https://tools.ietf.org/id/?doc=sha</div><div><br /></div><div>https://tools.ietf.org/id/?doc=rsa</div><div><br /></div><h4 style="text-align: left;">Encryption Common Support:</h4><div><br /></div><div>https://tools.ietf.org/id/?doc=chacha</div><div><br /></div><div>https://tools.ietf.org/id/?doc=aes</div><div><br /></div><h4 style="text-align: left;">SM4e does seem a good possibility for C/T/RNG CORE HASH Functions!</h4><div><br /></div><div>ARM Crypto Extensions Code (Maybe AES Extensions would work here)</div><div>https://lkml.org/lkml/2022/3/15/324</div><div><br /></div><div>ARM Neon / SiMD / AVX Compatible (GPU is possible)</div><div>https://lkml.org/lkml/2022/3/15/323</div></div><div><br /></div><div><br /></div><div>*</div><div><br /></div><h4 style="text-align: left;">197 FIPS NIST Standards Specification C/T/RNG https://science.n-helix.com/2022/02/interrupt-entropy.html</h4><br />Only a Neanderthal would approve a non additive source combination that is injected into the HASH & Re-HASHED , <br /><br />One does not Procreate inadequate RANDOM from a simple bias KERNEL, Hardware RNG's added together may add around 450% Complexity! <br /><br />Hardware RNG devices MUST be able to Re-HASH to their 197 NIST Standards Specification, That is FINAL 2022 DT<br /><br />KEYS: trusted: allow use of kernel RNG for key material<br /><br />https://lkml.org/lkml/2022/3/16/598<div><br /></div>CAAM PRNG Reference : https://lkml.org/lkml/2022/3/16/649</div></div></div></div></div>Red Helixhttp://www.blogger.com/profile/18214366000501364627noreply@blogger.com0