Tuesday, October 29, 2024

TLS - Secure Negotiation & Transfer agreements in a modern IOT Friendly way, With PSK, ML-KEM's & ASCON

5 Way HAND https://is.gd/ECH_TLS : AES AlaML-KEM Falcon DES5 00:33 20/10/2024 - 2018 Rupert S


TLS - Secure Negotiation & Transfer agreements in a modern IOT Friendly way, With PSK, ML-KEM's & ASCON

in reference to :


https://csrc.nist.gov/Projects/block-cipher-techniques

https://nvlpubs.nist.gov/nistpubs/ir/2024/NIST.IR.8459.pdf
https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-131Ar3.ipd.pdf

ECH first, Client interactions with server (DNS is first though)

https://developers.cloudflare.com/ssl/edge-certificates/ech/
https://datatracker.ietf.org/doc/draft-ietf-tls-svcb-ech/

PSK & Updating DNS Security Profile

https://datatracker.ietf.org/doc/draft-eastlake-dnsop-rfc2930bis-tkey/

PSK & Updating DNS Security in use

https://datatracker.ietf.org/doc/draft-ietf-uta-tls13-iot-profile/

https://datatracker.ietf.org/doc/draft-ietf-tls-extended-key-update/

Logging keys leads to debugging & Kracks in the wall with eyes

https://datatracker.ietf.org/doc/draft-ietf-tls-ech-keylogfile/

https://datatracker.ietf.org/doc/draft-ietf-tls-hybrid-design/

related to

Also https://www.logitech.com/content/dam/logitech/en/business/pdf/logi-bolt-white-paper.pdf

ASCON may be right for you, If you are in IOT & can barely breath on 33mhz https://is.gd/DictionarySortJS

PSK, ML-KEM, AES

https://is.gd/ECH_TLS
https://is.gd/KeyBitSecurity
https://is.gd/AES_Strengths

https://science.n-helix.com/2022/03/ice-ssrtp.html

https://science.n-helix.com/2024/10/ecc.html

https://science.n-helix.com/2024/10/tls.html

RS

*

ID-Matrix-dev-random - AnonCRT - Generating public keys involving matrix operations
https://is.gd/MatrixGenID

In this example a Matrix M² is used with dev/random to develop a certificate ID of anonymous nature..

The common attribute is that dev/random & attached data are used to generate a key ID, Personal & Server,

Usage such as CC cards, ID & Radio or mobile data & wifi..

The principles of the cert chain!

RS

https://is.gd/ECH_TLS

*

RSA 2048 + ECC Chaining, I would like to be clear RSA 2048 is 4x the certificate ECC 384 Certs are with ECC included in RSA Protocols,


While it is easy to inside crack an RSA on a 300 point Quantum computer worth an estimated 2 Billion $,

It is not that easy for the gamer or crack-ware

DT 'All-serious gamer', Rupert "The-All-Effort"

*

The first effort: RS

(Client or Server) : Compression

Speed of course! & Bandwidth...

Common use of compression speeds up the internet, The list is (with directories) : LSTD, Brotli-G, GZip, Deflate

The first principle to bear in mind for certificates is that most code will not repeat very often..

However ECC is a curve & if you know your own? You can compress it!

Bear in mind that prefetching a curve tells others, You may have it (client or server)

A common principle of the data hoarder like a certificate server is space! Space costs money! & Time..

Common things to compress? Almost everything!

Key Points:

Compression Techniques:

LSTD, Brotli-G, GZip, Deflate:
These are common compression algorithms used to reduce file size and improve transmission speed.

Certificate Compression:

ECC Curve Compression:
By knowing the specific curve used; Compression can be applied to reduce storage and transmission overhead.

Prefetching Considerations:
Prefetching a curve can signal its availability to others; Which can have security implications.

Space Optimization:
Compressing certificates and other data can reduce storage requirements.

Time Efficiency:
Compression can speed up data transfer and processing.

Complexity of Certificate Compression:
Implementing certificate compression can be complex and requires careful consideration of cryptographic algorithms and security protocols.

While compression improves efficiency, it potentially creates risk,
Compression can make data more susceptible to certain attacks.

Rupert S

*

PSK & Fast ECC Encryption : Encoded DNS & LSTD Adoption through compressible strings:


Firstly Secure Encrypted DNS exists, Secondly Cloud DNS Exists..

So location is not ID! or IP..

As stated in this document PSK Early Secret extraction is less of a problem for the following reasons:

Similar strings of length as pointed out by the NIST recommended passwords?

Memory but also compression!

Complexity is an object.. Hard to compress, Hard to remember & recall! But not impossible...

But later yes? When we know things about what we want..

Compressed secrets are low latency quick sends!

You have to bear in mind that PSK slope or PSK Escalation? Yes that is where you move onto more complex strings!

Bear in mind that early adoption of a pool of Random strings.. Takes space in a DNS or server Cloud Host archive!

Quick string PSK is a highly compressible and undeniably hackable version..

However our aim is the following:

UDP is pseudo-random
TCP is logical

Under these conditions & in a tunnel; PSK Compression on first ETA.. Is a clear clean 0 to 60 (in car terms),

Fast & Furious is our moto!

RS

*

PSK : Limited Exposure


Exposing a 64Bit, 80Bit, 128Bit key to the wind? Special requirements

ASCON versions have appeared to support PQC Light, So you know there is potential!

Military Air & Navy recommend 128 Bit PSK, Really some craft have computers big enough for 64 Bit,

64Bit is not ideal; But in the limited exposure field of Landing; Docking & Traveling over 4KM²; 64Bit still holds ground!

With special encryption: ECC & DES3/4/5 Mode : AES, ASCON, ...

The relevance of specialist encryption techniques, Described by the Light Encryption category :

https://csrc.nist.gov/Projects/lightweight-cryptography/finalists

Light Cryptography specialised as : ECC Mode { Insert mode here } : { Bit Depth }

We have potential!

PSK EHDSA

*

ECDSA,ASCON, AES, ML-KEM, Falcon, Dilithium, :


https://csrc.nist.gov/Projects/lightweight-cryptography/finalists

https://csrc.nist.gov/Projects/post-quantum-cryptography/publications

Option 1:

Delivering a Key Ramp..

Simple 8Bit key with high compression ratio first ? Data latency allows unnoticeable first key with LSTD Compression

8Bit PSK
It should be reasonable to assume that an 8 digit PSK is 8Bit or 16Bit with UTF-8,

Next delivery of either a 64Bit, 128Bit PSK.. An exchange of 64Bit PSK from client & 128Bit from server?

Potentially dual encryption..
Low complexity hardware

Both directions Key Encrypted Data.

PSK Pre Share Key (through DNS, Preferable Auto from Registered DNS & Cloud Provider)

PSK Key pool delivers key on first contact to server,

PSK Key length escalation, Thoughts..

4 Key DES is in principle the timed exchange ok keys, Now as you know with ECH Enhanced Client Hello (Cloudflare - NIST - Standards W3 - RS),

As you may know an open secret is exchanged first before a security certificate; The exchange protocol:

Exchange protocol:

Preliminary contact protocol:

Escalating Ramp:

Modes suitable for DNS, 0.8us exposure

8Bit }
16Bit }
32Bit } shared many key

Secondary key generation

64Bit }
128Bit }
256Bit }
512Bit } Multiples for ECC, DES3/4/5 Mode

Rupert S

It shall be known that with ECC, AES delivers a time related encoding

Option 1+2: The Key Exchange

Next delivery of either a 64Bit, 128Bit PSK.. An exchange of 64Bit PSK from client & 128Bit from server?

Potentially dual encryption..
Low complexity hardware

On existence of a key

Dilithium, Falcon Key delivery

The client shall receive a key for deliveries to server, Potent /dev/random Key..
Server shall deliver a reception key to server verified certificate..

The Client & Server have their own origin certificate..

If Without a personal key; The client shall have a cooky key from dev/random key creation or a client pool!

If the client has a personal Cooky Key hash or a Client Key, Server shall be in reception of encrypted data..

Both directions Key Encrypted Data.

Reference: https://is.gd/ECH_TLS

Rupert S

*

DES5, ECC, : ML-KEM, AES


ECC & DES3/5

Insertion of certificate verified key exchange with verified return stub key (verified against contact key)

3 to 5 minute timed; multiple /dev/RND stub key exchanges to change pattern..

Variable 3 Port timed; 1 to 3 ports transmission from source to end point,

To stop port flooding, single arrival port.

Exchanges between server & client to involve multi round pollinated STUB Certificate exchange & use.

ECC & DES3/5

Represents Stub Certificate exchange:

----+++++-----+++++---
-----++---+++---+++---
++++---+++---+++---+++

Rupert S

*

Key Exchange Protocol with ECC, AES


The provided text outlines a proposed key exchange protocol that leverages ECC and AES for enhanced security and flexibility.

Here's a breakdown of the key components:

Preliminary Contact and Key Establishment:

PSK (Pre-Shared Key): A shared secret is established between the client and server using DNS or a cloud provider.

Key Length Escalation: The PSK length can be increased over time to enhance security.

ECC and AES: ECC is used for key exchange, while AES is used for symmetric encryption.

Key Delivery and Encryption:

Option 1: Key Ramp:

A simple 8-bit key with high compression is initially exchanged.

Subsequent exchanges involve larger keys (e.g., 64-bit, 128-bit) to strengthen security.

Dual encryption can be considered for added protection.

Option 2: Dilithium or Falcon:

The client receives a key from /dev/urandom for sending data to the server.

The server delivers a reception key to the client, verified against the server's certificate.

If the client doesn't have a personal key, it uses a cookie key or a client pool key.

Stub Certificate Exchange:

A mechanism is proposed to periodically exchange stub certificates for added security.

This involves multiple /dev/urandom key exchanges and transmission through variable ports to prevent port flooding.

Key Points and Considerations:

The protocol aims to provide a secure and flexible key exchange solution.

It incorporates ECC for key exchange and AES for encryption, offering a strong combination.

The option to use Dilithium or Falcon for key delivery provides additional flexibility.

The stub certificate exchange mechanism adds a layer of security by periodically changing the keys.

Potential Improvements:

Additional Security Measures: Perfect forward secrecy (PFS) to protect against compromise of long-term keys.

Performance Optimization: Evaluate the performance impact of the proposed protocol, especially in terms of latency and computational overhead.

Compatibility: Ensure compatibility with existing standards and protocols to facilitate widespread adoption.

Overall, the proposed key exchange protocol presents a promising approach that combines ECC, AES, and additional security mechanisms..

By addressing the identified areas for improvement, It can potentially contribute to a more secure and robust communication environment.

RS

******** Reference Material :>


Session EEC/RSA/AES/Encryption Key Connection Protector - Certificate (c)RS + Reward welcome

The 1024/2048/4096 cert spawns the EEC cert pair as elliptic Curves based on the primary...

the curve cert is responding through TLS and QUIC to the eec key,

Formed temporarily from the local public key & or user certificate!

The computation of verification comes from the ability of the connection,

To provide several versions of the certificates EEC temporary cert (lasts one hour for example)

multiple EEC cert variants all come from a common root cert,

Therefore the server and user can talk enciphering both ways in a complex manner,

That is complex to spy upon.

The same methodology produces verifiable source certificates of sizes 512 to 8192(For example)

That can then do RSA and AES and other cyphers from larger base certificates,

Also same size hashed & cyphered Cryptographic pairs.

Hence the use of a hidden session cooky :

(AES:RSA Encrypted and temporarily anonymously IP Locked - refreshed on ip change (for ISP changes to ip)

This is very important, also user anonymous certificates! equates a temporary,

Subcert & session ECC Elliptic Curve

Such is the way that a local P11 Connection can make a local temp session EEC Elliptic RSA AES

(Copyright) Rupert S

https://science.n-helix.com/

I suggest the cloud UID for verification HMAC or a constant sent to the user per day/Session..

Frankly if the code AES we use is in plain script people could spy it..

I think spies do spy cookies & they do steal logins this way!

HMAC the AES of the UID code or send an AES/HMAC code inside a personal JS,

That echo's the cloud key for decryption; A Worker..

The communication with the server JS Security Encipher would most certainly..

Make hacking the Security EEC Server Certificate communications very hard to accomplish.

Cloud edge JS Encode to a local worker & from the local worker to edge & server.

The process in called Dual Edge Encrypt Factor : DE²F

Interesting code for security https://developers.cloudflare.com/workers/examples/signing-requests

Reference: https://drive.google.com/file/d/1WmhMcCZZjDI4pKnQsccvaf4RdquhPPs8/ https://is.gd/ECH_TLS

https://is.gd/DictionarySortJS

https://is.gd/UpscaleWinDL

https://is.gd/HPC_HIP_CUDA

https://is.gd/UpscalerUSB_ROM

https://is.gd/OpenStreamingCodecs

********* Really 2018, But really DES3 1980's************


'virtio-crypto: implement RSA algorithm'

Hardware Drive & System RAM 'DES 4 Key 64Bit & 128Bit AES & PolyChaCha & the Chinese one'

for protocols a very good idea & not CPU intensive>

Is 64Bit AES Even supported in crypto hardware : https://lkml.org/lkml/2022/3/1/1428

64Bit 4 Key is a potential with DES & may well work far faster than 128Bit (64 Bit processors)

In the case of HDD Drives & VM Drives may be transparent..Offers security:

1 key per drive layer : 4 Platters = 4 Keys

16 Platters = 8 Keys or 4 Keys

(c)RS 2022

https://bit.ly/VESA_BT

*******

Support rsa & pkcs1pad(rsa,sha1) with priority 150.

Test with QEMU built-in backend, it works fine.

1, The self-test framework of crypto layer works fine in guest kernel

2, Test with Linux guest(with asym support), the following script

test(note that pkey_XXX is supported only in a newer version of keyutils):

- both public key & private key

- create/close session

- encrypt/decrypt/sign/verify basic driver operation

- also test with kernel crypto layer(pkey add/query)

All the cases work fine.

rm -rf *.der *.pem *.pfx

modprobe pkcs8_key_parser # if CONFIG_PKCS8_PRIVATE_KEY_PARSER=m

rm -rf /tmp/data

dd if=/dev/random of=/tmp/data count=1 bs=226

openssl req -nodes -x509 -newkey rsa:2048 -keyout key.pem -out cert.pem -subj "/C=CN/ST=BJ/L=HD/O=qemu/OU=dev/CN=qemu/emailAddress=qemu@qemu.org"

openssl pkcs8 -in key.pem -topk8 -nocrypt -outform DER -out key.der

openssl x509 -in cert.pem -inform PEM -outform DER -out cert.der

PRIV_KEY_ID=`cat key.der | keyctl padd asymmetric test_priv_key @s`

echo "priv key id = "$PRIV_KEY_ID

PUB_KEY_ID=`cat cert.der | keyctl padd asymmetric test_pub_key @s`

echo "pub key id = "$PUB_KEY_ID

keyctl pkey_query $PRIV_KEY_ID 0

keyctl pkey_query $PUB_KEY_ID 0

echo "Enc with priv key..."

keyctl pkey_encrypt $PRIV_KEY_ID 0 /tmp/data enc=pkcs1 >/tmp/enc.priv

echo "Dec with pub key..."

keyctl pkey_decrypt $PRIV_KEY_ID 0 /tmp/enc.priv enc=pkcs1 >/tmp/dec

cmp /tmp/data /tmp/dec

echo "Sign with priv key..."

keyctl pkey_sign $PRIV_KEY_ID 0 /tmp/data enc=pkcs1 hash=sha1 > /tmp/sig

echo "Verify with pub key..."

keyctl pkey_verify $PRIV_KEY_ID 0 /tmp/data /tmp/sig enc=pkcs1 hash=sha1

echo "Enc with pub key..."

keyctl pkey_encrypt $PUB_KEY_ID 0 /tmp/data enc=pkcs1 >/tmp/enc.pub

echo "Dec with priv key..."

keyctl pkey_decrypt $PRIV_KEY_ID 0 /tmp/enc.pub enc=pkcs1 >/tmp/dec

cmp /tmp/data /tmp/dec

echo "Verify with pub key..."

keyctl pkey_verify $PUB_KEY_ID 0 /tmp/data /tmp/sig enc=pkcs1 hash=sha1

*****

Ascon, Story, (only something the military would appreciate), DT


Now you may feel this is a bunch of talawaki! Well fine! Walla Walla :p

Now you know the birdman(& women) story; Now to refine a point about ASCON & how good it is?

When I was convincing the officers I was talking to Birdmen...

I had my reasons, The improvement of the electron microscope; The antigravity; The analysis...

Yar Yar, But hay? you know something? ASCON is great!

So they gave me permission to carry the formula of ASCON to the birdmen with some conditional requirements,

Desires for technology...

So as I stood with the science officer I said; So the base officers have something to share...

Oh you know man may not be a super being; but he can be underrated!

So I unfolded a piece of paper with a maths formula and some; you know 'Demands' as the French say Desires!

So the Birdman scientist looked at it for a second and .... looked at it...

What is this nonsense....

I DON'T KNOW.... I thought you WERE... Clever :P & I winked!

He looked some more! EURIKA, Not so fast....

Can you do better?

This is good yes, Astounded but oh my god! They shared that with us!

Yes they did and if you can come up with something new.... To add to it...

& Some other things; You & I & some Muscle Bigos can visit the base...

Would you like that? Arrangements were made...

Something Found!

Nothing is known of Ascons more advanced models & most probably... it is unlikely they ever will.

All you need to know is...

ASCON IS GREAT!

Duke Thrust

*****

Skipjack, DES3, GCM, A story for gamers about the Logitech G Series gamer mouse! If Aliens are not enough, Try gamers & cheaters


Once upon a time there was a contest in Asia...

Yes I know , astounding! :L Well anyway the contest was on Euro-Gamer live! So you know how long winded the interviews are before the contest?

The interview was 1.3 hours & the guys had the gaming rigs setup...

The guy had his mouse 'Plugged in' To his Plug/Adapter 'Radio init'

In the audience were a group of malcontents...

Malcontents with hacking radio adapters!

They hacked his Radio over 1 hour of interviews...

But something gave them away..

Network traffic; The sniggering...

The shuffle of feet & conversation...

You know detective work! & you Do Know that they have detectors for this kind of harassment? Right, you know they do!

Radio jamming, Scamming, hacking, falsification.... Theft & robbery!

They got one of them; Don't matter... We got the code!

He turned off & on his gear... his mouse, his headset...

You know what? THE CODE CHANGES!

Hail Logitech G, Hail you the gamer!

Duke Thrust

ECC - Elliptic Matrix - Lattice Maths - RS

Elliptic Matrix - Lattice Maths


Lattice Square cohesive, Time Stamp Elliptoid 

(c)Rupert S

Elliptic in out

*

Matrix Formula M.A.P & AVX Computed parallel instruction

We can either repeat loop solves : (cos(b), sin(b)) * a + mean,
Or we can form a table matrix

(cos(b), sin(b)) = x , * a + mean = y

     1      2     3      4
a x*y, x*y, x*y, x*y
b x*y, x*y, x*y, x*y
c x*y, x*y, x*y, x*y
d x*y, x*y, x*y, x*y

*

High Precision Maths Solve : { 16Bit, 32Bit, 64Bit & so forth } :

Create table ARC, SIN,TAN, Size = Multiples of 4 or rather 2x2, Or 8 or 4x4

Values (cos(b), sin(b)) = x

tan(T) = y

Example:

Values (cos(b), sin(b)) = x * y = tan(T)


     1      2     3     4
a x*y, x*y, x*y, x*y
b x*y, x*y, x*y, x*y
c x*y, x*y, x*y, x*y
d x*y, x*y, x*y, x*y

Parallel rows shall be sorted (SiMD)

Values of {A,B,C,D}:1, {A,B,C,D}:2, {A,B,C,D}:3, {A,B,C,D}:4,

Sort by atomic High Accuracy RTC (timer) ECC

The table shall be sorted by a given gradient, Ellipse,

The rules shall be:

Cache the ellipses,

Form the ellipses into a elliptic curve,

Reduce the curve to a set of maths formula,

Map the curves for dimensions over time,

Curve definition precision steps :

Reduce the curve to a higher state logical maximum cap : { 16Bit, 32Bit, 64Bit & so forth } per tick / Second

Specify a bit depth for the expansion of the curve : { 16Bit, 32Bit, 64Bit & so forth } per tick / Second

Send a reciprocal curve per..: second, Per negotiated time period, Per group

*****

New table #Formulae 08:51 29/10/2024


arc sin tan table , useful for clocks!, Well anyway Maths

Python

import numpy as np

# Create angles from 0 to 90 degrees in steps of 10 degrees
angles = np.arange(0, 91, 10)

# Calculate sine and tangent of each angle
sine_values = np.sin(np.radians(angles))
tan_values = np.tan(np.radians(angles))

# Create the table header
table_header = "{:10s} {:10s} {:10s}".format("Angle", "Sin", "Tan")

# Create the table rows using string formatting
table_rows = []
for angle, sine, tangent in zip(angles, sine_values, tan_values):
table_rows.append("{:10d} {:10.4f} {:10.4f}".format(angle, sine, tangent))

# Combine the header and rows into a table string
table_string = "\n".join([table_header] + table_rows)

# Print the arc sin tan table
print(table_string)

// (c)Rupert S

https://is.gd/ECH_TLS

*****

ID-Matrix-dev-random - AnonCRT - Generating public keys involving matrix operations
https://is.gd/MatrixGenID

In this example a Matrix M² is used with dev/random to develop a certificate ID of anonymous nature..

The common attribute is that dev/random & attached data are used to generate a key ID, Personal & Server,

Usage such as CC cards, ID & Radio or mobile data & wifi..

The principles of the cert chain!

RS

https://is.gd/ECH_TLS

*****

ASCON may be right for you, If you are in IOT & can barely breath on 33mhz https://is.gd/DictionarySortJS

PSK, ML-KEM, AES
https://is.gd/ECH_TLS
https://is.gd/KeyBitSecurity
https://is.gd/AES_Strengths

https://science.n-helix.com/2022/03/ice-ssrtp.html

https://science.n-helix.com/2024/10/ecc.html

https://science.n-helix.com/2024/10/tls.html

*****

Machine Learning


https://science.n-helix.com/2022/10/ml.html

https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html

Accelerated Python: NPU, TPU, SiMD

https://is.gd/CoralAI
https://is.gd/TPU_Inference
https://is.gd/TPU_Inference2

https://is.gd/DictionarySortJS
https://is.gd/UpscaleWinDL
https://is.gd/TFLiteDev
https://is.gd/TFLiteDevP2

https://is.gd/HPC_HIP_CUDA
https://is.gd/SPIRV_HIPcuda

https://is.gd/UpscalerUSB_ROM

https://is.gd/OpenStreamingCodecs

https://is.gd/AMDPro2024PolarisCombined

The perfect Proposal RS

Friday, September 27, 2024

XRay Scan

XRay Scan, A Space bird related story, With a scientific point 05:41 27/09/2024


When I initially was in the tube & through to the lasers examining the earth, mud & plant samples...
Lasers here are directed at samples floating in air! Now as i said this involves..

Anti Gravity &
Directed Red lasers ( presumably unknown forms of scanning )
Possibly heat dissipated matter; AKA the gas examination we use today with a mass spectrometer!

Now I have frequented hospitals before & do occasionally visit a kid with leukaemia & other illnesses...

In actual fact I can perform several miracles ...

The miracle of desperate thought & observation
The miracle of caring
The miracle of positive thinking; Staff need hope & energy
The miracle of group thinking!

& Finally all the prayer worship & magical gift stuff that HP, God, Odin Father, Loki, Thor & Christ & myself are proud of!

But practicality! Right Because I was not born a faith healer, I was born a cynical scientist student...

However God saw to me being an avid believer; Saving me from drowning under 3m of water when I couldn't swim & nobody was there to save me but him.

But you know from the heart that you may have the same cynicism as an atheist & know that hurts because Gods don't help a selfish C****

Directed radiation, XRays & radio require aiming specifically directed intense radiation..

Directly at large clusters of CELLS (Cancers)

Direct radio does a lot of damage!

However Cancer has one big weakness & that is Radio does a lot more damage to cancer cells generally than normal cells!

Reasons include:

Water content

Constant cellular division

less firm cell walls

The lack of genetic correction

Error multiplication

Energy demand, AKA cancer cells are energy greedy!

Nutrition demands (cell replication, resource burning, Lack of vein presence in dense clusters, Salt & iodine)

Directed pulse XRay & Radio & even needle injected alpha beta decay...

Directed amplification Laser Array

Damage is our hope!

Rupert S

https://is.gd/DictionarySortJS

https://kindpassion.n-helix.com/2024/09/bird.html

Monday, September 2, 2024

Laser TV

Laser TV 13:13 02/09/2024 (c) Rupert S

Laser TV : Now to put a point very important, if the firmware stalls the Laser points directly at the viewer at full power!

Even a 1 Watt laser can potentially blind someone.

Refraction is our friend, no one is looking directly at a laser, When static because of chip or firmware failure or assassination.

Several means of protecting the client exist

The basic formula is to use microchip lasers & LED that are specifically made to point,
Basically LED that point are not specifically infinite! But we certainly don't- care; Do we haha

Basic diode laser with a vibrating glass lens inside a solenoid.

The laser or LED is formulated to point in directions & move so that it forms shapes on a surface or piece of opaque material.

The opaque material & materials like steam, Can be the focus of local re emits & non direct reflection & We can use a material that holds & re emits light,

Example materials include glow in the dark paint (light reception material)

Lasers can also point at radiant opaque but reflective surfaces..

Surface paints that blur on refraction so that re emits in a curve provide more viewer angles,

Lensed surfaces provide good refraction potential, With glossy white & mirror inside them & sub lens Black LED such as found in calculators for over 20 years.

Representetive of optic lenses with reflective material backing

[ ][ ][ ][ ][ ]
[ ][ ][ ][ ][ ]
[ ][ ][ ][ ][ ]
[ ][ ][ ][ ][ ]
[ ][ ][ ][ ][ ]

The principle works for either forward firing reflector plates,
Layers on the wall on a mat reflective,
Refractive lensing you fire through.

Angle calculations make an intentional decision to be Square; So distortions are minimal,

Curved lenses provide circular motion the advantage, But distortion has to be calculated well..
The ( ) & the [ ] bracket lens both work; Overall Square lenses are cheaper to produce consistency from.
 
(c)RS

Genuinely good JS + Python & configuration work, Windows, Linux, ARM

ML tensor + ONNX Learner libraries & files
Model examples in models folder

https://is.gd/DictionarySortJS
https://is.gd/UpscaleWinDL
https://is.gd/HPC_HIP_CUDA

https://is.gd/UpscalerUSB_ROM

https://is.gd/OpenStreamingCodecs

https://is.gd/AMDPro2024PolarisCombined

The perfect Proposal RS


Tuesday, March 26, 2024

GoFetch Security Exploit - Repair Security Fix (c)RS

GoFetch memory dependent prefetch exploits 01:15 26/03/2024 (c)RS

GoFetch Vulnerability:

Exploits DMPs present in certain processors (e.g., Apple Silicon, newer Intel) to leak sensitive information.

DMPs aim to improve performance by prefetching data the processor might need based on past access patterns.

Malicious actors can trick DMPs into prefetching data from memory locations they shouldn't access, revealing sensitive information like cryptographic keys.

If these analytics are unavailable, the exploit presumably fails.

*

How the Virus Works :

GoFetch memory dependent prefetch, exploits rely on exploiting performance boosting statistic logs,

Virus works by analysing High Precision Timers & the Runtime Analytics Process,
If those facts are unavailable.. Then the virus procedural analytics would not work!
Praise the quality of the analytics process!

Analyses data from High Precision Timers and Runtime Analytics Process.

These analytics likely reveal patterns in memory access that the virus exploits to trigger DMP behaviour and leak information.

If these analytics are unavailable, the exploit presumably fails.

Countermeasures

Restrict access to analytics data: Only certificate certified applications should access the data DMPs rely on.

Permissions: Similar to Android, keep performance data and timers private, requiring explicit permission for access.

Delayed delivery: False or delayed data might not be as effective but could slow down attackers.

Sandboxing: Isolate untrusted applications in a virtual machine (VM) to limit their ability to exploit the system & performance metrics & statistics.

That being said; I believe the virus works by analysing High Precision Timers & the Runtime Analytics Process,
If those facts are unavailable.. Then the virus procedural analytics would not work!

you can however praise the quality of the analytics process!

Rupert S

*

The thoughts to process:

One or Two Facts,

Facts worth noting about the statistics required to exploit the CPU internals:

One

Keep the statistics away from the non certified virus..
keep them Admin..

Two

Unshared performance statistics & timers; don't get processed!
keep the properties personal permissions like android.

Three

Lies about statistics are not allowed...
However delayed delivery affects little but a code developer...

Four,

Applications have to have been trusted to gain statistics

You can contain the bug with analytic observation of the data query and if no permission is granted...

Boot them to VM virtual "reality" aka delayed and a fabrication of certainty.

GOD Loves you...
Jahova

RS

That being said; I believe the virus works by analysing High Precision Timers & the Runtime Analytics Process,
If those facts are unavailable.. Then the virus procedural analytics would not work!

you can however praise the quality of the analytics process! haha

Rupert S

Monday, July 24, 2023

ZenBleed

ZenBleed Parallel Solvent RS 2023

ZenBleed, So what about 64Bit to 128Bit bleed in SiMD? Mind you; 'Bound to be One' 20:20pm 24/07/2023 (c)RS

XMM 128Bit YMM 256Bit ZMM 512Bit

My theory involves using higher modes for synchronous packing!

What do i mean ?

When you have a full system (processes), 64Bit Processes start packing 128Bit registers! Particularly with Float units 182Bits...

Indeed an olderror is packing 128Bit registers with Float unit (FPU) Values with rollover!

So?

Two things first positive:

We can pack FPU Register Values into 256Bit (and Zero : vzeroupper & tzcnt (Trailing Zero Count)),
Enabling us to directly utilise SiMD <> with <> FPU!

We can solve the lower XMM to YMM to ZMM differences! How ?

We Multiple Array fill the next register with at least 2 values!

So ?

Parallel processing!

How ?

XMM-128 | ZMM / 4 or 128 * 4! Parallel!*4 Best!

XMM-128 | YMM / 2 or 128 * 2! Parallel!*2 Best!

YMM-256 | ZMM / 2 or 256 * 2! Parallel!*2 Best!

FPU-182 | YMM or 182 * 1 = Single File FPU <> SiMD |

ZMM / 2 or 182+r * 2! Parallel!*2 Best! = Double File FPU <> SiMD

r = Remainder for vzeroupper | tzcnt

Parallel Operation Principle with CPU Register & OPS division : RS


We will be using the value split:

512/2 = 256*2
256/2 = 128*2
128/2 = 64*2
128/4 = 32*4

We will therefor be able to use 32Bit, 64Bit, 128Bit , 256Bit, 512Bit values at leasure..
But we have to optimise the entire branch to use a single precision!

Single Type Precision operations make the effects of C++ Fast-float & Half Precision removed...

No operation errors.. & Parallel operation

reference (Faster Maths & ML)

(c)Rupert S

< Yes Bug Bounty & Solve Bounty : Bounty Bounty >

https://lock.cmpxchg8b.com/zenbleed.html

Vulnerability

It turns out that with precise scheduling, you can cause some processors to recover from a mis-predicted vzeroupper incorrectly!

This technique is CVE-2023-20593 and it works on all Zen 2 class processors, which includes at least the following products:

AMD Ryzen 3000 Series Processors
AMD Ryzen PRO 3000 Series Processors
AMD Ryzen Threadripper 3000 Series Processors
AMD Ryzen 4000 Series Processors with Radeon Graphics
AMD Ryzen PRO 4000 Series Processors
AMD Ryzen 5000 Series Processors with Radeon Graphics
AMD Ryzen 7020 Series Processors with Radeon Graphics
AMD EPYC “Rome” Processors

Speculation

Hold on, there’s another complication! Modern processors use speculative execution, so sometimes operations have to be rolled back.

What should happen if the processor speculatively executed a vzeroupper, but then discovers that there was a branch misprediction? Well, we will have to revert that operation and put things back the way they were… maybe we can just unset that z-bit?

If we return to the analogy of malloc and free, you can see that it can’t be that simple - that would be like calling free() on a pointer, and then changing your mind!

That would be a use-after-free vulnerability, but there is no such thing as a use-after-free in a CPU… or is there?

RS Spectra Mitigations https://science.n-helix.com/2018/01/microprocessor-bug-meltdown.html
ZenBleed Parallel Solvent RS 2023 https://science.n-helix.com/2023/07/zenbleed.html

Core/CPU/GPU security core SSL/TLS BugFix
https://science.n-helix.com/2020/06/cryptoseed.html
https://science.n-helix.com/2019/05/zombie-load.html

Vectors & maths
https://science.n-helix.com/2022/08/simd.html
https://science.n-helix.com/2022/04/vecsr.html
https://science.n-helix.com/2016/04/3d-desktop-virtualization.html
https://science.n-helix.com/2022/04/vecsr.html
https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html
https://science.n-helix.com/2023/02/smart-compression.html

Networking & Management
https://science.n-helix.com/2023/06/tops.html
https://science.n-helix.com/2023/06/ptp.html
https://science.n-helix.com/2023/06/map.html
https://science.n-helix.com/2023/02/pm-qos.html
https://science.n-helix.com/2022/08/jit-dongle.html
https://science.n-helix.com/2022/06/jit-compiler.html
https://science.n-helix.com/2022/03/ice-ssrtp.html
https://science.n-helix.com/2022/01/ntp.html

Faster Maths & ML
https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html
https://science.n-helix.com/2021/02/multi-operation-maths.html
https://science.n-helix.com/2021/11/parallel-execution.html
https://science.n-helix.com/2022/12/math-error-solve.html
https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html
https://science.n-helix.com/2022/10/ml.html

Focus on Quality
https://science.n-helix.com/2022/09/ovccans.html
https://science.n-helix.com/2022/11/frame-expand-gen-3.html
https://science.n-helix.com/2022/03/fsr-focal-length.html

https://blog.cloudflare.com/zenbleed-vulnerability/

https://www.theverge.com/2023/7/25/23806705/amd-ryzen-cpu-processor-zenbleed-vulnerability-exploit-bug

************* Reportage >

Introduction

All x86-64 CPUs have a set of 128-bit vector registers called the XMM registers. You can never have enough bits, so recent CPUs have extended the width of those registers up to 256-bit and even 512-bits.

The 256-bit extended registers are called YMM, and the 512-bit registers are ZMM.

These big registers are useful in lots of situations, not just number crunching! They’re even used by standard C library functions, like strcmp, memcpy, strlen and so on.

Let’s take a look at an example. Here are the first few instructions of glibc’s AVX2 optimized strlen:


(gdb) x/20i __strlen_avx2
...
<__strlen_avx2+9>: vpxor xmm0,xmm0,xmm0
...
<__strlen_avx2+29>: vpcmpeqb ymm1,ymm0,YMMWORD PTR [rdi]
<__strlen_avx2+33>: vpmovmskb eax,ymm1
...
<__strlen_avx2+41>: tzcnt eax,eax
<__strlen_avx2+45>: vzeroupper
<__strlen_avx2+48>: ret

The full routine is complicated and handles lots of cases, but let’s step through this simple case. Bear with me, I promise there’s a point!

The first step is to initialize ymm0 to zero, which is done by just xoring xmm0 with itself1.

VPXOR xmm0, xmm0, xmm0
> vpxor xmm0, xmm0, xmm0
vpcmpeqb ymm1, ymm0, [rdi]
vpmovmskb eax, ymm1
tzcnt eax, eax
vzeroupper

Here rdi contains a pointer to our string, so vpcmpeqb will check which bytes in ymm0 match our string, and stores the result in ymm1.

As we’ve already set ymm0 to all zero bytes, only nul bytes will match.

vpcmpeqb ymm1, ymm0, rdi
vpxor xmm0, xmm0, xmm0
> vpcmpeqb ymm1, ymm0, [rdi]
vpmovmskb eax, ymm1
tzcnt eax, eax
vzeroupper

Now we can extract the result into a general purpose register like eax with vpmovmskb.

Any nul byte will create a 1 bit, and any other value will create a 0 bit.

vpmovmskb eax, ymm1
vpxor xmm0, xmm0, xmm0
vpcmpeqb ymm1, ymm0, [rdi]
> vpmovmskb eax, ymm1
tzcnt eax, eax
vzeroupper

Finding the first zero byte is now just a case of counting the number of trailing zero bits.

That’s a common enough operation that there’s an instruction for it - tzcnt (Trailing Zero Count).

tzcnt eax, eax
vpxor xmm0, xmm0, xmm0
vpcmpeqb ymm1, ymm0, [rdi]
vpmovmskb eax, ymm1
> tzcnt eax, eax
vzeroupper

Now we have the position of the first nul byte, in just four machine instructions!

You can probably imagine just how often strlen is running on your system right now, but suffice to say, bits and bytes are flowing into these vector registers from all over your system constantly.

Zeroing Registers

You might have noticed that I missed one instruction, and that’s vzeroupper.

vzeroupper
vpxor xmm0, xmm0, xmm0
vpcmpeqb ymm1, ymm0, [rdi]
vpmovmskb eax, ymm1
tzcnt eax, eax
> vzeroupper

You guessed it, vzeroupper will zero the upper bits of the vector registers.

The reason we do this is because if you mix XMM and YMM registers, the XMM registers automatically get promoted to full width. It’s a bit like integer promotion in C.

This works fine, but superscalar processors need to track dependencies so that they know which operations can be parallelized. This promotion adds a dependency on those upper bits, and that causes unnecessary stalls while the processor waits for results it didn’t really need.

These stalls are what glibc is trying to avoid with vzeroupper. Now any future results won’t depend on what those bits are, so we safely avoid that bottleneck!

The Vector Register File

Now that we know what vzeroupper does, how does it do it?

Your processor doesn’t have a single physical location where each register lives, it has what’s called a Register File and a Register Allocation Table. This is a bit like managing the heap with malloc and free, if you think of each register as a pointer. The RAT keeps track of what space in the register file is assigned to which register.

In fact, when you zero an XMM register, the processor doesn’t store those bits anywhere at all - it just sets a flag called the z-bit in the RAT. This flag can be applied to the upper and lower parts of YMM registers independently, so vzeroupper can simply set the z-bit and then release any resources assigned to it in the register file.

Z-Bit

A register allocation table (left) and a physical register file (right).

Speculation

Hold on, there’s another complication! Modern processors use speculative execution, so sometimes operations have to be rolled back.

What should happen if the processor speculatively executed a vzeroupper, but then discovers that there was a branch misprediction? Well, we will have to revert that operation and put things back the way they were… maybe we can just unset that z-bit?

If we return to the analogy of malloc and free, you can see that it can’t be that simple - that would be like calling free() on a pointer, and then changing your mind!

That would be a use-after-free vulnerability, but there is no such thing as a use-after-free in a CPU… or is there?

Spoiler: yes there is 🙂

Zenbleed Demo

This animation shows why resetting the z-bit is not sufficient.

Vulnerability

It turns out that with precise scheduling, you can cause some processors to recover from a mispredicted vzeroupper incorrectly!

This technique is CVE-2023-20593 and it works on all Zen 2 class processors, which includes at least the following products:

AMD Ryzen 3000 Series Processors
AMD Ryzen PRO 3000 Series Processors
AMD Ryzen Threadripper 3000 Series Processors
AMD Ryzen 4000 Series Processors with Radeon Graphics
AMD Ryzen PRO 4000 Series Processors
AMD Ryzen 5000 Series Processors with Radeon Graphics
AMD Ryzen 7020 Series Processors with Radeon Graphics
AMD EPYC “Rome” Processors

The bug works like this, first of all you need to trigger something called the XMM Register Merge Optimization2, followed by a register rename and a mispredicted vzeroupper. This all has to happen within a precise window to work.

We now know that basic operations like strlen, memcpy and strcmp will use the vector registers - so we can effectively spy on those operations happening anywhere on the system! It doesn’t matter if they’re happening in other virtual machines, sandboxes, containers, processes, whatever!

This works because the register file is shared by everything on the same physical core. In fact, two hyperthreads even share the same physical register file.

Don’t believe me? Let’s write an exploit 🙂

Exploitation

There are quite a few ways to trigger this, but let’s examine a very simple example.

vcvtsi2s{s,d} xmm, xmm, r64
vmovdqa ymm, ymm
jcc overzero
vzeroupper
overzero:
nop

Here cvtsi2sd is used to trigger the merge optimization. It’s not important what cvtsi2sd is supposed to do, I’m just using it because it’s one of the instructions the manual says use that optimization3.

Then we need to trigger a register rename, vmovdqa will work. If the conditional branch4 is taken but the CPU predicts the not-taken path, the vzeroupper will be mispredicted and the bug occurs!

Optimization

Exploit Running

It turns out that mis-predicting on purpose is difficult to optimize! It took a bit of work, but I found a variant that can leak about 30 kb per core, per second.

This is fast enough to monitor encryption keys and passwords as users login!

We’re releasing our full technical advisory, along with all the associated code today. Full details will be available in our security research repository.

If you want to test the exploit, the code is available here.

Note that the code is for Linux, but the bug is not dependent on any particular operating system - all operating systems are affected!

Discovery

I found this bug by fuzzing, big surprise 🙂 I’m not the first person to apply fuzzing techniques to finding hardware flaws. In fact, vendors fuzz their own products extensively - the industry term for it is Post-Silicon Validation.

So how come this bug wasn’t found earlier? I think I did a couple of things differently, perhaps with a new perspective as I don’t have an EE background!

Feedback

The best performing fuzzers are guided by coverage feedback. The problem is that there is nothing really analogous to code coverage in CPUs… However, we do have performance counters!

These will let us know when all kinds of interesting architectural events happen.

Feeding this data to the fuzzer lets us gently guide it towards exploring interesting features that we wouldn’t have been able to find by chance alone!

It was challenging to get the details right, but I used this to teach my fuzzer to find interesting instruction sequences. This allowed me to discover features like merge optimization automatically, without any input from me!

Oracle

When we fuzz software, we’re usually looking for crashes. Software isn’t supposed to crash, so we know something must have gone wrong if it does.

How can we know if a a CPU is executing a randomly generated program correctly? It might be completely correct for it to crash!

Well, a few solutions have been proposed to this problem. One approach is called reversi. The general idea is that for every random instruction you generate, you also generate the inverse (e.g. ADD r1, r2 → SUB r1, r2). Any deviation from the initial state at the end of execution must have been an error, neat!

The reversi approach is clever, but it makes generating testcases very complicated for a CISC architecture like x86.

A simpler solution is to use an oracle. An oracle is just another CPU or a simulator that we can use to check the result. If we compare the results from our test CPU to our oracle CPU, any mismatch would suggest that something went wrong.

I developed a new approach with a combination of these two ideas, I call it Oracle Serialization.

Oracle Serialization

As developers we monitor the macro-architectural state, that’s just things like register values. There is also the micro-architectural state which is mostly invisible to us, like the branch predictor, out-of-order execution state and the instruction pipeline.

Serialization lets us have some control over that, by instructing the CPU to reset instruction-level parallelism. This includes things like store/load barriers, speculation fences, cache line flushes, and so on.

The idea of a Serialized Oracle is to generate a random program, then automatically transform it into a serialized form.

A randomly generated sequence of instructions, and the same sequence but with randomized alignment, serialization and speculation fences added.

movnti [rbp+0x0],ebx movnti [rbp+0x0],ebx
sfence
rcr dh,1 rcr dh,1
lfence
sub r10, rax sub r10, rax
mfence
rol rbx, cl rol rbx, cl
nop
xor edi,[rbp-0x57] xor edi,[rbp-0x57]

These two program might have very different performance characteristics, but they should produce identical output. The serialized form can now be my oracle!

If the final states don’t match, then there must have been some error in how they were executed micro-architecturally - that could indicate a bug.

This is exactly how we first discovered this vulnerability, the output of the serialized oracle didn’t match!

Solution

We reported this vulnerability to AMD on the 15th May 2023.

AMD have released an microcode update for affected processors. Your BIOS or Operating System vendor may already have an update available that includes it.

Workaround

It is highly recommended to use the microcode update.

If you can’t apply the update for some reason, there is a software workaround: you can set the chicken bit DE_CFG[9].

This may have some performance cost.

Linux

You can use msr-tools to set the chicken bit on all cores, like this:

# wrmsr -a 0xc0011029 $(($(rdmsr -c 0xc0011029) | (1<<9)))

FreeBSD

On FreeBSD you would use cpucontrol(8).

Others

If you’re using some other operating system and don’t know how to set MSRs, ask your vendor for assistance.

Note that it is not sufficient to disable SMT.

Detection

I am not aware of any reliable techniques to detect exploitation. This is because no special system calls or privileges are required.

It is definitely not possible to detect improper usage of vzeroupper statically, please don’t try!

Conclusion
It turns out that memory management is hard, even in silicon 🙂

Acknowledgements

This bug was discovered by me, Tavis Ormandy from Google Information Security!

I couldn’t have found it without help from my colleagues, in particular Eduardo Vela Nava and Alexandra Sandulescu. I also had help analyzing the bug from Josh Eads.

3DChiplet Side By Side 3D Magic with 3D Trenching

3DChiplet Side By Side 3D Magic with 3D Trenching 2021-2023

3D Fabric 5800X3D is hard in production but the delivery is the problem so ... i have another proposal,

Called 

Side By Side 3D Magic (c)Rupert S


Yes 3D Chips are good for cache, Simply connecting chiplets does not require 3D or 3D Stacking,

Side By Side 3D Magic (c)Rupert S

https://science.n-helix.com

Has Layered Chip wafer & PCB Board with interweaved wires:

Carbon fibers, Copper or aluminum or Iron, Not a problem

Through the PCB Chip board, These micro tunnels provide all the PCI & Chip tunnels that a Board could require!

Layered micro tunnel imprinted PCB can have 3 wires per layer (crosswise, Diagonal & Ordered form)

Additionally tunneling up and down is not a problem for you simply layer a connection point that is welded to the next layer as it is laid on top..

Micro film is available, As this is both electrostatic & noise resistant composite.

Since this is a micro multiformat PCB / Chip fabric, At no time do you have to worry about dampness or heat split when made well.

https://www.youtube.com/watch?v=pBZQeW1eeEw

Example of 3D Layered PCB, A but too rigid but good for a phone or telescope Board..

Chips can be placed inside if you need to! for space reasons; Embed the chiplet..

PCB is ideal for this task; Common view PCB is large space & coy compact?

3D PCB is a space saver & 3D Network Ethernet/Chip IO memory ops

PCB Wire mesh (internal networks) = - |, PCB Layer = _

______(CHIP With Connect)________
----------|-----|-----|----|----|-----------------
_______\____|___\___\_|___________
--------(cooling & IO Chip)--------------
_______|__|_______|___|___________


***********

07:39 23/07/2023 (c)Rupert S

Circuit 3D Print with laser (c)RS


While trenching semiconductors work, in space (vacuum) electrical energy transfers through vacuum!

So you have to use a resistor material in the trench, this is not impossible if you imbed ceramic formulas with a laser!

you can however with this technology go upto 2.7v on 5nm; Because higher voltages are faster & more resistant; this makes sense..

The trench (hole) Formatic processor 3D layering technology with:

Circuit = C, Trench = \_/ , resistor = r, Circuit in trench = c, raised bit Circuit or resistor = /C\

C\r/C C\r/C C\r/C

C\_/C C\_/C C\_/C

C\_/C C\r/C C\_/C

/C\c/C\r/C\r/C\r/C\

The challenge of using traditional circuit printing methods in space is that the vacuum can cause the circuit to degrade over time..

This is because the vacuum can strip away the electrons that carry current in the circuit.

3D laser circuit printing could help to mitigate this problem by creating a very dense and compact circuit. This reduces the surface area of the circuit that is exposed to the vacuum and it helps to protect the circuit from the harsh environment of space.

& Also..

One of the challenges of using trench & processor circuit methods in space is that electrical energy transfers through vacuum; Which can be difficult in a vacuum.

This means that you need to use a resistor material in the trench,

It is possible to imbed ceramic formulas with a laser; This could be a promising way to create resistors in/for space.

However, 3D laser circuit printing could help to mitigate this problem; As the laser can be used to create a very precise and durable circuit.

This technology is meant for the world but also with spatial integrity for deep space & So functionally Rugged/Rigid in use & Function.

Additional thoughts on the challenges and potential of 3D laser circuit printing for space applications:

Challenges:
The vacuum of space can be very harsh on materials, so it is important to use materials that are resistant to radiation and temperature extremes.

Potential:

3D laser circuit printing could allow for the creation of more complex and efficient circuits.

3D laser circuit printing could make it possible to print circuits on-demand; Which could be a major advantage for space missions.

It could also be used to create circuits that are more resistant to the harsh environment of space.

The lack of gravity can also make it difficult to print precise circuits..

(c)Rupert S

Application 23/07/2023

https://science.n-helix.com/2023/07/3dchiplet.html

https://science.n-helix.com/2023/06/map.html

https://science.n-helix.com/2023/06/ptp.html

https://science.n-helix.com/2023/06/tops.html

https://science.n-helix.com/2022/01/ntp.html


*********************

Tilly Arms; The girl with no arms, sympathetic nerve response & frequency rate : Operation Cyborg RS 2023

Tilly Arms; The girl with no arms

I think that the arms are very good, But she needs more!
Clearly artificial skin in silver would do the trick?

I noticed that she has control of them though her stimulated skin.... at the elbow....
Now i saw a study that clearly would help....

Neurons respond on training to noisy signals- & clear notes+

We can clearly get a sympathetic skin monitor to receive the feelings; By listening to skin cell responses ....

Now i feel that since a 9v battery stings the tongue; 2volts is about a bit too much right on sweaty skin, So 1.8 is around right? Dr

https://www.youtube.com/shorts/pmIoL-Ja_Co

Depending upon how much resistance there is in skin, might even help with Lightening & Shocks...

RS

20:08 23/07/2023 What have we learned; Brain Cells : RS : https://www.youtube.com/watch?v=bEXefdbQDjw

Brain Cells respond to:

Clear tones : } well to { Entropic Noisy tones }: unwell
Clean Image } to [ Entropic Noisy Image }

Cell electrode networks begin at 0.75cm for tasks like DOOM

Cell inputs are learned,
Dynamic connections form to the electrodes & We use logic on the inputs...

Here the strategy is to use tones & noise to respond to the doom player in motion.

The cell structure is clearly not a problem at 3700 * 4 mm

Rupert S

*

AnPa_Wave - Analogue Pattern Wave Vector SiMD Unit : (c)RS


The base symphony is harmony, In other words waveforms; There are a couple of Simple methods that really work:

High performance Float values F16, F32, F64, FPU

Q-Bit Quantum; All forms of Quantum wave work
Radio waves;
Light patterns
Photon wave patterns; single & multiple
Sound hardware; 1 to 3 Bit DAC; Audio conversions; Sample range
Analogue chips that work on harmony & frequency
SVM Elliptic curve maths
Sin, Arc, Tan, Time, Vector

In essence Harmony & frequency is the equivalent of Complex Elliptic curve maths

A Music note score suffices to specify harmony basics:

Waveform shape in 3D
Harmony / Disharmony
Vibration High / Vibration Low
Power High / Power Low
Volts High / Volts Low
Watts High / Wats Low

(c)Rupert S

https://science.n-helix.com/2023/07/3dchiplet.html

https://science.n-helix.com/2023/06/map.html

Wonderful Wave-Pattern Analogue waveforms in meta materials - Pattern recognition in reciprocal space with a magnon-scattering reservoir
https://www.nature.com/articles/s41467-023-39452-y.pdf