#### Brain Bit Precision Int32 FP32, Int16 PF16, Int8 FP8, Int6 FP6, Int4? Idealness of Computational Machine Learning ML TOPS for the human brain:

Brain level Int/Float inferencing is ideally in Int8/7 with error bits or float remainders

Comparison List : RS

48Bit Int+Float Int48+FP48 (many connections, Eyes for example) HDR Vison

40BitInt+Float Int40+FP40 HDR Basic

Int16 FP32

Int8 Float16(2Channel, Brain Node)(3% Brain Study)

Int7 (20% Brain Study)

Int6 (80% Brain Study)

Int5 (Wolves (some are 6+))

Int4 (Sheep & worms)

Int3 (Germ biosystems)

Statistically a science test stated 80% of brains in man quantify Bit at 6 20% to 7Bit

XBox X & PlayStation 5 do down to INT4Bit (quite likely for quick inferencing)

Be aware that using 4 bit Int instructions .. potentially means more instructions used per clock cycle & more micro data transfers..

Int8 is most commonly liable to quantify data with minimum error in 8Bit like the Atari STE or the Nintendo 8Bit..

Colour perception for example is many orders of magnitude higher! Or 8bit colours EGA is all we would use..

16Bit was not good enough.. But 32Bit suites most people! But 10Bit(x4) 40Bit & Dolby 12Bit(x4) 48Bit is a luxury & we love it!

#### Restricted Boltzmann ML Networks : Brain Efficient

I propose that SIMD of large scale width & depth can implement the model :

Restricted Boltzmann Machines (RBMs) have been proposed for developing neural networks for a variety of unsupervised machine learning applications

Restricted Boltzmann Machines utilize a percentage correctness based upon energy levels of multiple node values; That represent a percentage chance of a correct solution,

My impression is that Annealer machine simply utilise more hidden values per node on a neural network,

Thus i propose that SIMD of large scale width & depth can implement the model..

A flexible approach is to experiment with percentages from a base value...

100 or 1000; We can therefore attempt to work with percentiles in order to adapt classical computation to the theory of multiplicity.

SiMD in parallel can; As we know with RISC Architecture ..

Attempt to run an ideal network composing many times Factor & regression learning model..

Once the rules are set; Millions of independent IO OPS can be performed in cyclic learning,

Without sending or receiving data in a way that interferes with the main CPU & GPU Function..

Localised DMA.

"Adaptive hyperparameter updating for training restricted Boltzmann machines on quantum annealers"

Adaptive hyperparameter updating for training restricted Boltzmann machines on:

Quantum annealers

Wide Path SiMD

"Restricted Boltzmann Machines (RBMs) have been proposed for developing neural networks for a

variety of unsupervised machine learning applications such as image recognition, drug discovery,

and materials design. The Boltzmann probability distribution is used as a model to identify network

parameters by optimizing the likelihood of predicting an output given hidden states trained on

available data. Training such networks often requires sampling over a large probability space that

must be approximated during gradient based optimization. Quantum annealing has been proposed

as a means to search this space more efficiently which has been experimentally investigated on

D-Wave hardware. D-Wave implementation requires selection of an effective inverse temperature

or hyperparameter (β) within the Boltzmann distribution which can strongly influence optimization.

Here, we show how this parameter can be estimated as a hyperparameter applied to D-Wave

hardware during neural network training by maximizing the likelihood or minimizing the Shannon

entropy. We find both methods improve training RBMs based upon D-Wave hardware experimental

validation on an image recognition problem. Neural network image reconstruction errors are

evaluated using Bayesian uncertainty analysis which illustrate more than an order magnitude

lower image reconstruction error using the maximum likelihood over manually optimizing the

hyperparameter. The maximum likelihood method is also shown to out-perform minimizing the

Shannon entropy for image reconstruction."

(c)Rupert S

Example ML Statistic Variable Conversion : Super Sampling Virtual Resolutions : Talking about machine learning & Hardware functions to use it/Run it; To run within the SiMD & AVX feature-set.

For example this works well with fonts & web browsers & consoles or standard input display hubs or User Interfaces, UI & JS & Webpage code.

In the old days photo applications did exist to use ML Image enhancement on older processors..

So how do they exploit Machine Learning on hardware with MMX for example ?

Procedural process data analytics:

Converting large statistics data bases; On general Tessellation/Interpolation of images

The procedural element is writing the code that interpolates data based upon the statistics database...

Associated colours..

Face identity...

Linearity or curvature...

Association of grain & texture...

Databases get large fast & a 2 MB to 15MB Database makes the most sense...

Averages have to be categorized by either being worthy of 2 Places in the database or an average..

You can still run ML on a database object & then the points in the table are called nodes!

Indeed you can do both, However database conversion makes datasets way more manageable to run within the SiMD & AVX feature-set.

However the matter of inferencing then has to be reduced to statistical averages & sometimes ML runs fine inferencing this way.

Both ways work, Whatever is best for you & the specific hardware.

(c)Rupert S

**

### DL-ML slide : Machine Learning DL-ML

By my logic the implementation of a CPU+GPU model would be fluid to both..

Machine Learning : Scientific details relevant to DL-ML slide (CPU,GPU,SiMD Hash table(M1 Vector Matrix-table +Speed)

The vector logic is compatible to both CPU+GPU+SiMD+AVX.

Relevant because we use Vector Matrix Table hardware.. and in notes the Matrix significantly speeds up the process.

(Quantum Light Matrix)

The relevance to us is immense with world VM servers

DL-ML Machine Learning Model compatible with our hardware

By my logic the implementation of a CPU+GPU model would be fluid to both..

The vector logic is compatible with both CPU+GPU.

However this is a model we can use & train..