Monday, February 19, 2018

programmable logic structures

How to really make inline ram and processing PLS - programmable logic structures.

Patent Rupert S

first of all you have to realize that the scale of the ram matters...

Two you have to matrix the ram module between the processing units..

on the die the ram modules do not nessarily have to be exactly matrixed between processing structures:

SIMD
FPU
Integer float
GPU - integer - float - matrix ram - cache - storage - EEC error correction
FPMG - reprogramable - neurological - classic evaluation
comparison theory - resistor logic (c)RS
ecetera

matrixed cross section, involves more wiring than line by line...

in line allow for micro channel fiber..
Inline channeling is a logical choice and considering 3D circuite designs a most probable solution..
Additionally the use of inline allows for wider data buffering and therfore for increased complexity of workload.
Threading involves passing data Over,Under,Through,sideways or around.

Each model has specific advantages

Passthough = Additional modification.
Pass around = lack of circute depth nessesity.
3D = adaptable matrix but less heat loss and increased noise (can be managed and filtered.

Matrixed allows for more processing capacity to the ram and can still be micro channeled...

Classic crossbaring allows the matrix to be channeled to other unit's in the grid..
This is fast and however the importance of using compressed circuite design is very important..

3D - Matrixed allows for more processing capacity to the ram and can still be micro channeled...

Classic crossbaring allows the matrix to be channeled to other unit's in the grid..
This is fast and however the importance of using compressed circuite design is very important..
With 3 Dimensional design the network can combine both cross bar and light/Energy fiber channeling.

Overall 3D Matrixing is more liable to fail, to be more brittle and fragile..
However this design is a lot more capable and in addition will involve the capacity of variable data channel width.

(Copyright) Rupert S