Monday, February 19, 2018

programmable logic structures

How to really make inline ram and processing PLS - programmable logic structures.

Patent Rupert S

first of all you have to realise that the scale of the ram matters...

Two you have to matrix the ram module between the processing units..

on the die the ram modules do not necessarily have to be exactly matrixed between processing structures:

SIMD
FPU
Integer float
GPU - integer - float - matrix ram - cache - storage - EEC error correction
FPMG - re-programmable - neurological - classic evaluation
comparison theory - resistor logic (c)RS
ecetera

matrixed cross section, involves more wiring than line by line...

in line allow for micro channel fibre..
Inline channelling is a logical choice and considering 3D circuit designs a most probable solution..
Additionally the use of inline allows for wider data buffering and therefore for increased complexity of workload.
Threading involves passing data Over,Under,Through,sideways or around.

Each model has specific advantages

Pass-though = Additional modification.
Pass around = lack of circuit depth necessity.
3D = adaptable matrix but less heat loss and increased noise (can be managed and filtered.

Matrixed allows for more processing capacity to the ram and can still be micro channelled...

Classic cross-barring allows the matrix to be channelled to other unit's in the grid..
This is fast and however the importance of using compressed circuite design is very important..

3D - Matrixed allows for more processing capacity to the ram and can still be micro channelled...

Classic cross-barring allows the matrix to be channelled to other unit's in the grid..
This is fast and however the importance of using compressed circuit design is very important..
With 3 Dimensional design the network can combine both cross bar and light/Energy fibre channelling.

Overall 3D Matrixing is more liable to fail, to be more brittle and fragile..
However this design is a lot more capable and in addition will involve the capacity of variable data channel width.

(Copyright) Rupert S

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