FPU double precision : mathematical errors: Thoughts and questions

FPU double precision mathematical errors: Thoughts and questions  

https://lhcathome.cern.ch/lhcathome/forum_thread.php?id=5317

Double precision maths is luckily the modern CPU core FPU feature..
Precision of 2 errors over 1000000 result will mean one or two errors per trillion calculations,
However feasible perfectly error free results are..
The net result is believably within the error factor posed by Intel guidelines.

Error free incites perfect pre-fetch and super class stability,
The facts remain the same on error count:

AVX float buffer overrun,
FPU Buffer overrun.
Rounded results.

Most plausibly a buffer over run.
Consistently very high precision numbers require a 180 bit buffer...
Around 16KB stack buffer should prevent overflow (per result)
Compressing the resultant into a compressed memory zip saves data space.

(c)Rupert S

perhaps this will help: http://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html

http://science.n-helix.com/2019/05/compiler-optimisation.html

http://science.n-helix.com/2018/06/compression-libraries-index-prime.html

http://science.n-helix.com/2020/01/float-hlsl-spir-v-compiler-role.html

"My priority is to publish "IEEE 754 as intended - or how to
obtain identical double precision floating-point results".

SixTrack LHC@home is running well but tasks are
still being taken rather slowly and I reckon we use,
at best, one third of your provided capacity. Still your
support is vital for the High Luminescent LHC studies.

Personally I have a couple of issues:
I need to access old migrated data to define SixTrack
performance and this is a problem right now.
While the Invalid result error rate is in general very low,
24 Invalid and over one million valid today, I need to
identify the genuine computational errors.

You can find my recent CERN Open Days presentation at
http://mcintosh.web.cern.ch/mcintosh/
along with the state of my research.
Eric Mcintosh"

Coronavirus

Examination of Corona virus :

Apparent symptoms "fever, coughing and muscle aches"

Possible sources of infection ..Sweat .. possibly if mixed with infected blood/puss
Breath? "possibly cough"
Infected meat ?
"Corona virus is complex and most probably has a low heat sensitivity"
"Possibly responds to cool air well & low humidity"
Rupert S

"Thailand has confirmed its fifth case of the new Corona virus.

"The patient is a 33-year-old woman from Wuhan on vacation," deputy public health minister Sathit Patucha told Reuters, adding she was under quarantine at Rajavithi hospital and her condition was improving.

The woman arrived in Bangkok on Tuesday with her daughter and visited a private hospital complaining of a fever, coughing and muscle aches before being transferred to a government hospital on Thursday.

Her daughter tested negative for the virus.
Samuel Osborne
24 January 2020 10:44"

https://www.independent.co.uk/news/world/asia/coronavirus-news-live-death-toll-latest-symptoms-wuhan-uk-china-us-sars-a9299716.html

Symptom statistics: 99 patients minority report

99 had Inflammation of lung tissue & high liquidity issues
82 had fever
81 had a cough
31 had shortness of breath
11 had muscle ache
nine had confusion
eight had a headache
five had a sore throat

https://www.thelancet.com/journals/lancet/article/PIIS0140-6736%2820%2930211-7/fulltext

https://www.thelancet.com/action/showPdf?pii=S0140-6736%2820%2930211-7

Features of the disease Corona Virus China throughout the active phase:

Can include multiple organ failure & Auto-immune response/overload on rare cases.

https://www.thelancet.com/journals/lancet/article/PIIS0140-6736(20)30183-5/fulltext

https://www.thelancet.com/action/showPdf?pii=S0140-6736%2820%2930183-5

Further details : Corona:

Infection occurs before symptoms most probably & also during infection symptom display

Incubation period 5 days to 2 weeks, Infection rate probable around 3% per hour..

"Based on the first 425 confirmed cases in China, each infection led to 2.2 others on average"
"mortality rate potential 2% to 3%"

https://apnews.com/910032f504fd6931ec1750939c4e862d

We are the minority: China : UN : World

Solve data : https://is.gd/MicroAnonimaData

WHO OutBreak

WORLD Community Gains Nobel Prize for solving WORLD Raid Virus Event

https://apnews.com/b2810cebad305f66112a0c68be0f8c9a

https://apnews.com/VirusOutbreak

We are the minority: China : UN : World
Solve data : https://is.gd/MicroAnonimaData

Public awareness grows with new corona virus!:

https://www.bbc.com/news/world-51338899 - vaccine creation video & world statistics

Situation report WHO:

https://www.who.int/emergencies/diseases/novel-coronavirus-2019/situation-reports/

Technical guidance WHO:

https://www.who.int/emergencies/diseases/novel-coronavirus-2019/technical-guidance

Information corona:

https://www.bbc.com/news/health-51214864 - Symptoms

https://www.bbc.com/news/world-asia-china-51176409 - Recovery Illness

https://www.youtube.com/watch?v=OZcRD9fV7jo&feature=emb_logo

https://www.paho.org/hq/index.php?option=com_content&view=article&id=15696:coronavirus&Itemid=4206&lang=en

https://www.paho.org/hq/index.php?option=com_jem&view=event&id=349:who-s-public-consultation-on-human-genome-editing&lang=en

high priority : https://www.paho.org/hq/index.php?option=com_content&view=article&id=13708:migration-health-americas&Itemid=72502&lang=en

Science facts corona:

https://www.thelancet.com/journals/lancet/article/PIIS0140-6736%2820%2930211-7/fulltext

https://www.thelancet.com/action/showPdf?pii=S0140-6736%2820%2930211-7

Identifying active damage to bio systems with active virus

https://www.thelancet.com/journals/lancet/article/PIIS0140-6736(20)30183-5/fulltext

https://www.thelancet.com/action/showPdf?pii=S0140-6736%2820%2930183-5

Rupert S https://science.n-helix.com 

Float, HLSL & SPIR-V Compiler Role

Float, HLSL & SPIR-V Compiler Role
(c)RS

Vulkan 1,1.2,1.3+ & DX10,11,12+ , HLSL & SPIR-V
Rule sets : Float,Vector,AVX,SiMD

General Instruction Optimisation Procedure  & Vulkan/DX Shader stack.

HLSL & SPIR-V Compilers jobs are to streamline code into efficient Float & SiMD,Vector,AVX Instruction sets that do the maths in the order most efficient for clock cycle use & Instruction load,store & set cycles.

HLSL & SPIR-V should be optimisation compiler sub-rules for valid Vector,AVX,SiMD instructions.
Complex maths is 90% going to be float & SiMD instruction are clock cycle optimiser's for uncomplicated maths with multiple vectors.

General Instruction Optimisation Procedure  & Vulkan/DX Shader stack.

Firstly the SiMD Shader base language is Assembler with script balanced scripting models

GPU: AMD,NVidia,STI,ARM,Intel ,RISC sets(IBM,Cisco,Del,HP,Fujitsu,Sun,Subset Micro-Processors,Thunder 2,CISC: AMD,Intel, IBM
(Others Exist.)

Basic instruction strategy of SiMD & Float adaptation of the main concerns for all programming models that funnel into SiMD/AVX/Vector & broadly Float..

HLSL,SPIR-V Code is a layer 2 abstraction over the code base Vectored Instruction Set,
Conceptually the baggage is imagining that there is a limitation to level 3 C Code..
Well as SiMD/Vector/AVX/Float is a Algebra maths formula, The basic solution is algebra.

Algebra is the super set within which Shader code exists as a subset of Float,
Understanding this fact is key to understanding the concept.

The role of the shader layer shall be divided into two parts:
Complex maths : (Integer, Float) & Simple Maths with multiple dataset values.

Firstly the Coder separates the two layers that solve the maths algebra.
(FLOAT)The complex maths Objects(Algebra) & (Vector,AVX,SiMD)the Vector rule set Objects.

Examples:
Polygon (float) Values = Result A,B,C & then Vector to tessellation
Preferably we have the polygons worked out and saved in ram & then we tessellate.

Vector Instruction: Memory Loaded Objects (A,B,C,D,Ecetera)
Instruction sets of bit swaps being common in Interpolation & Anti Aliasing for example.

Vector instruction sets : AVX are in principle to redice CPU Cycle count on multiple Object(A,B,C,D) Simple Maths without testing the rule sets.

The world of Vector involves Bit Swaps (More complex algebra)
& Simple Mul (Multiply) + - & Division /

Bit swapping data sets appears to be a key player in SiMD/AVX
So arguing about Float matters.. and the role of Vector instruction is clearly defined as increasing instruction count per clock cycle for a limited instruction set.

Understanding efficiency is the object of the compiler & we have to test the instruction speed & efficiency versus FLOAT..

Bit Swaps are 3 Float instruction cycles for example versus 1 in AVX; With series of Objects to swap,
Series of 4 for example.

Float &Integer maths Instructions:

Dimensional code such as 3D Polygons,Curves,Ellipses,FTT,Blast & Maths related to vectored noise reduction such as Analogue Vacuum Tube Maths; Indeed Ohms law for example.

So imagine a world where simple algebra is the law, So algebra is soon complicated & involves 3 roll loops.

For example:

For A = 3, C = EMC², D = Entropy, E = Energy

therfor A + B

B = ( G = ( F - ((D/C)+(E*C))))

Exumé Temré
Vector is to simplify cycle, Float is to explain the butterfly

https://science.n-helix.com/2019/05/compiler-optimisation.html

https://www.khronos.org/blog/hlsl-first-class-vulkan-shading-language

(c)Rupert Summerskill

CPU & GPU Problem Solutions

CPU & GPU Problem Solutions: Updates happen

Screen flicker Problems Games & Browsers/OS:

The reason for the flicker may be because of ram page overlap in the pre-fetch/Buffer... due to large ram sizes in the PCI fetch...
Glitching may occur with a low level driver with exceptionally low levels of buffer / Stack cache...The suggested frame buffer is 3 frames,

I optimise Frame cache to 7 the octagonal source code requirements of fetch and pre-fetch CPU/GPU processing tip should be overlapped by a pre organised DMA Compressed data fetch...The same goes for fibre channel architecture..

The frame buffer automatically allocates a loose Paging system.. flex Muscle: Align code & RAM Fetch/Write to Kilobyte Order boundary.

Ordered to be data aligned with the requirements of the cache cycle and data size...

64Bit processors order on 4Kb boundaries minimum up to 64Kb optimum... Larger buffers can afford to lose a 1 to 63 KB but not more to obtain optimum ram boundary aligned cache burst DMA Cache fetch & set/write.

In Vulkan and DX12 over estimated buffer may introduce latency, DMA Cached fetch is the answer.

(c)Rupert S

****

https://science.n-helix.com/2019/06/kernel.html

https://science.n-helix.com/2019/06/vulkan-stack.html

https://science.n-helix.com/2016/04/3d-desktop-virtualization.html

https://science.n-helix.com/2017/02/open-gaming.html

https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html

https://science.n-helix.com/2019/05/compiler-optimisation.html

Compiler books & reading : https://science.n-helix.com/2017/04/boinc.html

Vectored code : tessellation & other functions using SIMD & Compute Shader maths:
https://www.youtube.com/watch?v=0DLOJPSxJEg

Classic Physics

Theorem : Classic Physics : a Relative Version of events ATOMIC : RS

Classic physics presents the electron as a non quantum event: several versions available

Electrons may move though another dimension when tied to the proton...

the electron passes over a dimensional quartet, A symphony of harmony & attraction..

List : 1A Devastation (Classic Harmony)

By moving in 1 (rotating relative to atom)

2 that rotate on 2 axis around the central point of the atom..
Regard this event as moving on two axis relative to energy requirements to be lower or higher..
the energy is potentially an axis.

By regarding the Energy axis as dimensional; The 3 axis appear in reality..
However the electron moves though such speed in the hyperial dimension..
Hyper space or and subspace,
In & out relative to gravity axis AKA The gravity well or Expansion event : Time horizon.

Potentially the electron appears to be located partially in the place a quanta of electron potential would appear..

So doing the electron may be of any size we desire (In subspace) Potentially representing appearance in reality as the presence of a small field (Known to us as the Electron).

Field representation of all Mass & Mass-less objects; Does create the potential to support holographic presentation & Classic science views of solid & robust nature.

Classic views are thus .. Preserved in argument of holographic, Quanta & New Age Theories.

Dimensions are in effect free, Travelling in them is the thing that costs energy & effort.

(C)Rupert S

https://science.n-helix.com/2019/10/black-hole-core.html

https://science.n-helix.com/2018/05/matrix-of-density.html

Spinning vortex : Black holes in the centre of metal core planets : Planet Core Theory

Spinning vortex : Black holes in the centre of metal core planets : 

Planet Core Theory:

reaction and mass : heat and energy

To surmise the heat created influencing electrons in the core excites matter so much that energy of atoms feeds the black holes speed,
However the energy of the matter is greater than can be absorbed by atom sized black holes.

Smashing electrons at the excitement levels of the core into smallish black-holes proves hard and luckily.. saves worlds from the energy absorbing capacity of smaller black holes..

Theory: The event horizon absorption energy (negative) is less than absorbed electrons with core heat from metal core (magnetic)

Magnetism is preserved and engendered by black hole heat and frantic chaotically inclined balanced centripetal motion..

Strong energies create the necessary speed & energy to prevent absorption of core mass.

(c) Rupert S  https://science.n-helix.com/2018/05/matrix-of-density.html

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QUAKE SERVER : Multi Terabyte Node, Dynamic access maps
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Star wars Online
Star-trek Online

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Amazingly the revolutionary TACC Wrangler ML System offers priority one multi port 10GB Ethernet with internet access of less than 15ms latency.. High security & key location in Texas Arizona..

Wonderful news.

https://www.cloudflarestatus.com/

https://portal.xsede.org/allocations/announcements

https://portal.xsede.org/resource-monitor

https://is.gd/ProcessorLasso

Rupert S

****

VPS : Serious business expansion:

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