Friday, June 10, 2022

JIT Compiler

Driver & Firmware Integrated JIT Compiler (c)RS

Driver & Firmware Integrated JIT Compiler - DPIC Display Protocol Indirect Compute 2022

Presenting JIT for hardware interoperability & function : https://is.gd/DisplaySourceCode

Integrated JIT Compiler directly into a Shader & OpenCL / Direct Compute Driver Ethernet Protocol Socket & IP

To & from all devices though Firmware Central JIT Compute Compiler

Computation tasks can be carried out by all installed Hardware & USB / Plugged devices:

WebGPU
Python
JavaScript
WebCL, OpenCL & Direct Compute
JIT compiled maths

Indirect Computation such as maths in Application : WebGPU, WebCL, OpenCL & Direct Compute.

Utilising Computation is as simple as having a V8 WebGPU function available,

May be directly available from the GPU without accessing the CPU if SDK is directly supported in GPU RAM...

So in the case of a TV BlueRay Player as an example; We may infact simply be able to integrate..

HTTPS: WebGPU, WebCL, OpenCL & Direct Compute & Methods such as JIT compiled maths.

The plan we use is to; Integrate JIT Compiler directly into a Shader & OpenCL / Direct Compute Driver Ethernet Protocol Socket & IP

Computation tasks can be carried out by all installed Hardware & USB / Pluged devices,

To & from all devices though Firmware Central JIT Compute Compiler

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Kernel Method requires around 20Kb + Cache Kernel run on OpenCL &or Direct Compute,
Closest device runtime &or Operation infrastructure procedure call.

In the case examples:

Camera focus OpenCL Kernel Ofload
(Edge detect, No image : edges & 4pixels with gradient with jpg compression)

Audio device with buffers OpenCL Kernel Ofload
(processing input is from CPU to Audio Device : Simple Objective Pre Processing case)

SSD & HDD Firmware OpenCL Kernel Ofload
(Location & Write & Math proof of safe write &or read, Error correction)

Printer OpenCL Kernel Ofload
In the case of the printer the postscript driver "Is NOT" installed in your router,
The router prints but has basic drivers,

OpenCL Kernel Ofload (from printer),
Makes the task of processing a Postscript Font & Curl Angle print; Easy!

If you have a USB Hub with processor,
The Postscript Instruction Set is processed as OpenCL Vector Print

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DPIC Device Protocol Indirect Compute Hub

Proposed HDMI/DisplayPort Hub (also GPU Processed)
Proposed USB Hub,
Proposed Bluetooth Hub,
Proposed WiFi Hub
Proposed Ethernet/Net Hub

with
50Mhz to 800Mhz processor with Dynamic Eco settings
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On the aspect of HDMI & DisplayPort HTTP Ethernet protocol - DPIC Display Protocol Indirect Compute 2022 (c)RS https://bit.ly/VESA_BT

On the aspect of HDMI & DisplayPort HTTP Ethernet protocol; Several forms of Computation exist as possible for the equipment involved : Televisions, Monitors & GPU & CPU

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(c)Rupert S https://bit.ly/VESA_BT

Research topic RS : https://is.gd/Dot5CodecGPU https://is.gd/CodecDolby https://is.gd/CodecHDR_WCG https://is.gd/HPDigitalWavelet https://is.gd/DisplaySourceCode

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Example : JIT Optimise Dynamic code - DPIC Device Protocol Indirect Compute

Audio/Video/GPU/CPU/Urt/USB/BT : hardware to slow or fast? trade Processor Resources : How? DCP:JIT

Camera Focusing API for Web : Application,
Because Computers surely focus a camera better if we use DPIC : Device Compute
Processing JIT Compiler,
Then Latency is not the issue!

Video & Audio can do with additional processing : How? DCP:JIT

Monitor would be able to do so much more! With additional processing : How? DCP:JIT

Kernel Method requires around 20Kb + Cache Kernel run on OpenCL &or Direct Compute,
Closest device runtime &or Operation infrastructure procedure call.

Tier processing; Objectives:

High quality process,
Performance,
Shared workload,
Appropriate Computing unit

In the case examples:

Camera focus OpenCL Kernel Ofload
(Edge detect, No image : edges & 4pixels with gradient with jpg compression)

Audio device with buffers OpenCL Kernel Offload
(processing input is from CPU to Audio Device : Simple Objective Pre Processing case)

SSD & HDD Firmware OpenCL Kernel Offload
(Location & Write & Math proof of safe write &or read, Error correction)

Printer OpenCL Kernel Offload
In the case of the printer the postscript driver "Is NOT" installed in your router,
The router prints but has basic drivers,

OpenCL Kernel Offload (from printer) > (from USBHub : Some) > (Router back to printer),
In an ideal situation the Kernel processes the next tier up; In this case Pro-USBHub;
Leaving the router process free but with a very high quality printing job done.

Makes the task of processing a Postscript Font & Curl Angle print; Easy!

If you have a USB Hub with processor,
The Postscript Instruction Set is processed as OpenCL Vector Print

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DPIC Device Protocol Indirect Compute Hub

Proposed HDMI/DisplayPort Hub (also GPU Processed)
Proposed USB Hub,
Proposed Bluetooth Hub,
Proposed Wifi Hub
Proposed Ethernet/Net Hub

with
50Mhz to 800Mhz processor with Dynamic Eco settings
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(documents) JIT & OpenCL & Codec : https://is.gd/DisplaySourceCode

Friday, April 1, 2022

VecSR - Vector Standard Render

VecSR - Vector Standard Render


VESA Standards : Vector Graphics, Boxes, Ellipses, Curves & Fonts : Consolas & other brilliant fonts : (c)RS

Vector Compression VESA Standard Display protocol 3 : RS

SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts

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32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)
(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second

Security Relevant Extensions
SVM : Elliptic Curves & Polynomial graphs & function
AES : Advanced Encryption Standard Functions
AVX : 32Bit to 256Bit parallel Vector Mathematics
FPU : IEEE Float Maths
F16b : 16Bit to 32Bit Standards Floats
RDTSCP : Very high precision time & stamp

Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1

Photos & Performance https://is.gd/4447GamerWEBB


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OT-SVG Fonts & TT-SVG Obviously Rendered in Direct X 9+ & OpenGL 3+ Mode & Desktop Rendering modes


Improve Console & TV & BIOS & General Animated Render

Vector Compression VESA Standard Display protocol 3 : RS

SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts
Improve Console & TV & BIOS & General Animated Render

Vector Display Standards with low relative CPU Weight
SiMD Polygon Font Method Render

Default option point scaling (the space) : Metadata Vector Fonts with Curl mathematical vector :

16 Bit : SiMD 1 width
32 Bit : SiMD Double Width

High precision for AVX 32Bit to 256Bit width precision.

Vectoring with SiMD allows traditional CPU mastered VESA Emulation desktops & safe mode to be super fast & displays to conform to VESA render standards with little effort & a 1MB Table ROM.

Though the VESA & HDMI & DisplayPort standards Facilitates direct low bandwidth transport of and transformation of 3D & 2D graphics & fonts into directly Rendered Super High Fidelity SiMD & AVX Rendering Vector

Display Standards Vector Render : DSVR-SiMD Can and will be directly rendered to a Surface for visual element : SfVE-Vec

As such transport of Vectors & transformation onto display (Monitor, 3D Unit, Render, TV, & Though HDMI, PCI Port & DP & RAM)

Directly resolve The total graphics pipeline into high quality output or input & allow communication of almost infinite Floating point values for all rendered 3D & 2D Elements on a given surface (RAM Render Page or Surface)

In high precision that is almost unbeatable & yet consumes many levels less RAM & Transport Protocol bandwidth,

Furthermore can also render Vector 3D & 2D Audio & other elements though Vector 'Fonting' Systems, Examples exist : 3D Wave Tables, Harmonic reproduction units for example Yamaha and Casio keyboards.

RGBA Composite Layer X-OR


RGBA Can simply be the shape printed onto alpha layer; Wide Transparency effect.
RGB-Supposition is X-OR Shape on mapping block or cube or curve & shape; Due to Alpha Alias smooth blending is achieved.

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Furthermore can also render Vector 3D & 2D Audio & other elements though Vector 'Fonting' Systems, Examples exist : 3D Wave Tables, Harmonic reproduction units for example Yamaha and Casio keyboards.

Personally QFT is a much more pleasurable experience than VRR at 2xFPS+
Stable FPS & X-OR Partial Frame Retention saving on compression.

"QFT a Zero compression or low level compression version of DSC
1.2bc

X-OR Frame Buffer Compression & Blank Space Compression:
Vector Compression VESA Standard Display protocol 3"

"QFT transports each frame at a higher rate to decrease “display
latency”, which is the amount of time between a frame being ready for
transport in the GPU and that frame being completely displayed. This
latency is the sum of the transport time through the source’s output
circuits, the transport time across the interface, the processing of
the video data in the display, and the painting of the screen with the
new data. This overall latency affects the responsiveness of games:
how long it appears between a button is pressed to the time at which
the resultant action is observed on the screen.

While there are a lot of variables in this equation, not many are
adjustable from an HDMI specification perspective. QFT operates on the
transport portion of this equation by reducing the time it takes to
send only the active video across the cable. This results in reduced
display latency and increased responsiveness."

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(c)Rupert S

Drawing tools & functions that are the basis of our draw frame & font functions : Polygon maths


Core Processor features : SVM, SiMD, FPU
Core tools : https://science.n-helix.com/2019/06/vulkan-stack.html

Reference material for Drawing Elliptoids, Curves & Polygons

SVM Elliptic Curve magic:
Fractal maths for improved efficiency & Combustion energy, Regard the photos & the FX8320E for details

Effective Application of SVM Processor Elliptic Maths
https://is.gd/SVMefficiency

Linear Bounding Volume Hierarchy &
Elliptic Bounding Volume Hierarchy for SVM Processor Feature:
SVM Can be emulated in SiMD pure 32Bit Single or 64Bit Double Precision,
& is for high complexity rendering such as non regular windows.

https://www.phoronix.com/scan.php?page=news_item&px=RADV-LBVH-Lands

SVM Can be emulated in SiMD pure 32Bit Single or 64Bit Double Precision..
Is useful for creating non Circle curves such as elliptoids & oblong wave boxes.

In VSR & VSR Variable Lighting we can define spaces with eliptoids SVM,
Therefore shape around trees & grasses & animals &or people & Whales.

https://www.youtube.com/watch?v=UojqzrPtR70

(c)RS

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FFT or QFFT : Fast Fourier Transform


FFT or QFFT is not only about audio; But also Video & 3D, Mouse & input/output devices (c)RS 2022

FFT or QFFT is not only about audio; But also Video & 3D,
In fact FFT Fast Fourier Transforms are about any device such as a mouse that directly interacts with Waves,

Such a device is the laser mouse & pointer; The primary reason is to use Noise reduction & path smoothing,
Primarily to create a 16Bit to 256Bit pure float with high compression or pack bit properties.

Creating Sine-oidial curves & waves or SiMD, Float & packed integer/Float operations saves on bandwidth & increases messaging speed therefore!

Both the input & output from Bluetooth, 2.4G & USB & Serial can in fact be reduced to mapped Curves & angles; While this introduces a small error factor & this is a factor that producers & driver developers need to work out & create error margins for.

Creation & development of Ultra high precision Input & output for Humans, Robots & precision pointers; Requires a precise production FFT & to account for the fact surrounding the interactive motion of point A to point B; & In fact point C...

Development continues & today's mission is to open minds about why we use FFT & noise reduction & Curve maps such as elliptic SVM & Bit Averaging Fast transforms for Center point Algebra & Math Tables & Graphs.

Further study includes Raytracing & All Haptic motion; Sensors & Car engine Mechanics.

(c)Rupert S

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Include vector today *important* RS https://vesa.org/vesa-display-compression-codecs/

https://science.n-helix.com/2016/04/3d-desktop-virtualization.html

https://science.n-helix.com/2019/06/vulkan-stack.html

https://science.n-helix.com/2019/06/kernel.html

https://science.n-helix.com/2022/03/fsr-focal-length.html

https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html

https://bit.ly/VESA_BT

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Core Concepts of Direct Vector Render Frame Buffers & Cache


LHP_DSC_Xor : Screen Fast Buffer Access


VESA Standard Ethernet Standard Frame Protocol for QFT, VRR & Low Latency High Performance Dynamic Compression XOR Frame Refresh : LLHP_DSCX : LHP_DSC_Xor

QFT & VRR basically allow the TV to float a resolution refresh free from Frame Cache Memory Refresh (Refueling the Cache Buffer) ,
Basically the frame can be fetched from the Frame Cache (4MB to 64MB) Without interacting with the CPU

This means a Fast Direct DMA Cache pull on frame to Screen & does not demand that the CPU need to perform this fast; Additionally the Frame comes without tearing or Frame pulls from the HDMI or display port VESA Ethernet Standard Frame Protocol.

Rupert S

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Predicted Content Compression Frame Negotiation (c)RS


Compression for HDMI & DP : VRR & QFT with frame content prediction & Minimal Adjust; X-OR Content replacement

Compression Implicitly supported : STC, DXT, EAC & ATSC & DSC , Most of these compression forms are available in ARM, AMD, NVidia & Intel Hardware & therefore directly supported by us in creating the best frames & video; HDR WCG RGBA/X 4 Channel.

Compression required for a display; Common details include using Compression as a last desperate measure to improve bandwidth for displays on High Definitions such as 4K on HDMI 2!

My personal strategy is to implement compression that is transparent; Starting right at almost non,

Frequently the problem with VRR & QFT is that a frame is sent or not sent...

By utilizing Prediction in compression we force the prediction of an exact copy of present data,
We adjust the frame with X-OR & modify only a few details; Therefore we do not need to send a lot of data & can send more frames!

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Vector Compression VESA Standard Display protocol 3 +

DSC : Zero compression or low level compression version of DSC
1.2bc

Frame by Frame compression with vector prediction.

Personally, QFT is a much more pleasurable experience than VRR at 2xFPS+
Stable FPS & X-OR Partial Frame Retention saving on compression.

X-OR Frame Buffer Compression & Blank Space Compression:

X-OR X=1 New Data & X=0 being not sent,
Therefore Masking the frame buffer,

A Frame buffer needs a cleared aria; A curve or ellipsoid for example,
Draw the ellipsoid; This is the mask & can be in 3 levels:

X-OR : Draw or not Draw Aria : Blitter XOR
AND : Draw 1 Value & The other : Blitter Additive
Variable Value Resistor : Draw 1 Value +- The other : Blitter + or - Modifier

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PCCFN


The idea Behind PCCFN is to modify the frame by a smaller amount with low bandwidth & thereby increase frame rate by the following method:

DSC Compression is used & Predict is enabled..
Predict is used to redisplay the frame on the screen; With no data needing to be sent : X-OR..
However Modifications are made to the frame by overruling parts of the Static frame with data..

The effect is that only parts of the frame (Vector Motion Prediction); Are sent,

Both bandwidth & speed are preserved & the same effect works from BFrames & Partial Full Frames.

https://hdmi.org/spec21sub/variablerefreshrate
https://hdmi.org/spec21sub/quickframetransport

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ITS_DHDR_VRR : Gaming & Desktop : HDR, Source-Based Tone Mapping (SBTM)

High Efficiency DSC Screen Dynamic Shift State Screen blanking Replacement
Low Bandwidth Requirement for 40Hz to 240Hz+

HDR, HDMI & Display-port Standards VESA 2022 : Independent Thread
Asymmetric Compute Frame Buffer Tree for HDR, Display & Compression
DSC : RS (c)Rupert S

Composer Frame DSC is where we Compose a frame in the renderer, That
frame is for example the window task bar & another box for the
Explorer frame; The example is not OS Exclusive; Is an example.

We implement DSC Display compression in the frame (smaller than the
display resolution or super sampled),

Every piece of content in the Main Render Frame to HDMI & Display port
is computed independently with static content not being adjusted or
recompressed until needed,

Our goal is to place Every frame or window in a Sub-Buffer Cache & Render to the main Frame Cache/Buffer,

On completion of the frame at whatever FPS Refresh we desire for the Main Frame Buffer,
Effectively we Blitter &or Byte-swap our Window Frame Buffer to a location within the Main Frame buffer,

The location of our window & our localised processing mean that content of each window & therefore process is independently proven to be the Same as the frame before (We X-OR),

Therefore we Frame Predict (DSC) That a small portion of the main frame buffer has the same data,
We do not need to change a thing & so we do not need to utilize the processor to render it..

However if data has changed; Then the change is localised to a single small render space in the main frame buffer & we therefore can refresh the screen faster & Frame Prediction (Like JPG & MPEG)

Proves that we only need to inform the Screen (HDMI & DP Signal in our case);
That no additional date is sent; However any changes to the main frame buffer such as main view or video or text files or HTML Refresh will be Sent & Rendered,
Without Latency issues or large amounts of data being sent though the Cable..

But we still render faster than recompressing a main frame buffer completely & in addition change what we wish per thread without the resulting processing Hanging or waiting on Data To arrive from a baton-pass.

Our reasoning is that each frame is independent; Therefore we compose
in GPU or CPU & independently Compress the Frame within adjusted
context of the HDMI & DisplayPort,

3 Frame Buffer; We can optimise the whole frame with Prediction
Compression if we wish,

The Main goal : Independent Thread Render for Sub-Framing High Dynamic
Range with Independent Application Variable Refresh Rate :
ITS_DHDR_VRR.

The main advantages are : Task bar is Low CPU Resource use but high
refresh rate; low data modification rate over a tiny area of the task
bar,

The Game Window & the Frame (Mostly Square) are drawn with sub-pixel
precision on location..
But the frame that barely changes does not need recompression in DSC..

The Game window does not need to compute or adjust content Compression
for the frame...

Every piece of content in the Main Render Frame to HDMI & Display port
is computed independently with static content not being adjusted or
recompressed until needed.

This works with the HDR, HDMI & Display-port Standards VESA

(c)Rupert S


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*Application of SiMD Polygon Font Method Render

*3D Render method with Console input DEMO : RS

3D Display access to correct display of fonts at angles in games & apps without Utilizing 3rd Axis maths on a simple Shape polygon Vector font or shape. (c)Rupert S

3rd dimensional access with vector fonts by a simple method:

Render text to virtual screen layer AKA a fully rendered monochrome, 2 colour or multi colour..

Bitmap/Texture,

Due to latency we have 3 frames ahead to render to bitmap DPT 3 / Dot 5

Can be higher resolution & we can sub sample with closer view priority...

We then rotate the texture on our output polygon & factor size differential.

The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize

Why ? Because rotating a polygon is harder than subtracting or adding width, Hight & direction to fully complex polygon Fonts & Polygon lines or curves...

The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize.

Such an example is my SiMD & MMX > AVX Image resizer,
Mipmapping fonts does tend to require over sized fonts..
For example Size 8 & 9 font output = Size 10 to 14 Font,

TT-SVG & Open Fonts OT-SVG & Bitmap fonts compress well;
Mipmapped from 3 sizes larger & Cached as a DOT3/5 or NV12...
You have to save a cache; The Cache can be:

Emulated or Dynamic Spacing (for difficult SETSPACE Console Font situations)
2 Tone, Grey, RGB, RGBA_8888, RGBA_1010102, RGBA_F16, P010, 444A, 888A or 101010A &
(DSC Precached Predicted Block Compression)tm

The representation with alpha is mainly for smoothing & clean lines & is very quick to draw.

Therefore we can Cache a Bitmap Version of any font,
We can of course Vector Render A font & directly to compressed surface rendering.

The full process leads up to the terminal & how to optimize CON,
We can & will need to exceed capacities of any system & To improve them!

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DSC Precached Predicted Block Compression


We have a font for example with Alpha stored in the screen buffer & of a set size for BLITTING on top of a colour or image background,

The alpha prevents the transposed X-OR Image or Font from having noise & creates ..a smooth sharp in-place modification of content.

For our purpose X-OR can use Alpha instead of a single colour because this allows a very delicate smooth presentation on top of the background..

Repeated application (& Probably Saving of, To save Resource usage); Can overlay graphic of Font Content.

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VecSR is really good for secondary loading of sprites & text; In these terms very good for pre loading on for example the X86, RISC, AMIGA & Famicom type devices,With appropriate loading into Sprite buffers or Emulated Secondaries (Special Animations) or Font Buffers.

Font Drawing & Vector Render

Although Large TT-SVG & OT-SVG fonts load well in 8MB Ram on the Amiga with Integer & Emulated Float (Library); Traditional Bitmap fonts work well in a Set Size & can resize well if cached & Interpolated &or Bilinear Anti-Alias & sharpened a tiny bit!

presenting: Dev-Con-VectorE²
Fast/dev/CON 3DText & Audio Almost any CPU & GPU ''SiMD & Float/int"
Class VESA Console +

With Console in VecSR you can 3DText & Audio,

VecSR Firmware update 2022 For immediate implementation in all
operating systems & ROM's

Potential is fast & useful.

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I will put this in print, My 3D & 2D Vector SiMD standard is the thing that i believe will save the most bandwidth on HDMI & DisplayPort Cables & Enable Vector 3D such as Laser Printers & Laser Screens, At the end of the day WE NEED VECTORS : RS
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https://science.n-helix.com/2022/04/vecsr.html

https://is.gd/Dot5CodecGPU

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Camera & HDMI & DP Compression Modes


Camera Modes
4:2:1 , 4:2:2 for the 4K Camera : HDR
4:4:4 for the faster 4K Camera : HDR
4:2:1 , 4:2:2 for the faster 8K Camera : HDR

TV Modes

HDMI 1.4 | 4:2:1 , 4:2:2 , 8bit, 10Bit for HD to HD+
HDMI 2 | 4:2:2 , 10Bit, 12Bit HDR 4K
HDMI 2.1 | 4:2:2, 10Bit, 12Bit, 16Bit 4K to 6K/8K..

Example : 5120x2880x 60000Khz-GPixClock-DataRate GRefreshRate-38.365Hz-DBLScan 4:2:2 12Bit

If we had DSC compression modes installed in firmware ...

BEST MODE : Can we upgrade this dynamically to HDMI 2.1 Standards with firmware & DSC Installed

Question is can we implement BEST MODE for our Quality range & Also utilize DSC & Alternative Texture Mode Compression & Dynamic MAX Speed

Yes We Can RS : DSC, ETC, ASTC & DTX Compression for display frames

Yes for Studio recording 4:2:2 mode offers 2x the resolution & 4 extra Bit for the same money as 4:4:4 : 4:2:2 10Bit, 12Bit, 14Bit, 16Bit : Higher Dynamic Contrast & Colour

Examples
https://youtu.be/VCdrB1b7wfc

https://youtu.be/NIsoSA8uO04
https://youtu.be/Suc0OV_9TiA

Render Folder https://bit.ly/VESA_BT

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ASTC, EAC, DXT, PVRTC & DSC with firmware updated & need to be
included in the standards & firmware.

YCoCg-R


https://en.wikipedia.org/wiki/YCoCg

The screen content coding extensions of the HEVC standard and the VVC standard include an adaptive color transform within the residual coding process that corresponds with switching the coding of RGB video into the YCoCg-R domain.

The use of YCoCg color space to encode RGB video in HEVC screen content coding found large coding gains for lossy video, but minimal gains when using YCoCg-R to losslessly encode video

Yes for Studio recording 4:2:2 mode offers 2x the resolution & 4 extra Bit for the same money as 4:4:4 : 4:2:2 10Bit, 12Bit, 14Bit, 16Bit : Higher Dynamic Contrast & Colour

HDMI 1.4 | 4:2:1 , 4:2:2 , 8bit, 10Bit for HD to HD+
HDMI 2 | 4:2:2 , 10Bit, 12Bit HDR 4K
HDMI 2.1 | 4:2:2, 10Bit, 12Bit, 16Bit 4K to 6K/8K..

Example : 5120x2880x 60000Khz-GPixClock-DataRate
GRefreshRate-38.365Hz-DBLScan 4:2:2 12Bit

https://www.cablematters.com/blog/DisplayPort/hdmi-2-1-vs-displayport-2-0

https://www.cablematters.com/blog/DisplayPort/what-is-display-stream-compression

https://en.wikipedia.org/wiki/YCoCg

https://is.gd/Dot5CodecGPU

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Things Task Shaders can (c)RS


https://www.phoronix.com/scan.php?page=news_item&px=AMD-RDNA3-More-5.19-Tasks-RADV

Task Shaders can be launched to implement Elliptic & Polygon MESH & thus create:

Things Task Shaders can implement though MESH Shading & Polygons:

(Direct Load of a preform MESH)

Multi-Threaded+
Tundra & fauna
Polygon Fonts
Video Rendering Polygon interpretative interpolation..
Polygon MESH Conceptualised Vector Audio.
X-OR DSC Blank space removal
Polygon math & viewer & Viewer Angle based dynamic MESH Subtraction & Addition..
Close loop Tessellation

OpenCL Group micro tasks
Direct Compute/DirectedCL Group micro tasks
Multi-Threading
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"Task shader is an optional stage that can run before a Mesh shader in a graphics pipeline. It's a compute-like stage whose primary output is the number of launched mesh shader workgroups (1 task shader workgroup can launch up to 2^22 mesh shader workgroups), and also has an optional payload output which is up to 16K bytes."

Friday, March 25, 2022

ICE-SSRTP GEA Replacement 2022 + (c)RS

ICE-SSRTP GEA Replacement 2022 + (c)RS


"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension
of GEA-1 with a higher amount of processing, and apparently not
weakened) are bit-oriented stream ciphers."

GEA-2 > GEA-3 is therefor 64Bit Safe (Mobile calls) & 128Bit Safe (Reasonable security)
SHA2, SHA3therefor 128Bit Safe (Reasonable security Mobile) ++
AES & PolyChaCha both provide a premise of 128Bit++

So by reason alone GEA has a place in our hearts.

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ICE-SSRTP GEA Replacement 2022 + (c)RS


IiCE-SSR for digital channel infrastructure can help heal GPRS+ 3G+ 4G+ 5G+

Time NTP Protocols : is usable in 2G+ <> 5G+LTE Network SIM

ICE-SSRTP Encryption AES,Blake2, Poly ChaCha, SM4, SHA2, SHA3, GEA-1 and GEA-2 
'Ideal for USB Dongle & Radio' in Rust RS ' Ideal for Quality TPM Implementation'

"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension
of GEA-1 with a higher amount of processing, and apparently not
weakened) are bit-oriented stream ciphers."

IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol

Interleaved signals help Isolate noise from a Signal Send & Receive ...

Overlapping inverted waves are a profile for complex audio & FFT is the result.

Interleaved, Inverted & Compressed & a simple encryption?

Time differentiated : Interleave, Inversion & differentiating Elliptic curve.


We will be able to know and test the Cypher : PRINCIPLE OF INTENT TO TRUST

We know of a cypher but : (Principle RS)

We blend the cypher..
Interleaved pages of a cypher obfuscate : PAL CScam does this

Timed : Theoretically unique to you in principle for imprecision, But we cannot really have imprecise in Crypto!

But we can have a set time & in effect Elliptic curve a transient variable T,
With this, Interleave the resulting pages (RAM Buffer Concept)

Invert them over Time Var = T

We can do all & principally this is relatively simple.

(c)RS

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Modulus Dual Encrypt & Decrypt package : Processor feature (c)RS


AES-CCM & AES-GCM & Other Cypher Modulus + CCM & GCM can be accelerated with a joint AES Crypto module,

Processor feature & package : Module list:

2 Decryption pipelines working in parallel,
With a Shared cache & RAM Module
Modulus & Semi-parallel modulating decryption & Encryption combined with Encapsulation Cypher IP Protocol packet

Parallax Cryptographic Processing Unit: RS


The capacity To Multiply decryption on specific hardware in situations such as lower Bit precision is to be implemented as follows:

On AES-NI & ARM Cryptographic processors; In particular PSP+PPS(ARM+) & SiMD ..

The capacity to exploit the fact that the nonce is 16Bit to 64Bit & full float upto 128Bit for legal decryption (client) means there is a simple method to use:

In situations that a AES-NI & ARM Cryptographic unit can process 2 threads on a 256Bit Function we can do both the main 128Bit/192Bit & the nonce 16Bit to 64Bit & Enable a single instruction Roll to Synchronise both The main HASH & Nonce.

AES & Crypto hardware can utilise the CPU/GPU/Processor FPU & SiMD to decrypt the nonce (smaller so fast) & in the same 8bto to 64Bits of code; Inline & parallax the cryptographic function.

With a 256Bit AES-NI & Cryptographic unit : Parallel Decryption & Return Encryption by using 2x 128Bit & a Processor Enciphered Nonce.

Security Relevant Extensions

SVM : Elliptic Curves & Polynomial graphs & function
AES : Advanced Encryption Standard Functions
AVX : 32Bit to 256Bit parallel Vector Mathematics
FPU : IEEE Float Maths
F16b : 16Bit to 32Bit Standards Floats
RDTSCP : Very high precision time & stamp

Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1

32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)
(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second

AES & Elliptic Hardware Acceleration : AES & SVM along with AVX Micro-block decoding.


ECC Elliptic Curve encrypt is 20% to 40% more efficient than Large Size RSA AES on game packets @ QUICC
512/384/256 AES Elliptic is clearly advantageous because of compression block size on small network packets,

Larger streams such as video clearly favour 2048 Bit RSA AES; With SVM Elliptic feature,

RSA,512, 384 AES Elliptic curve is a clear winner!

(c)Rupert S

*reference*

https://science.n-helix.com/2022/03/ice-ssrtp.html

Performance Comparison of AES-CCM and AES-GCM Authenticated Encryption Modes
http://worldcomp-proceedings.com/proc/p2016/SAM9746.pdf

Basic comparison of Modes for Authenticated-Encryption -IAPM, XCBC, OCB, CCM, EAX, CWC, GCM, PCFB, CS
https://www.fi.muni.cz/~xsvenda/docs/AE_comparison_ipics04.pdf

*

Example Encryption Results:


gnutls-cli --benchmark-tls-ciphers

Testing throughput in cipher/MAC combinations (payload: 1400 bytes)

AES-128-GCM - TLS1.2 0.56 GB/sec
AES-128-GCM - TLS1.3 0.57 GB/sec
AES-128-CCM - TLS1.2 185.36 MB/sec
AES-128-CCM - TLS1.3 182.74 MB/sec
CHACHA20-POLY1305 - TLS1.2 112.79 MB/sec
CHACHA20-POLY1305 - TLS1.3 111.61 MB/sec
AES-128-CBC - TLS1.0 168.16 MB/sec
CAMELLIA-128-CBC - TLS1.0 53.82 MB/sec
GOST28147-TC26Z-CNT - TLS1.2 15.39 MB/sec

As can be seen:

AES-GCM is
1056x better than Camellia &
508x Better than ChaChaPoly
309x Better than AES-CCM

So what about ChaChaGCM?

RS

*

Example of use:

Nostalgic TriBand : Independence RADIO : Send : Receive :Rebel-you trade marker

Nostalgic TriBand 5hz banding 2 to 5 bands, Close proximity..
Interleaved channel BAND.

Microchip clock and 50Mhz Risc Rio processor : 8Bit : 16Bit : 18Bit
Coprocessor digital channel selector &

channel Key selection based on unique..

Crystal time Quartz with Synced Tick (Regulated & modular)

All digital interface and resistor ring channel & sync selector with
micro band tuning firmware.

(c)Rupert S

*

Good for cables ? and noise ?

Presenting :  IiCE-SSR for digital channel infrastructure & cables
<Yes Even The Internet &+ Ethernet 5 Band>

So the question of interleaved Bands & or signal inversion is a simple
question but we have,

SSD & HDD Cables & does signal inversion help us? Do interleaving bands help us?

In Audio inversion would be a strange way to hear! but the inversion
does help alleviate ...

Transistor emission fatigue...

IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol

Interleaved signals help Isolate noise from a Signal Send & Receive ...

Overlapping inverted waves are a profile for complex audio & FFT is the result.

Interleaved, Inverted & Compressed & a simple encryption?

Good for cables ? and noise ?

Presenting : IiCE for digital channel infrastructure & cables <Yes
Even The Internet &+ Ethernet 5 Band>

(c) Rupert S

*
Given the ZFS Results the strategy to utilize (c)RS

Crypto Storage & RAM Strategy (c)RS


GCM : Accelerated by SVM Elliptic Curve & AES & ARM Crypto-Extensions,
Processor Compression Accelerated,

2 to 64 Blocks,
Header Separated; GZIP, BZip & LZ8 & LZH & Wavelet & Hardware Compression with independent Encrypted Segmentation & Sub-Grouping.

Hash main block group listing & Tables for drive repair and DIR & Access Acceleration.

https://www.medo64.com/content/media/ubuntu-2204-zfs-speed.png
AES-128-GCM - TLS1.2 0.56 GB/sec
AES-128-GCM - TLS1.3 0.57 GB/sec

*

https://science.n-helix.com/2018/12/rng.html

https://science.n-helix.com/2022/02/rdseed.html

https://science.n-helix.com/2017/04/rng-and-random-web.html

https://science.n-helix.com/2022/02/interrupt-entropy.html

https://science.n-helix.com/2021/11/monticarlo-workload-selector.html

https://science.n-helix.com/2022/03/security-aspect-leaf-hash-identifiers.html

Basic comparison of Modes for Authenticated-Encryption -IAPM, XCBC, OCB, CCM, EAX, CWC, GCM, PCFB, CS


Integral to Telecoms Security TRNG

*RAND OP Ubuntu : https://manpages.ubuntu.com/manpages/trusty/man1/pollinate.1.html

https://pollinate.n-helix.com

*

Audio, Visual & Bluetooth & Headset & mobile developments only go so far:


https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html

https://science.n-helix.com/2021/11/ihmtes.html

https://science.n-helix.com/2022/03/ice-ssrtp.html

https://science.n-helix.com/2021/10/eccd-vr-3datmos-enhanced-codec.html
https://science.n-helix.com/2021/11/wave-focus-anc.html
https://science.n-helix.com/2021/12/3d-audio-plugin.html

*

***** Dukes Of THRUST ******


Nostalgic TriBand : Independence RADIO : Send : Receive :Rebel-you trade markerz

Nostalgic TriBand 5hz banding 2 to 5 bands, Close proximity..
Interleaved channel BAND.

Microchip clock and 50Mhz Risc Rio processor : 8Bit : 16Bit : 18Bit
Coprocessor digital channel selector &

channel Key selection based on unique..

Crystal time Quartz with Synced Tick (Regulated & modular)

All digital interface and resistor ring channel & sync selector with
micro band tuning firmware.

(c)Rupert S

Dev/Random : Importance

Dev/Random : Importance : Our C/T/RNG Can Help GEA-2 Open Software implementation of 3 Bits (T/RNG) Not 1 : We need Chaos : GEA-1 and GEA-2 Implementations we will improve with our /Dev/Random

Our C/T/RNG Can Help GEA-2 Open Software implementation of 3 Bits
(T/RNG) Not 1 : We need Chaos : GEA-1 and GEA-2 Implementations we
will improve with our /Dev/Random

We can improve GPRS 2G to 5G networks still need to save power, GPRS
Doubles a phones capacity to run all day,

Code can and will be improved, Proposals include:

Blake2
ChaCha
SM4
SHA2
SHA3

Elliptic Encipher
AES
Poly ChaCha

Firstly we need a good solid & stable /dev/random

So we can examine the issue with a true SEED!

Rupert S https://science.n-helix.com/2022/02/interrupt-entropy.html

TRNG Samples & Method DRAND Proud!

https://drive.google.com/file/d/1b_Sl1oI7qTlc6__ihLt-N601nyLsY7QU/view?usp=drive_web
https://drive.google.com/file/d/1yi4ERt0xdPc9ooh9vWrPY1LV_eXV-1Wc/view?usp=drive_web
https://drive.google.com/file/d/11dKUNl0ngouSIJzOD92lO546tfGwC0tu/view?usp=drive_web
https://drive.google.com/file/d/10a0E4Gh5S-itzBVh0fOaxS7JS9ru-68T/view?usp=drive_web

https://github.com/P1sec/gea-implementation

"GEA-1 and GEA-2, which are very similar (GEA-2 is just an extension
of GEA-1 with a higher amount of processing, and apparently not
weakened) are bit-oriented stream ciphers."

"A stream cipher, such as the well-known RC4 or GEA-1, usually works
through using the Xor operation against a plaintext. The Xor operation
being symmetrical, this means that encrypting should be considered the
same operation as decrypting: GEA-1 and GEA-2 are basically
pseudo-random data generators, taking a seed (the key, IV and
direction bit of the GPRS data, which are concatenated),

The generated random data (the keystream) is xored with the clear-text
data (the plaintext) for encrypting. Then, later, the keystream is
xored with the encrypted data (the ciphertext) for decrypting. That is
why the functions called in the target library for decrypting and
encrypting are the same.

GEA-1 and GEA-2 are bit-oriented, unlike RC4 which is byte-oriented,
because their algorithms generate only one bit of pseudo-random data
at once (derived from their internal state), while algorithms like RC4
generate no less than one byte at once (in RC4's case, derived from

permutation done in its internal state). Even though the keystream
bits are put together by the current encryption / decryption C and
Rust libraries into bytes in order to generate usable keystream,
obviously.

Based on this, you can understand that GEA-1 and GEA-2 are LFSR:
Linear Feedback Shift Register-oriented ciphers, because their
internal state is stored into fixed-size registers. This includes the
S and W registers which serve for initialization / key scheduling
purposes and are respectively 64 and 97-bit wide registers, and the A,
B, C (and for GEA-2 only D) registers which serve for the purpose of
keystream generation, which are respectively 31, 32, 33 and 29-bit
wide registers.

On each iteration of the keystream generation, each register is
bit-wise rotated by one position, while the bit being rotated from the
left towards the right side (or conversely depending on in which bit
order you internally represent your registers) is fed back to the
algorithm and mutated depending on given conditions. Hence, the

shifted-out bit is derived from other processing, and reinserted,
while being for this reason possibly flipped depending on conditions
depending on bits present at the other side of the given register.

This is the explanation for the name of linear feedback shift register
(shift because of the shift operation required for the rotation, and
linear feedback because of the constant-time transform operation
involved).

The rest of the register may also be mutated at each iteration steps,
as in the case of the GEA-1 and 2, whole fixed Xor sequences (which
differ for each register) may be applied depending on whether the
rotated bit is a 0 or a 1.

Note that a step where the register iterates is called clocking (the
register is clocked), and that the fixed points where the register may
be Xor'ed when the rotated bit becomes a 1 are called taps. The linear
function which may transmute the rotated bit at the clocking step
(taking several bits of the original register as an input) is called
the F function.

Those kind of bit-oriented LFSR algorithms, such as GEA-1 and 2 (for
GPRS) and A5/1 and 2 (for GSM), were designed this way for optimal
hardware implementations in the late 80's and early 90's."

*****

IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol

Interleaved signals help Isolate noise from a Signal Send & Receive ...

Overlapping inverted waves are a profile for complex audio & FFT is the result.

Interleaved, Inverted & Compressed & a simple encryption?

Good for cables ? and noise ?

Presenting :  IiCE-SSR for digital channel infrastructure & cables
<Yes Even The Internet &+ Ethernet 5 Band>

So the question of interleaved Bands & or signal inversion is a simple
question but we have,

SSD & HDD Cables & does signal inversion help us? Do interleaving bands help us?

In Audio inversion would be a strange way to hear! but the inversion
does help alleviate ...

Transistor emission fatigue...

IiCE-SSRTP : Interleaved Inverted Signal Send & Receive Time Crystal Protocol

Interleaved signals help Isolate noise from a Signal Send & Receive ...

Overlapping inverted waves are a profile for complex audio & FFT is the result.

Interleaved, Inverted & Compressed & a simple encryption?

Good for cables ? and noise ?

Presenting : IiCE for digital channel infrastructure & cables <Yes
Even The Internet &+ Ethernet 5 Band>

(c) Rupert S


Tuesday, March 22, 2022

Security Aspect Leaf HASH Identifiers

VM Virtual Call Frame : Security Aspect Leaf HASH Identifiers : Rupert S

Leaf HASH Identifiers in 16Bit/32Bit/64Bit : RS

With this example in mind 16Bit HASH Values & identifiers make sense.

16Bit HASH Reasoning Table: based upon Leaf HASH Identifiers in 16Bit/32Bit/64Bit

16Bit Leaf HASH, Compatible max RAM) : 4GB Large Page

16 Million HASH groups for identifiers with 128MB RAM per HASH Master group..

256 HASH master Table
256 HASH Per Group

16:32MB up to 4GB(16Bit Leaf HASH, Compatible max RAM) : RAM per group

16Bit Hash identifier tables load into 16KB of processor cache
Load, Save & Store can be done in a higher Bit depth; 32Bit for example
SiMD can operate in Half, Single & Double Float capacity

Micro work loads such as motion & video & 3D Tessellation

*

VM Virtual Call Frame : Security Aspect Leaf HASH Identifiers in 16Bit/32Bit/64Bit : RS

If the CPU Manager can call Compression & Cypher independently on TASK Call,
If the Processor Manager can call from Virtualisation functions for each secure task group.

Security Aspect : With CPU Cache in the 8MB+ Region Leaf HASH Identifiers can be stored:

Compressed if Processor has Compression such as BZip
Encrypted Compressed if Processor has Compression such as AES

In a Secure &+ Work Isolation Container : WIC or SWIC contained L2 (Compress Store Small Identifier List)

In a Secure &+ Work Isolation Container : WIC or SWIC contained L3 (larger identifier lists),

(c)Rupert S

Reference Kernel Security:

https://science.n-helix.com/2021/11/monticarlo-workload-selector.html

https://science.n-helix.com/2022/02/interrupt-entropy.html

https://science.n-helix.com/2018/12/rng.html

https://science.n-helix.com/2022/02/rdseed.html

https://science.n-helix.com/2017/04/rng-and-random-web.html

Leaf HASH Identifier Paths to clear logic:

Performance issues related to handheld would be solved with the use of:

FP16 packed pixel
FP16 background object maths
FP/Int8/4 Machine learning adaptive code...
Compute Shaders
Compression > DOT Image format

With these resources available, We can potentially do more!

https://science.n-helix.com/2019/06/vulkan-stack.html
https://science.n-helix.com/2022/03/fsr-focal-length.html
https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html
https://science.n-helix.com/2022/03/simd-render.html

*
https://science.n-helix.com/2019/06/kernel.html

Trace ID : Kernel & Bios HASH Reference
https://lkml.org/lkml/2022/3/22/446

Jumpless Security HASH
https://lkml.org/lkml/2022/3/22/440

SPE Decode & Encode
https://lkml.org/lkml/2022/3/22/415

IDR Transaction ID's VMBus : HASH
https://lkml.org/lkml/2022/3/22/459
*

As you know in my studies i found that 16x AA rarely has a performance hit on all verified hardware since RX200 3GB (and the RX560) & even the RX5770 1GB.The NVidia 1080 can manage most of this & i optimised Elite Dangerous for the 1080 & RX200 market.


A lot of the performance issues related to handheld would be solved with the use of:

FP16 packed pixel
FP16 background object maths
FP/Int8/4 Machine learning adaptive code...
Compute Shaders
Compression > DOT Image format

With these resources available, We can potentially do more!

*

"Apex Legends : I get the feeling that the lower final precision on the screen output is the result of a 4x Anti Aliasing layer and lower Image compression settings,"

*

Elite Dangerous Reference Videos:https://www.youtube.com/watch?v=JmMQPS_azJA&list=PL8DNvgnwiUU1cezx_Y9DraHjyqJxnrrN7

ML & Game performance improvement https://is.gd/ProcessorLasso

Rupert S

The Handheld market performance ratings are :

Snapdragon (often used & is good)

High quality option based upon Notebook expectations

AMD Chipset
NVidia

My studies concluded that both NVidia and AMD have little to worry about AA performance upto 16x and it makes almost no performance advantage to use less in my performance tuning...

I am frequently in possession of older hardware; Like many users i cannot always afford all the best gear,

However there are examples of things that make a bigger hit:

16x tessellation rarely causes a problem (RX200 3GB+)24 & 32 both dynamically jiggle FPS around heavy asteroids & space stations in frontier elite..

but looks amazing!

Multisampling is manageable at 2x on RX200 on elite dangerous

(a quite intense graphic space MMO)
4x MultiSampling does involve a 20% frame rate drop, Quality is preferred but i went for 2x as it rarely causes issues.

Texture Image compression format optimisation is a priority NO.1 Priority..

You save a lot of space & heavy usage of DOT 1 > 5 compression management is advised..
10Bit sampling is perfectly logical.

https://www.nintendolife.com/news/2021/03/video_check_out_this_side-by-side_comparison_of_apex_legends_running_on_switch_and_ps4_pro

https://www.youtube.com/watch?v=uGrPwt_KHRE

Elite Dangerous 64Bit PvP Arena DeathMatch 4Q 2xMultiSampling.mp4 (93.26 MB) https://mirrorace.org/m/6qr3y

Elite Dangerous 64 Sub.FM Rastafari PvP 2016-04-23 19-27-22-552.mp4 (89.27 MB) https://mirrorace.org/m/54waA

EliteDangerous - CQC PvP Arena - Bloody is the bath of kings - 2016-05-05 14-30-27-909.mp4 (277.04 MB) https://mirrorace.org/m/3IO7p

yes cloudflare apex_eoso.nx7v.icu apex_eu.nx7v.icu apex_wes.nx7v.icu apex_eas.nx7v.icu

USA: pop: apex_sv1.nx7v.icu apex_sv2.nx7v.icu apex_sv3.nx7v.icu

*

Thursday, March 10, 2022

SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts

VESA Standards : Vector Graphics, Boxes, Ellipses, Curves & Fonts : Consolas & other brilliant fonts : (c)RS

SiMD Render - Vector Graphics, Boxes, Ellipses, Curves & Fonts

Improve Console & TV & BIOS & General Animated Render

Vector Display Standards with low relative CPU Weight
SiMD Polygon Font Method Render

Default option point scaling (the space) : Metadata Vector Fonts with Curl mathematical vector :

16 Bit : SiMD 1 width
32 Bit : SiMD Double Width

High precision for AVX 32Bit to 256Bit width precision.

Vectoring with SiMD allows traditional CPU mastered VESA Emulation desktops & safe mode to be super fast & displays to conform to VESA render standards with little effort & a 1MB Table ROM.

https://science.n-helix.com/2022/04/vecsr.html



https://science.n-helix.com/2022/03/fsr-focal-length.html

https://science.n-helix.com/2018/01/integer-floats-with-remainder-theory.html

*

*Application of SiMD Polygon Font Method Render

*3D Render method with Console input DEMO : RS

3D Display access to correct display of fonts at angles in games & apps without Utilizing 3rd Axis maths on a simple Shape polygon Vector font or shape. (c)Rupert S

3rd dimensional access with vector fonts by a simple method:

Render text to virtual screen layer AKA a fully rendered monochrome, 2 colour or multi colour..

Bitmap/Texture,

Due to latency we have 3 frames ahead to render to bitmap DPT 3 / Dot 5

Can be higher resolution & we can sub sample with closer view priority...

We then rotate the texture on our output polygon & factor size differential.

The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize

Why ? Because rotating a polygon is harder than subtracting or adding width, Hight & direction to fully complex polygon Fonts & Polygon lines or curves...

The maths is simple enough to implement in games on an SSE configured Celeron D (depending on resolution and Bilinear filter & resize.

Saturday, March 5, 2022

FSR-Focal Length

Fast FSR-Focal Length Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS

FSR Focal Length Box Image Scaling Sharpening & blurring &or expansion with mathematical sharpening interpolation (c)Rupert S

*

Some photos of L2, Close to L2 may be an impossible focus; Unless image enhancement is used
(Sharpening & light angle mathematical focal length shift
(Computational Focal Length Sharpening Enhanced by Ray-Tracing)

*

We need to utilize diffraction & ray dispersion mathematics from physics,
For example for opaque surfaces & water ripples; Or by our personal preference lenses

For digital image focusing, Sharpening, Clarity & Depth Of Field DOF,
& When processing photos, video & art.

For this we present: Fast FSR-Focal Length;
With the intention of Sharply defined focus & processing.

*

Fast FSR-Focal Length Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS

& FSR Focal Length Box Image Scaling Sharpening & blurring &or expansion with mathematical sharpening interpolation (c)Rupert S

3d Graphics, Frame Render & Texture Image enhancement:

(Sharpening & light angle mathematical focal length shift
(Computational Focal Length Sharpening Enhanced by Ray-Tracing)

Focal length works by expanding an image by the refraction index,
In Figure 1 a simple example is offered:

fig 1 (I)=Light Ray Path (===)=lens


(object or image)
I I
I I
       I  =============== I
\ /
      =======================
==I===I===I===I==I==
       =====================
/ I / I \ /  I \ I \


https://bit.ly/VESA_BT


https://science.n-helix.com/2022/03/fsr-focal-length.html
https://science.n-helix.com/2021/09/temporal-aliasing-image-shaping-polygon.html
https://science.n-helix.com/2022/03/simd-render.html
https://science.n-helix.com/2019/06/vulkan-stack.html

https://github.com/GPUOpen-Effects/FidelityFX-FSR2/releases/tag/v2.0.1a
https://github.com/GPUOpen-Effects/FidelityFX-FSR/releases/tag/v1.0.2

Ray-Tracing Code: Refraction & index Sharpening, Blurring & Image resizing:RS

We utilize refraction, Expansion & Compression math code to work out the Image formed on the other side..

With Refraction & Reflection Simplex Raytracing models (15 to 400 Rays normally)..

We are able to sharpen or blur a scene by depth or by focus or by density or optical capacities of materials & matter or curvature for water surfaces..

To simplify matters for computational performance we work out the multiplication or division factors involved in compressing or expanding the image or audio compared to the perspective of the perceiver, Viewer or camera, Ear or Eye or infact sensation.

FSR & FSR-FL (Camera lens & CMOS Sharpening & Focus adjustment)

Methods To clarify (Hardware)

OpenCL (Microsoft CL pack is available to DX12 V11 Devices to OPenCL 1.2 + Khronos)

SiMD, AVX-256, AVX-512(bit) FPU(183Bit + 256 on Epyc Zen3)
Precision Double, Precision Single Float

Ray-Tracing SiMD (Such as PS5 & XBox & RX5770 :2019+)

PhysicsX (NVidia & CPU)

Also works for Thrust & Curvature motion & momentum.

Rupert S

(c)Rupert S https://science.n-helix.com

*

FSR-FL Magnifex3D(tm)RS

3d image Phase differentiation through differential : Magnifex3D(tm)RS

The objective of this phase is to create 2 objectives:

3D positioning & shape
Focus the image or sound impression

FSR-FL Calculations of diffraction do 2 things:

Focus the image around 0.00+-3
Calculate Distance & 3D Parameters though Differential Diffraction

The same can be stated of audio & the parameters are the same in effect.

3d image Phase differentiation through differential : Magnifex3D(tm) (c) Rupert S https://science.n-helix.com

3d image including distance : WEBB : During the watching of this video

James Webb Telescope shares first focused Image of star HD 84406
https://www.youtube.com/watch?v=-wo_AT8pR6o

It came to my attention that 18 segments obviously produce location specific data,
Additional calculations would be required to calculate distance though ARC

List

18 Diverse ANGLES

1 View

18 impressions of star HD 84406

Phase decouple a single frame per 17 produces a 3D image with distance...

Calculating the 18 mirror Angle differentials with slightly different data will create a 3D view,

For example of a chemical; A multiple angle refraction image results in a 3D image.

Common Usage : 3D

Magnifiers, Telescopes, Microscopes, Atomic Wave Analysis.

*

Research topic RS : https://is.gd/Dot5CodecGPU https://is.gd/CodecDolby https://is.gd/CodecHDR_WCG https://is.gd/HPDigitalWavelet https://is.gd/DisplaySourceCode

*

Utility of FSR-FL-RT
Minimal Process Compute
Fast FSR-Focal Length Ray-Tracing Code

Portable OpenCL
OpenCL may be ideal for TV & Device, Display & Audio rendering & Upscaling with integral POCCL Support

https://is.gd/DisplaySourceCode

https://aka.ms/clglcp-faq
http://portablecl.org/
https://github.com/pocl/pocl

https://apps.microsoft.com/store/detail/9NQPSL29BFFF?hl=en-us&gl=US

http://portablecl.org/downloads/pocl-3.0.tar.gz

Friday, February 18, 2022

Interrupt Entropy

NT Interrupt counter Entropy : A counter theory : RS


"more importantly, our
distribution is not 2-monotone like NT's, because in addition to the
cycle counter, we also include in those 4 words a register value, a
return address, and an inverted jiffies. (Whether capturing anything
beyond the cycle counter in the interrupt handler is even adding much of
value is a question for a different time.)"

NT Interrupt counter Entropy : A counter theory : RS

To be clear interrupts are old fashioned (NT & Bios) : Points

Network cards have offloading? Yes & why cannot we?

Offloaded does not mean that a time differential matrix HASH AES of 32Bit words,
Cross pollinated though MMX, AVX , SiMD is plausible!

Combined with even network latency timing & interrupt latency...

Various system differentials can alternate line in our table per clock sync!

In this reference Quartz clock instability is not only counter acted by NTP...
But also utilized as a variable co-modifier.

So why not also advantage ourselves of the clock frequency scaling effect to confuse odds again for Entropy (Random, Not Entropy)

SSD does also have a write counter & a cleared state, not so boring as one thinks if per 32KB segment is hashed in 4Bit, 8,Bit 32Bit float! (remember we have DOT3 DOT 4 & INT8 in ML)

We can utilize write cycle statistics & all hardware; Interrupts by themselves are rather Boring!

Computed timings on processes multiplexed over 3 Threads per group in competition is also a potential complexifier of Random

Rupert S

https://science.n-helix.com/2018/12/rng.html

https://science.n-helix.com/2022/02/rdseed.html

https://science.n-helix.com/2017/04/rng-and-random-web.html

https://science.n-helix.com/2022/02/interrupt-entropy.html

https://science.n-helix.com/2018/05/matrix-of-density.html

https://science.n-helix.com/2019/10/classic-physics.html

https://science.n-helix.com/2021/11/monticarlo-workload-selector.html

https://science.n-helix.com/2022/03/security-aspect-leaf-hash-identifiers.html

https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html

****

PreSEED Poly Elliptic SiMD RAND : RS


Preseed ; 3 Seeds with AES or Poly ChaCha or even 1 : 2 would be rather fast Init

Blending them would make a rather paranoid Kernel developer feel safe! :D

Like so List:

3 seeds 32Bit or 64Bit :
Examples :

1 Seed : Pre seeded from CPU IRQ & Net 16Bit values each & merged
2 & 3 from server https://pollinate.n-helix.com &or System TRNG

4 Seed mix 128Bit Value

Advantages :

AVX & SiMD Mixxer is fast 'Byte Swap & Maths etcetera" & MultiThreaded
AES Support is common :

*

HASH : RSA Source Cert C/TRNG : (c)RS


Elliptic RSA : Cert Mixer : RSA 4096/2048/1024Temporal : 384/256/192 ECC Temporal

Centric Entropy HASH: Butterfly Effects

ChaCha
SM4
SHA2
SHA3

Elliptic Encipher
AES
Poly ChaCha

Elliptic : Time Variance : Tick Count Variance : On & Off Variance : IRQ

*

Time & Crystal : Quartz as a diffraction point fractal differentiator : RS


RDTSC Variable bit differentiation & deviation of the quartz sub .0001 Value combined with complexity of unique interplay with Alternative clocks such as Network cards, Audio cards & USB Sticks & Bluetooth radio clocks & Ultimately the NTP Pools themselves when required.

(TIME Differential Float maths) TSC : RDTSC : RDTSCP : TCE supports single and half precision floating-point calculations

Security Relevant Extensions

SVM : Elliptic Curves & Polynomial graphs & function
AES : Advanced Encryption Standard Functions
AVX : 32Bit to 256Bit parallel Vector Mathematics
FPU : IEEE Float Maths
F16b : 16Bit to 32Bit Standards Floats
RDTSCP : Very high precision time & stamp

Processor features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 htt pni ssse3 fma cx16 sse4_1 sse4_2 popcnt aes f16c syscall nx lm avx svm sse4a osvw ibs xop skinit wdt lwp fma4 tce tbm topx page1gb rdtscp bmi1

32Bit SiMD Operations Available on AVX Per Cycle (A Thought on why 32Bit operations are good!)
(8Cores)8*32Bit SiMD(AVX) * 6(times per cycle) * 3600Mhz = 1,382,400 Operations Per Second

*

For RDTSCP = TValue TV1=16.0685 TV2=16.1432 TV3=15.1871
When Processor Mzh = PV1 PV2 PV3
RAND Source = Es1 Es2 Es3

If Xt = 1.9 < then roll right

((TV1 - TV2) * (PV1 - PV2)) / ((TV1 - TV3) * (PV1 - PV3)) = FractorXt(Xt)

Es1 * Xt = Differential

Es2 Es3

(c) Rupert S

Quartz as a diffraction point fractal differentiator : RS

https://science.n-helix.com/2022/02/interrupt-entropy.html

https://tches.iacr.org/index.php/TCHES/article/download/7274/6452
https://perso.univ-rennes1.fr/david.lubicz/articles/gda.pdf
https://patents.google.com/patent/US9335971
*

"Taking spinlocks from IRQ context is problematic for PREEMPT_RT. That
is, in part, why we take trylocks instead. But apparently this still
trips up various lock dependency analysers. That seems like a bug in the
analyser's that should be fixed, rather than having to change things
here.

But maybe there's another reason to change things up: by deferring the
crng pre-init loading to the worker, we can use the cryptographic hash
function rather than xor, which is perhaps a meaningful difference when
considering this data has only been through the relatively weak
fast_mix() function.

The biggest downside of this approach is that the pre-init loading is
now deferred until later, which means things that need random numbers
after interrupts are enabled, but before work-queues are running -- or
before this particular worker manages to run -- are going to get into
trouble. Hopefully in the real world, this window is rather small,
especially since this code won't run until 64 interrupts have occurred."

https://lore.kernel.org/lkml/Yhc4LwK3biZFIqwQ@owl.dominikbrodowski.net/T/

Rupert S

*

Asymmetry dev/random:

Explain it & code it please :D We most certainly know what Asymmetry is in PCI Transactions for GPU & Audio!

The high precision clock source is a CPU feature, but what one forgets is that other processors & network cards have Clock Crystals & So do local networks though the Ethernet Time Sync protocol, PCI Cards with Fast Sync, Repeaters & Boosters..

We need Asymmetric T/T2 or (T * T2)/T3 Etcetera
The main feature is a Timer & The Synchronicity of that timer; Being Asymmetric on time is a feature!

We laugh but yes Asymmetry Is a feature!
But we utilize the Asymmetry to provide CHAOS or Random Patterns,Not Precisely with a single Digit; We may? But we do not have to.

RDTSC is a logical choice for a processor; However our timers can also simply be a tick,
Network Ethernet, PCI-E, Audio BUS, HDD & SSD, Timing Sync Events,
In the case (Example) Network PCI Cards; They do indeed have a precise & variable clock..
In addition they have Network Traffic & Chaotic Packet IRQ; Timed IRQ & Offloaded IRQ & Data,
Also TLS Cypher packets; (Events Sometimes Offloaded & Sometimes not).

In a single System Time Crystals & Sync Events are simply the beginning of "The EventFul Day - Crypto"

Rupert S

Elliptic Curve Erratic Time Diffraction:


Relatively Subtle Timers, Clock Timers from NIC's or Statistical packet flows, Timer offsets & data flow Engrams & Anagrams & Flow patterns, Timers & Interrupts!

But real Timing & Sync Crystals are a work of real logic & Therefor potent in their Patterns & Powerfully influential on the Dynamic Maximum System Potential,

However played or used, Timers & Sync are the heart of a well centered Kye!

So as to timers & statistics; We do have to flow charts though ECC Elliptic Anonymizers.

We frequent the waters of personal & business & We do know so little from that,

Elliptic Curve Erratic Time Diffraction!

Unique Precise clocks & How many? Depends on how Expensive Your Mainframe is! Asymmetry dev/random: Explain it & code it please :D We most certainly know what Asymmetry is in PCI Transactions for GPU & Audio!

Rupert S

VMTGate2022:RS


What we are looking for essentially is 2 things:
Clock differential; As in speed & frequency shifts Electric signal variance,

The time shifting a number that does not guarantee forward (not obligatory),
For example a certificate ECC Elliptic that shifts 0.0005>6 to 4èéç=4 3fdé=5,

However a differential does Vary,

Still need system time to be precise (for Time NTP) & observations of differential are how we adjust..
Imprecision; Crystal Variance & imprecision is a core topic,
But we adapt imprecise results in NTP into precise ones.

Nanosecond TSC : RSTSCP
https://lkml.org/lkml/2022/4/25/57 

RS


[PATCH RFC v1 09/10] sparc: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"
[PATCH RFC v1 08/10] um: use sched_clock() for random_get_entropy( ... "Jason A. Donenfeld"
[PATCH RFC v1 07/10] arm64: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"
[PATCH RFC v1 06/10] x86: use sched_clock() for random_get_entropy ... "Jason A. Donenfeld"
[PATCH RFC v1 05/10] arm: use sched_clock() for random_get_entropy ... "Jason A. Donenfeld"
[PATCH RFC v1 04/10] mips: use sched_clock() for random_get_entrop ... "Jason A. Donenfeld"
[PATCH RFC v1 03/10] riscv: use sched_clock() for random_get_entro ... "Jason A. Donenfeld"
[PATCH RFC v1 02/10] m68k: use sched_clock() for random_get_entrop ... "Jason A. Donenfeld"
[PATCH RFC v1 01/10] random: use sched_clock() for random_get_entr ... "Jason A. Donenfeld"
[New] [PATCH RFC v1 00/10] archs/random: fallback to using sched_clock() ... "Jason A. Donenfeld"

https://lkml.org/lkml/2022/4/8/945
https://lkml.org/lkml/2022/4/8/946
https://lkml.org/lkml/2022/4/8/947
https://lkml.org/lkml/2022/4/8/948
https://lkml.org/lkml/2022/4/8/949
https://lkml.org/lkml/2022/4/8/950
https://lkml.org/lkml/2022/4/8/951
https://lkml.org/lkml/2022/4/8/952
https://lkml.org/lkml/2022/4/8/953
https://lkml.org/lkml/2022/4/8/954
https://lkml.org/lkml/2022/4/8/955

Timers
https://lkml.org/lkml/2022/4/9/459
https://lkml.org/lkml/2022/4/9/366

RDTSC
https://lkml.org/lkml/2022/4/9/482

Nanosecond TSC : RSTSCP
https://lkml.org/lkml/2022/4/25/57

*

Random : (Dynamic Elliptic Curve / T) * Factor Of T :

"Problems for Arm (32-bit), Motorola 68000 (M68k), Microblaze, SPARX32, Xtensa, and other niche architectures."

NoJitter - Initiating the dev/random ; Initiating Random with a SEED is the prospect I propose,
My personal Time Crystal RNG is based upon the variable clock rate principle of Quartz clock crystals & could potentially sound too regular.

However as we know very small variabilities in Super Stable Quartz crystals (Factory made) causes doubt,

However in the 0.005 or smaller range & Especially with variable frequencies & power input levels to controlled crystals; Creative Chaos Exists,

Particular market is motherboards that tweak frequencies to improve performance!

Clock rate variance is combined with a seed; As a Factoring agent & Again as a differentiator.

What Is a Factoring Differentiator ? a Math that shifts values subtly & therefor shifts our results from predictable to unpredictable; Well hard to!

The more effort we make; The harder it will be to see our Dynamic Elliptic Curve.

Rupert S

https://www.phoronix.com/scan.php?page=news_item&px=Linux-RNG-Opportunistic-urandom

*****

Serve C-TRNG QT Fractional Differentiator(c)RS


Server C/TRNG Quarts Time * Fractional differentiator : 8Bit, 16Bit, 32Bit, Float Int32 : Fractional Differentiator : fig-mantuary micro differentiator.


SipHash: a fast short-input PRF

Rotation Alignment : "The advantage of choosing such “aligned” rotation counts is that aligned rotation counts are much faster than unaligned rotation counts on many non-64-bit architectures."

http://cr.yp.to/siphash/siphash-20120918.pdf  

https://www.aumasson.jp/siphash/siphash.pdf

"Choice of rotation counts. Finding really bad rotation counts for ARX algorithms turns out to be difficult. For example, randomly setting all rotations in
BLAKE-512 or Skein to a value in {8, 16, 24, . . . , 56} may allow known attacks
to reach slightly more rounds, but no dramatic improvement is expected.
The advantage of choosing such “aligned” rotation counts is that aligned rotation counts are much faster than unaligned rotation counts on many non-64-bit
architectures. Many 8-bit microcontrollers have only 1-bit shifts of bytes, so
rotation by (e.g.) 3 bits is particularly expensive; implementing a rotation by
a mere permutation of bytes greatly speeds up ARX algorithms. Even 64-bit
systems can benefit from alignment, when a sequence of shift-shift-xor can be
replaced by SSSE3’s pshufb byte-shuffling instruction. For comparison, implementing BLAKE-256’s 16- and 8-bit rotations with pshufb led to a 20% speedup
on Intel’s Nehalem microarchitecture."

https://www.kernel.org/doc/html/latest/security/siphash.html

https://en.wikipedia.org/wiki/SipHash

Code SIP-HASH
https://github.com/veorq/SipHash

Serve C-TRNG QT Fractional Differentiator(c)RS

Server C/TRNG Quarts Time * Fractional differentiator : 8Bit, 16Bit, 32Bit, Float Int32 : Fractional Differentiator : fig-mantuary micro differentiator.

As we see rotation may benefact from the addition of Quartz crystal alignment sync data from 4 cycles & aligning data blocks,

Obviously we can pre share 4 64Bit blocks use use a pre seed AES/ChaCha Quad!
Indeed we can have 16 64Bit pre Seeds & chose them by time sync for kernel


Rupert S https://science.n-helix.com

*RAND OP Ubuntu : https://manpages.ubuntu.com/manpages/trusty/man1/pollinate.1.html

https://pollinate.n-helix.com

https://science.n-helix.com/2018/12/rng.html

https://science.n-helix.com/2022/02/rdseed.html

https://science.n-helix.com/2017/04/rng-and-random-web.html

https://science.n-helix.com/2021/11/monticarlo-workload-selector.html

https://science.n-helix.com/2022/02/visual-acuity-of-eye-replacements.html

https://science.n-helix.com/2022/02/interrupt-entropy.html

*

Encryption Methods:

https://tools.ietf.org/id/?doc=hash

https://tools.ietf.org/id/?doc=encrypt

HASH :


https://datatracker.ietf.org/doc/html/draft-ietf-cose-hash-algs

https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html

https://tools.ietf.org/id/?doc=sha

https://tools.ietf.org/id/?doc=rsa

Encryption Common Support:


https://tools.ietf.org/id/?doc=chacha

https://tools.ietf.org/id/?doc=aes

SM4e does seem a good possibility for C/T/RNG CORE HASH Functions!


ARM Crypto Extensions Code (Maybe AES Extensions would work here)
https://lkml.org/lkml/2022/3/15/324

ARM Neon / SiMD / AVX Compatible (GPU is possible)
https://lkml.org/lkml/2022/3/15/323


*

197 FIPS NIST Standards Specification C/T/RNG https://science.n-helix.com/2022/02/interrupt-entropy.html


Only a Neanderthal would approve a non additive source combination that is injected into the HASH & Re-HASHED ,

One does not Procreate inadequate RANDOM from a simple bias KERNEL, Hardware RNG's added together may add around 450% Complexity!

Hardware RNG devices MUST be able to Re-HASH to their 197 NIST Standards Specification, That is FINAL 2022 DT

KEYS: trusted: allow use of kernel RNG for key material

https://lkml.org/lkml/2022/3/16/598

CAAM PRNG Reference : https://lkml.org/lkml/2022/3/16/649